SEMICONDUCTOR TECHNICAL DATA The MC100LVEL92 is a triple PECL to LVPECL translator. The device receives standard PECL signals and translates them to differential LVPECL output signals. • • • • • 500ps Propagation Delays Fully Differential Design 20–Lead SOIC Package 5V and 3.3V Supplies Required 20 >1500V ESD 1 A PECL VBB output is provided for interfacing single ended PECL signals at the inputs. If a single ended PECL input is to be used the PECL VBB output should be connected to the D input and the active signal will drive the D input. When used the PECL VBB should be bypassed to ground via a 0.01µf capacitor. The PECL VBB is designed to act as a switching reference for the MC100LVEL92 under single ended input conditions, as a result the pin can only source/sink 0.5mA of current. DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-04 To accomplish the PECL to LVPECL level translation, the MC100LVEL92 requires three power rails. The VCC supply is to be connected to the standard PECL supply, the LVCC supply is to be connected to the LVPECL supply, and Ground is connected to the system ground plane. Both the VCC and LVCC should be bypassed to ground with a 0.01µf capacitor. Under open input conditions, the D input will be biased at a VCC/2 voltage level and the D input will be pulled to ground. This condition will force the “Q” output low, ensuring stability. Logic Diagram and Pinout: 20-Lead SOIC (Top View) VCC Q0 Q0 LVCC Q1 Q1 LVCC Q2 Q2 VCC 20 19 18 17 16 15 14 13 12 11 LVPECL LVPECL LVPECL PECL PECL PECL 1 2 3 4 5 6 7 8 9 10 VCC D0 D0 PECL VBB D1 D1 PECL VBB D2 D2 GND PIN NAMES Pins Function Dn Qn VBB LVCC VCC GND PECL Inputs LVPECL Outputs PECL Reference Voltage Output VCC for LVPECL Output VCC for PECL Inputs Common Ground Rail 7/97 Motorola, Inc. 1997 4–1 REV 2 MC100LVEL92 PECL INPUT DC CHARACTERISTICS –40°C Symbol Characteristic Min VCC Power Supply Voltage 4.5 IIH Input HIGH Current IIL Input LOW Current VPP 0°C Max Min 5.5 4.5 150 25°C Max Min 5.5 4.5 85°C Typ Max Min 5.5 4.5 150 Max 150 Unit 5.5 V 150 µA Condition 0.5 –600 0.5 –600 0.5 –600 0.5 –600 µA Minimum Peak-to-Peak Input1 150 150 150 150 mV VIH Input HIGH Voltage2 3835 4120 3835 4120 3835 4120 3835 4120 mV VCC = 5.0V VIL Input LOW Voltage2 3190 3515 3190 3525 3190 3525 3190 3525 mV VCC = 5.0V VBB Reference Output2 3620 3740 3620 3740 3620 3740 3620 3740 mV VCC = 5.0V IVCC Power Supply Current 12 mA Dn Dn 12 12 8.0 12 1. 150mV input guarantees full logic swing at the output. 2. DC levels vary 1:1 with VCC. LVPECL OUTPUT DC CHARACTERISTICS –40°C Symbol 0°C 25°C 85°C Characteristic Min Max Min Max Min Typ Max Min Max Unit VCC Power Supply Voltage 3.0 3.8 3.0 3.8 3.0 3.3 3.8 3.0 3.8 V VOH Output HIGH Voltage3 2.215 2.42 2.275 2.42 2.275 2.35 2.42 2.275 2.42 V VCC = 3.3V VOL Output LOW Voltage3 1.47 1.745 1.49 1.68 1.49 1.60 1.68 1.49 1.68 V VCC = 3.3V 15 20 21 mA IGND Power Supply Current 3. DC levels will vary 1:1 with VCC. 20 20 Condition MC100LVEL92 AC CHARACTERISTICS (LVCC = 3.0V to 3.8V; VCC = 4.5V to 5.5V) –40°C Symbol Characteristic Diff S.E. 0°C 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit 490 440 590 590 690 740 510 460 610 610 710 760 510 460 610 610 710 760 530 480 630 630 730 780 ps 20 20 25 100 200 20 20 25 100 200 20 20 25 100 200 20 20 25 100 200 ps tPLH tPHL Propagation Delay D to Q tSKEW Skew Output–to–Output4 Part–to–Part (Diff)4 Duty Cycle (Diff)5 VPP Minimum Input Swing6 150 VCMR Common Mode Range7 VPP < 500mV 1.3 VCC –0.2 1.2 VCC –0.2 1.2 VCC –0.2 1.2 VCC –0.2 VPP ≥ 500mV 1.5 VCC –0.2 1.4 VCC –0.2 1.4 VCC –0.2 1.4 VCC –0.2 150 150 150 mV V tr Output Rise/Fall Times Q 320 580 320 580 320 580 320 580 ps tf (20% – 80%) 4. Skews are valid across specified voltage range, part–to–part skew is for a given temperature. 5. Duty cycle skew is the difference between a TPLH and TPHL propagation delay through a device.Common Mode Range 6. Minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40. 7. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1V. MOTOROLA 4–2 ECLinPS and ECLinPS Lite DL140 — Rev 3 MC100LVEL92 OUTLINE DIMENSIONS DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D–04 ISSUE E –A – 20 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 1 –B – P 10 PL A B 0.010 (0.25) M B M 10 D 20 PL 0.010 (0.25) J M T S S F R X 45° C –T G 18 PL K SEATING – PLANE M DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0° 7° 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0° 7° 0.395 0.415 0.010 0.029 Motorola reserves the right to make changes without further notice to any products herein. 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