ONSEMI MC74LVX374DW

SEMICONDUCTOR TECHNICAL DATA
# " ! ! ! LVX
The MC74LVX374 is an advanced high speed CMOS octal D–type
flip–flop with 3–state outputs. The inputs tolerate voltages up to 7V,
allowing the interface of 5V systems to 3V systems.
This 8–bit D–type flip–flop is controlled by a clock input and an output
enable input. When the output enable input is high, the eight outputs are
in a high impedance state.
•
•
•
•
•
•
•
•
LOW–VOLTAGE CMOS
High Speed: fmax = 160MHz (Typ) at VCC = 3.3V
Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C
Power Down Protection Provided on Inputs
DW SUFFIX
20–LEAD SOIC PACKAGE
CASE 751D–04
Balanced Propagation Delays
Low Noise: VOLP = 0.8V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
VCC
O7
D7
D6
O6
O5
D5
D4
O4
CP
20
19
18
17
16
15
14
13
12
11
DT SUFFIX
20–LEAD TSSOP PACKAGE
CASE 948E–02
M SUFFIX
20–LEAD SOIC EIAJ PACKAGE
CASE 967–01
1
2
3
4
5
6
7
8
9
10
OE
O0
D0
D1
O1
O2
D2
D3
O3
GND
Figure 1. 20–Lead Pinout (Top View)
PIN NAMES
Pins
Function
OE
CP
D0–D7
O0–O7
Output Enable Input
Clock Pulse Input
Data Inputs
3–State Outputs
6/97
 Motorola, Inc. 1997
1
REV 0
MC74LVX374
OE
CP
1
11
2
nCP
3
O0
Q
D0
D
5
nCP
4
O1
Q
D1
D
6
nCP
7
O2
Q
D2
D
9
nCP
8
O3
Q
D3
D
12
nCP
13
O4
Q
D4
D
15
nCP
14
O5
Q
D5
D
16
nCP
17
O6
Q
D6
D
19
nCP
18
O7
Q
D7
D
Figure 2. Logic Diagram
INPUTS
OUTPUTS
OE
CP
Dn
On
OPERATING MODE
L
L
↑
↑
l
h
L
H
Load and Read Register
L
↑
X
NC
Hold and Read Register
H
↑
X
Z
Hold and Disable Outputs
H
H
↑
↑
l
h
Z
Z
Load Internal Register and Disable Outputs
H = High Voltage Level; h = High Voltage Level One Setup Time Prior to the Low–to–High Clock Transition; L = Low
Voltage Level; l = Low Voltage Level One Setup Time Prior to the Low–to–High Clock Transition; NC = No Change, State
Prior to Low–to–High Clock Transition; X = High or Low Voltage Level and Transitions are Acceptable; Z = High
Impedance State; ↑ = Low–to–High Transition; ↑ = Not a Low–to–High Transition; For ICC Reasons DO NOT FLOAT
Inputs
MOTOROLA
2
LCX DATA
BR1339 — REV 3
MC74LVX374
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MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage
–0.5 to +7.0
V
Vin
DC Input Voltage
–0.5 to +7.0
V
Vout
DC Output Voltage
–0.5 to VCC +0.5
V
IIK
Input Diode Current
–20
mA
IOK
Output Diode Current
±20
mA
Iout
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
±75
mA
PD
Power Dissipation
180
mW
Tstg
Storage Temperature
–65 to +150
_C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is
not implied.
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RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage
2.0
3.6
V
Vin
DC Input Voltage
0
5.5
V
Vout
DC Output Voltage
0
VCC
V
TA
Operating Temperature, All Package Types
–40
+85
_C
∆t/∆V
Input Rise and Fall Time
0
100
ns/V
DC ELECTRICAL CHARACTERISTICS
S b l
Symbol
P
Parameter
T
Test
C
Conditions
di i
Min
1.5
2.0
2.4
VIH
High–Level Input Voltage
2.0
3.0
3.6
VIL
Low–Level Input Voltage
2.0
3.0
3.6
VOH
High–Level Output Voltage
(Vin = VIH or VIL)
IOH = –50µA
IOH = –50µA
IOH = –4mA
2.0
3.0
3.0
VOL
Low–Level Output Voltage
(Vin = VIH or VIL)
IOL = 50µA
IOL = 50µA
IOL = 4mA
2.0
3.0
3.0
Iin
Input Leakage Current
Vin = 5.5V or GND
IOZ
Maximum Three–State
Leakage Current
ICC
Quiescent Supply Current
LCX DATA
BR1339 — REV 3
TA = 25°C
VCC
V
Typ
TA = – 40 to 85°C
Max
Min
1.5
2.0
2.4
0.5
0.8
0.8
1.9
2.9
2.58
Max
2.0
3.0
V
0.5
0.8
0.8
1.9
2.9
2.48
V
V
0.1
0.1
0.36
0.1
0.1
0.44
V
3.6
±0.1
±1.0
µA
Vin = VIL or VIH
Vout = VCC or GND
3.6
±0.25
±2.5
µA
Vin = VCC or GND
3.6
4.0
40.0
µA
3
0.0
0.0
U i
Unit
MOTOROLA
MC74LVX374
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AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°C
S b l
Symbol
fmax
tPLH,
tPHL
tPZL,
tPZH
tPLZ,
tPHZ
tOSHL
tOSLH
P
Parameter
Maximum Clock Frequency
(50% Duty Cycle)
Propagation Delay
CP to O
Output Enable Time
OE to O
Output Disable Time
OE to O
Output–to–Output Skew
(Note 1.)
T
Test
C
Conditions
di i
Min
Typ
TA = – 40 to 85°C
Max
Min
Max
VCC = 2.7V
CL = 15pF
CL = 50pF
60
45
115
60
50
40
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
100
60
160
95
85
55
VCC = 2.7V
CL = 15pF
CL = 50pF
8.5
11.0
16.3
19.8
1.0
1.0
19.5
23.0
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
6.7
9.2
10.6
14.1
1.0
1.0
12.5
16.0
VCC = 2.7V
RL = 1kΩ
CL = 15pF
CL = 50pF
7.6
10.1
14.5
18.0
1.0
1.0
17.5
21.0
VCC = 3.3 ± 0.3V
RL = 1kΩ
CL = 15pF
CL = 50pF
5.9
8.4
9.3
12.8
1.0
1.0
11.0
14.5
VCC = 2.7V
RL = 1kΩ
CL = 50pF
11.5
18.5
1.0
22.0
VCC = 3.3 ± 0.3V
RL = 1kΩ
CL = 50pF
9.6
13.2
1.0
15.0
VCC = 2.7V
VCC = 3.3 ±0.3V
CL = 50pF
CL = 50pF
U i
Unit
MHz
1.5
1.5
1.5
1.5
ns
ns
ns
ns
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (tOSHL) or LOW–to–HIGH (tOSLH); parameter
guaranteed by design.
CAPACITIVE CHARACTERISTICS
TA = 25°C
S b l
Symbol
P
Parameter
Min
TA = – 40 to 85°C
Typ
Max
10
Min
Max
U i
Unit
10
pF
Cin
Input Capacitance
4
Cout
Maximum Three–State Output Capacitance
6
pF
CPD
Power Dissipation Capacitance (Note 2.)
32
pF
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per flip–flop). CPD is used to determine the
no–load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 3.3V, Measured in SOIC Package)
TA = 25°C
S b l
Symbol
Typ
Max
U i
Unit
VOLP
Quiet Output Maximum Dynamic VOL
Ch
Characteristic
i i
0.5
0.8
V
VOLV
Quiet Output Minimum Dynamic VOL
–0.5
–0.8
V
VIHD
Minimum High Level Dynamic Input Voltage
2.0
V
VILD
Maximum Low Level Dynamic Input Voltage
0.8
V
MOTOROLA
4
LCX DATA
BR1339 — REV 3
MC74LVX374
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
TA = 25°C
Symbol
S b l
Parameter
P
Test
Conditions
T
C
di i
TA = – 40
to 85°C
Limit
Limit
Unit
U i
tw
Minimum Pulse Width, CP
VCC = 2.7V
VCC = 3.3 ±0.3V
7.5
5.0
8.0
5.5
ns
tsu
Minimum Setup Time, D to CP
VCC = 2.7V
VCC = 3.3 ±0.3V
6.5
4.5
6.5
4.5
ns
th
Minimum Hold Time, D to CP
VCC = 2.7V
VCC = 3.3 ±0.3V
2.0
2.0
2.0
2.0
ns
Typ
SWITCHING WAVEFORMS
VCC
OE
VCC
CP
50%
GND
50%
tPZL
GND
tW
tPLH
O
HIGH
IMPEDANCE
50% VCC
O
1/fmax
tPLZ
VOL +0.3V
tPHL
tPZH
50% VCC
tPHZ
VOH –0.3V
O
50% VCC
Figure 3.
HIGH
IMPEDANCE
Figure 4.
VALID
VCC
50%
D
GND
th
tsu
VCC
CP
50%
GND
Figure 5.
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
DEVICE
UNDER
TEST
CL*
* Includes all probe and jig capacitance
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
* Includes all probe and jig capacitance
Figure 6. Propagation Delay Test Circuit
LCX DATA
BR1339 — REV 3
1 kΩ
Figure 7. Three–State Test Circuit
5
MOTOROLA
MC74LVX374
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–04
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
–A–
20
11
–B–
10X
P
0.010 (0.25)
1
M
B
M
10
20X
D
0.010 (0.25)
T A
M
B
S
DIM
A
B
C
D
F
G
J
K
M
P
R
J
S
F
R X 45 _
C
–T–
G
18X
SEATING
PLANE
MILLIMETERS
MIN
MAX
12.65
12.95
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0_
7_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.499
0.510
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0_
7_
0.395
0.415
0.010
0.029
M
K
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
20X
0.15 (0.006) T U
K REF
0.10 (0.004)
S
M
T U
S
V
S
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
K
K1
2X
L/2
20
11
J J1
B
–U–
L
PIN 1
IDENT
SECTION N–N
1
10
0.25 (0.010)
N
0.15 (0.006) T U
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
M
A
–V–
N
F
DETAIL E
–W–
C
D
G
H
DETAIL E
0.100 (0.004)
–T– SEATING
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
PLANE
MOTOROLA
6
LCX DATA
BR1339 — REV 3
MC74LVX374
OUTLINE DIMENSIONS
M SUFFIX
PLASTIC SOIC EIAJ PACKAGE
CASE 967–01
ISSUE O
20
NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2 CONTROLLING DIMENSION: MILLIMETER.
3 DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4 TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5 THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
11
Q1
E HE
1
M_
L
10
DETAIL P
Z
D
VIEW P
e
A
c
A1
b
0.13 (0.005)
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
–––
2.05
0.05
0.20
0.35
0.50
0.18
0.27
12.35
12.80
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
–––
0.81
INCHES
MIN
MAX
–––
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.486
0.504
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
–––
0.032
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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– US & Canada ONLY 1–800–774–1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
INTERNET: http://motorola.com/sps
◊
LCX DATA
BR1339 — REV 3
7
MC74LVX374/D
MOTOROLA