ONSEMI MGSF2P02HDT1

MGSF2P02HD
Power MOSFET
2 Amps, 20 Volts
P−Channel TSOP−6
This device represents a series of Power MOSFETs which are
capable of withstanding high energy in the avalanche and
commutation modes and the drain−to−source diode has a very low
reverse recovery time. These devices are designed for use in low
voltage, high speed switching applications where power efficiency is
important. Typical applications are dc−dc converters, and power
management in portable and battery powered products such as
computers, printers, cellular and cordless phones. They can also be
used for low voltage motor controls in mass storage products such as
disk drives and tape drives. The avalanche energy is specified to
eliminate the guesswork in designs where inductive loads are switched
and offer additional safety margin against unexpected voltage
transients.
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VDSS
RDS(ON) TYP
ID MAX
20 V
175 mΩ
2.0 A
P−Channel
1 2 5 6
3
Features
• Miniature TSOP−6 Surface Mount Package − Saves Board Space
• Low Profile for Thin Applications such as PCMCIA Cards
• Very Low RDS(on) Provides Higher Efficiency and Expands
•
•
•
•
•
•
4
MARKING
DIAGRAM
Battery Life
Logic Level Gate Drive − Can Be Driven by Logic ICs
Diode is Characterized for Use in Bridge Circuits
Diode Exhibits High Speed, with Soft Recovery
IDSS Specified at Elevated Temperatures
Avalanche Energy Specified
Package Mounting Information Provided
1
3V
W
TSOP−6
CASE 318G
STYLE 1
3V
W
= Device Code
= Work Week
PIN ASSIGNMENT
Drain Drain Source
6
5
4
1
2
3
Drain Drain Gate
ORDERING INFORMATION
Device
Package
Shipping†
MGSF2P02HDT1
TSOP−6
3000 Tape & Reel
MGSF2P02HDT3
TSOP−6
10,000 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
 Semiconductor Components Industries, LLC, 2004
April, 2004 − Rev. 2
1
Publication Order Number:
MGSF2P02HD/D
MGSF2P02HD
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
20
V
Drain−to−Gate Voltage (RGS = 1.0 MΩ)
VDGR
20
V
VGS
±9
V
ID
A
Gate−to−Source Voltage
Drain Current − Continuous
Drain Current − Single Pulse (tp ≤ 10 s)
Total Power Dissipation @ TC = 25°C
Total Power Dissipation @ TC = 85°C
Thermal Resistance − Junction to Ambient (Note 1.)
IDM
PD
PD
RJA
1.3
10
400
210
312
Drain Current − Continuous
Drain Current − Single Pulse (tp ≤ 10 s)
Total Power Dissipation @ TC = 25°C
Total Power Dissipation @ TC = 85°C
Thermal Resistance − Junction to Ambient (Note 2.)
ID
IDM
PD
PD
RJA
2.9
15
2.0
1.0
62.5
W
W
°C/W
TJ, Tstg
− 55 to 150
°C
Operating and Storage Temperature Range
Single Pulse Drain Source Avalanche Energy VDD = 20 V, VGS = 4.5 Vpk,
IL = 3.6 Apk, L = 25 mH, RG = 25 EAS
mW
mW
°C/W
A
mJ
160
THERMAL CHARACTERISTICS
Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 5 seconds
TL
1. Minimum FR−4 or G−10 PCB, Operating to Steady State.
2. Mounted onto a 2″ square FR−4 Board (1″ sq. 2 oz. Cu 0.06″ thick single sided), Operating time ≤5 seconds.
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2
260
°C
MGSF2P02HD
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Symbol
Characteristic
Min
Typ
Max
20
−
−
−
−
−
−
1.0
10
−
−
± 100
0.7
−
0.95
2.2
1.4
−
−
−
145
220
175
280
1.3
2.0
−
Ciss
−
225
−
Coss
−
150
−
Crss
−
60
−
td(on)
−
15
−
tr
−
27
−
td(off)
−
60
−
tf
−
72
−
td(on)
−
20
−
tr
−
94
−
td(off)
−
49
−
tf
−
76
−
QT
−
5.3
7.5
Q1
−
0.7
−
Q2
−
2.6
−
Q3
−
1.9
−
−
−
0.89
0.72
1.1
−
trr
−
86
−
ta
−
27
−
tb
−
59
−
QRR
−
0.115
−
Unit
OFF CHARACTERISTICS
V(BR)DSS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Zero Gate Voltage Drain Current
(VDS = 20 Vdc, VGS = 0 Vdc)
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate−to−Source Leakage Current
(VGS = ± 9.0 Vdc, VDS = 0 Vdc)
IGSS
Vdc
A
nAdc
ON CHARACTERISTICS
Gate Threshold Voltage
(VDS = VGS, ID = 0.25 mAdc)
Temperature Coefficient (Negative)
VGS(th)
Drain−to−Source On−Voltage
(VGS = 4.5 Vdc, ID = 1.3 Adc)
(VGS = 2.7 Vdc, ID = 0.8 Adc)
RDS(on)
Forward Transconductance
(VDS = 10 Vdc, ID = 0.6 Adc)
gFS
Vdc
mV/°C
m
mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 15 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)
Transfer Capacitance
pF
SWITCHING CHARACTERISTICS
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDS = 10 Vdc, ID = 1.2 Adc,
VGS = 4.5
4 5 Vdc,
Vdc
RG = 6.0 Ω)
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 10 Vdc, ID = 0.6 Adc,
VGS = 2.7
2 7 Vdc,
Vdc
RG = 6.0 Ω)
Fall Time
Gate Charge
(VDS = 16 Vdc, ID = 1.2 Adc,
VGS = 4.5 Vdc)
nsec
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
VSD
(IS = 1.2 Adc, VGS = 0 Vdc)
Reverse Recovery Time
(IS = 1.2 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
NOTE: Pulse Test: Pulse Width ≤ 300 s, Duty Cycle ≤ 2%.
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3
Vdc
nsec
C
MGSF2P02HD
TYPICAL ELECTRICAL CHARACTERISTICS
4.0
4.0
VGS = 8.0 V
ID , DRAIN CURRENT (AMPS)
TJ = 25°C
2.9 V
ID , DRAIN CURRENT (AMPS)
VDS ≥ 10 V
3.1 V
4.5 V
3.0
2.7 V
3.7 V
2.5 V
3.3 V
2.0
2.3 V
2.1 V
1.0
3.0
2.0
1.0
TJ = − 55°C
0
0
0
0.4
0.8
1.2
1.6
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0
2.0
1.0
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
0.2
0.1
0
2.0
6.0
4.0
8.0
10
0.6
TJ = 25°C
0.5
0.4
VGS = 2.7 V
0.3
0.2
4.5 V
0.1
0
0
1.0
2.0
3.0
4.0
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
100
2.0
VGS = 4.5 V
ID = 0.8 A
TJ = 125°C
1.5
IDSS , LEAKAGE (nA)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
ID = 1.3 A
TJ = 25°C
0
4.0
Figure 2. Transfer Characteristics
0.4
0.3
3.0
2.0
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
25°C
100°C
1.9 V
1.7 V
1.0
100°C
10
1.0
0.5
25°C
VGS = 0 V
0.1
0
−50
−25
0
25
50
75
100
125
0
150
4.0
8.0
12
16
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance versus Temperature
Figure 6. Drain−To−Source Leakage Current
versus Voltage
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4
20
MGSF2P02HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (∆t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
800
C, CAPACITANCE (pF)
Ciss
VDS = 0 V
VGS = 0 V
TJ = 25°C
600
Crss
400
Ciss
200
Coss
Crss
0
−10
0
VGS
10
VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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5
20
1000
20
QT
4.0
VGS
VDS
16
3.0
12
Q1
Q2
2.0
8.0
ID = 1.2 A
TJ = 25°C
1.0
4.0
Q3
0
1.0
0
2.0
3.0
4.0
5.0
0
6.0
VDD = 10 V
ID = 1.2 A
VGS = 4.5 V
TJ = 25°C
t, TIME (ns)
5.0
VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
MGSF2P02HD
100
tf
td(off)
tr
td(on)
10
1.0
QG, TOTAL GATE CHARGE (nC)
10
100
RG, GATE RESISTANCE (OHMS)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
high di/dts. The diode’s negative di/dt during ta is directly
controlled by the device clearing the stored charge.
However, the positive di/dt during tb is an uncontrollable
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of tb/ta serves as a good indicator of recovery
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter trr), have less stored charge and a softer
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, trr, due
to the storage of minority carrier charge, QRR, as shown in
the typical reverse recovery wave form of Figure 11. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short trr and low QRR specifications to
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
2.0
di/dt = 300 A/µs
1.6
Standard Cell Density
trr
High Cell Density
trr
tb
ta
I S , SOURCE CURRENT
IS, SOURCE CURRENT (AMPS)
VGS = 0 V
TJ = 25°C
1.2
0.8
0.4
0
0.4
0.5
0.6
0.7
0.8
0.9
1.0
t, TIME
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 11. Reverse Recovery Time (trr)
Figure 10. Diode Forward Voltage versus Current
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6
MGSF2P02HD
TYPICAL ELECTRICAL CHARACTERISTICS
1.0
TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
0.5
0.2
0.1
0.1
P(pk)
0.05
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
RθJC(t) = r(t) RθJC
TJ(pk) − TC = P(pk) RθJC(t)
t1
0.02
t2
0.01
DUTY CYCLE, D = t1/t2
0.01
0.0001
0.001
0.01
0.1
t, TIME (s)
1.0
Figure 12. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 13. Diode Reverse Recovery Waveform
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7
10
100
MGSF2P02HD
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE L
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
A
L
6
S
1
5
4
2
3
B
MILLIMETERS
DIM MIN
MAX
A
2.90
3.10
B
1.30
1.70
C
0.90
1.10
D
0.25
0.50
G
0.85
1.05
H 0.013 0.100
J
0.10
0.26
K
0.20
0.60
L
1.25
1.55
M
0
10 S
2.50
3.00
D
G
M
J
C
0.05 (0.002)
K
H
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
INCHES
MIN
MAX
0.1142 0.1220
0.0512 0.0669
0.0354 0.0433
0.0098 0.0197
0.0335 0.0413
0.0005 0.0040
0.0040 0.0102
0.0079 0.0236
0.0493 0.0610
0
10 0.0985 0.1181
DRAIN
DRAIN
GATE
SOURCE
DRAIN
DRAIN
SOLDERING FOOTPRINT*
2.4
0.094
1.9
0.075
0.95
0.037
0.95
0.037
0.7
0.028
1.0
0.039
SCALE 10:1
mm inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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Phone: 81−3−5773−3850
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For additional information, please contact your
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MGSF2P02HD/D