MTP10N10EL Preferred Device Power MOSFET 10 A, 100 V, Logic Level, N−Channel TO−220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain−to−source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. http://onsemi.com 10 A, 100 V RDS(on) = 0.22 Features N−Channel • Avalanche Energy Specified • Source−to−Drain Diode Recovery Time Comparable to a Discrete • • • D Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature Pb−Free Package is Available G S MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−to−Source Voltage VDSS 100 Vdc Drain−to−Gate Voltage (RGS = 1.0 M) VDGR 100 Vdc Gate−to−Source Voltage − Continuous − Non−Repetitive (tp ≤ 10 ms) VGS VGSM ± 15 ± 20 Vdc Vpk ID ID 10 6.0 35 Adc 40 0.32 1.75 Watts W/°C Watts −55 to 150 °C Drain Current − Continuous @ TC = 25°C − Continuous @ TC = 100°C − Single Pulse (tp ≤ 10 s) Total Power Dissipation @ TC = 25°C Derate above 25°C Total Power Dissipation @ TC = 25°C (Note 1) Operating and Storage Temperature Range Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 10 Adc, L = 1.0 mH, RG = 25 ) Thermal Resistance − Junction−to−Case° − Junction−to−Ambient − Junction−to−Ambient (Note 1) Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 secs IDM PD TJ, Tstg Apk EAS mJ 50 °C/W RJC RJA RJA 3.13 100 71.4 TL 260 °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. When surface mounted to an FR4 board using the minimum recommended pad size. Semiconductor Components Industries, LLC, 2005 March, 2005 − Rev. 4 1 MARKING DIAGRAM & PIN ASSIGNMENT 4 1 2 4 Drain TO−220AB CASE 221A STYLE 5 3 MTP10N10EL LLYWW 1 Gate 3 Source 2 Drain MTP10N10EL LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device Package Shipping MTP10N10EL TO−220AB 50 Units/Rail MTP10N10ELG TO−220AB (Pb−Free) 50 Units/Rail *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Preferred devices are recommended choices for future use and best overall value. Publication Order Number: MTP10N10EL/D MTP10N10EL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 100 − − 115 − − − − − − 10 100 − − 100 1.0 − 1.45 4.0 2.0 − mV/°C − 0.17 0.22 Ohm − − 1.85 − 2.6 2.3 FS 5.0 7.9 − mhos pF OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 100 Vdc, VGS = 0 Vdc)° (VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125°C) IDSS Gate−Body Leakage Current (VGS = ±15 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C Adc nAdc ON CHARACTERISTICS (Note 2) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (VGS = 5.0 Vdc, ID = 5.0 Adc) RDS(on) Drain−to−Source On−Voltage (VGS = 5.0 Vdc, ID = 10 Adc)° (VGS = 5.0 Vdc, ID = 5.0 Adc, TJ = 125°C) VDS(on) g Forward Transconductance (VDS = 8.0 Vdc, ID = 5.0 Adc) Vdc Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, Vd VGS = 0 Vdc, Vd f=1 1.0 0 MHz) Output Capacitance Reverse Transfer Capacitance Ciss − 741 1040 Coss − 175 250 Crss − 18.9 40 td(on) − 11 20 tr − 74 150 td(off) − 17 30 SWITCHING CHARACTERISTICS (Note 3) Turn−On Delay Time Rise Time (VDD = 50 Vdc, ID = 10 Adc, VGS = 5.0 Vdc, Rg = 9.1 )) Turn−Off Delay Time Fall Time Gate Charge (See Figure 8) (VDS = 80 Vdc, ID = 10 Adc, VGS = 5.0 Vdc)) tf − 38 80 QT − 9.3 15 Q1 − 2.56 Q2 − 4.4 − Q3 − 4.6 − − − 0.98 0.898 1.6 − trr − 124.7 − ta − 86 − tb − 38.7 − QRR − 0.539 − − 4.5 − − 7.5 − ns nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (Note 2) (IS = 10 Adc, VGS = 0 Vdc) (IS = 10 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse e e se Recovery eco e y Time e Adc VGS = 0 Vdc, Vdc (IS = 10 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc nss C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25″ from package to center of die) Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad.) 2. Pulse Test: Pulse Width ≤ 300 s, Duty Cycle ≤ 2.0%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 2 Ld nH Ls MTP10N10EL TYPICAL ELECTRICAL CHARACTERISTICS 20 7V VGS = 10 V TJ = 25°C VDS ≥ 5 V 5V ID , DRAIN CURRENT (AMPS) ID , DRAIN CURRENT (AMPS) 20 4.5 V 15 4V 10 3.5 V 5 3V −55°C 15 25°C TJ = 100°C 10 5 2V 0 0 1 2 4 3 0 5 1 2 3 4 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.35 Figure 2. Transfer Characteristics VGS = 5 V 100°C 0.25 TJ = 25°C 0.15 −55°C 0.05 0 5 10 15 20 RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) Figure 1. On−Region Characteristics 0.25 TJ = 25°C VGS = 5 V 0.2 10 V 0.15 0.1 0 5 ID, DRAIN CURRENT (AMPS) 10 15 20 ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Drain Current and Temperature Figure 4. On−Resistance versus Drain Current and Gate Voltage 2 100 VGS = 5 V ID = 5 A VGS = 0 V TJ = 125°C 1.5 I DSS , LEAKAGE (nA) RDS(on) , DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 5 1 0.5 0 − 50 − 25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 10 100°C 1 150 0 Figure 5. On−Resistance Variation with Temperature 80 20 40 60 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 6. Drain−To−Source Leakage Current versus Voltage http://onsemi.com 3 100 MTP10N10EL POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 1800 1600 VDS = 0 V VGS = 0 V TJ = 25°C Ciss C, CAPACITANCE (pF) 1400 1200 1000 800 Ciss Crss 600 400 Coss 200 0 10 Crss 5 0 VGS 5 10 15 20 25 VDS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 4 90 12 QT 75 VGS 8 60 45 0 Q2 Q1 4 VDS Q3 0 2 30 TJ = 25°C ID = 10 A 4 6 8 15 0 10 1000 VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS) t, TIME (ns) VGS , GATE−TO−SOURCE VOLTAGE (VOLTS) MTP10N10EL TJ = 25°C ID = 10 A VDS = 100 V VGS = 5 V 100 tr tf td(off) td(on) 10 1 1 10 100 RG, GATE RESISTANCE (OHMS) QG, TOTAL GATE CHARGE (nC) Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS I S , SOURCE CURRENT (AMPS) 10 VGS = 0 V TJ = 25°C 8 6 4 2 0 0.5 0.6 0.7 0.8 0.9 1.0 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance−General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RJC). A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. http://onsemi.com 5 MTP10N10EL I D , DRAIN CURRENT (AMPS) 100 EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) SAFE OPERATING AREA VGS = 20 V SINGLE PULSE TC = 25°C 10 s 10 100 s 1 ms 1 10 ms dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 1 10 50 ID = 10A 40 30 20 10 0 100 25 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area 150 Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 D = 0.5 0.2 0.1 0.1 0.05 P(pk) 0.02 t1 0.01 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 0.01 0.00001 0.0001 0.001 0.01 0.1 t, TIME (SECONDS) Figure 13. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 6 RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RJC(t) 1 10 MTP10N10EL PACKAGE DIMENSIONS TO−220 THREE−LEAD TO−220AB CASE 221A−09 ISSUE AA SEATING PLANE −T− B C F T S 4 A Q 1 2 3 DIM A B C D F G H J K L N Q R S T U V Z U H K Z L R V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. J G D N INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 −−− −−− 0.080 STYLE 5: PIN 1. 2. 3. 4. http://onsemi.com 7 GATE DRAIN SOURCE DRAIN MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 −−− −−− 2.04 MTP10N10EL ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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