NTMD4N03, NVMD4N03 Power MOSFET 4 A, 30 V, N−Channel SO−8 Dual Features • Designed for use in low voltage, high speed switching applications • Ultra Low On−Resistance Provides • • • • • Applications • • • • • http://onsemi.com Higher Efficiency and Extends Battery Life − RDS(on) = 0.048 W, VGS = 10 V (Typ) − RDS(on) = 0.065 W, VGS = 4.5 V (Typ) Miniature SO−8 Surface Mount Package − Saves Board Space Diode is Characterized for Use in Bridge Circuits Diode Exhibits High Speed, with Soft Recovery NVMD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable* These Devices are Pb−Free and are RoHS Compliant VDSS RDS(ON) Typ ID Max 30 V 48 mW @ VGS = 10 V 4.0 A N−Channel D D G DC−DC Converters Computers Printers Cellular and Cordless Phones Disk Drives and Tape Drives G S MARKING DIAGRAM* AND PIN ASSIGNMENT 8 D1 D1 D2 D2 1 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−to−Source Voltage VDSS 30 V Gate−to−Source Voltage − Continuous VGS "20 V Drain Current − Continuous @ TA = 25°C − Single Pulse (tp ≤ 10 ms) ID IDM 4.0 12 Adc Apk PD 2.0 W TJ, Tstg −55 to +150 °C Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 4.45 Apk, L = 8 mH, RG = 25 W) EAS 80 mJ Thermal Resistance − Junction−to−Ambient (Note 1) RqJA 62.5 °C/W Total Power Dissipation @ TA = 25°C (Note 1) Operating and Storage Temperature Range Maximum Lead Temperature for Soldering Purposes for 10 seconds TL 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. When surface mounted to an FR4 board using 1″ pad size, t ≤ 10 s © Semiconductor Components Industries, LLC, 2013 August, 2013 − Rev. 4 1 S SOIC−8 SUFFIX NB CASE 751 STYLE 11 8 E4N03 AYWW G G 1 S1 G1 S2 G2 E4N03 = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device NTMD4N03R2G Package SOIC−8 (Pb−Free) Shipping† 2500 / Tape & Reel NVMD4N03R2G* SOIC−8 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D Publication Order Number: NTMD4N03R2/D NTMD4N03, NVMD4N03 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 30 − − 32 − − − − − − 1.0 10 − − 100 1.0 − 1.9 4.2 3.0 − − − 0.048 0.065 0.060 0.080 − 6.0 − Ciss − 285 400 Coss − 95 135 Crss − 35 70 td(on) − 7.0 15 tr − 14 30 td(off) − 16 30 tf − 10 20 QT − 8.0 16 Q1 − 1.1 − Q2 − 1.9 − VSD − − 0.82 0.63 1.0 − Vdc trr − 14 − ns ta − 10 − tb − 4.0 − QRR − 0.008 − OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 mA) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 25°C) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125°C) IDSS Gate−Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C mAdc nAdc ON CHARACTERISTICS (Note 2) Gate Threshold Voltage (VDS = VGS, ID = 250 mAdc) Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−State Resistance (VGS = 10 Vdc, ID = 4 Adc) (VGS = 4.5 Vdc, ID = 2 Adc) RDS(on) Forward Transconductance (VDS = 3 Vdc, ID = 2 Adc) gFS Vdc mV/°C W Mhos DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 20 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance pF SWITCHING CHARACTERISTICS (Notes 2 & 3) Turn−On Delay Time (VDD = 20 Vdc, ID = 2 A, VGS = 10 V, RG = 2 W) Rise Time Turn−Off Delay Time Fall Time Gate Charge (VDS = 10 Vdc, VGS = 10 Vdc, ID = 3.5 A) ns nC BODY−DRAIN DIODE RATINGS (Note 2) Diode Forward On−Voltage (IS = 2 Adc, VGS = 0 V) (IS = 2 Adc, VGS = 0 V, TJ = 150°C) Reverse Recovery Time (IS = 2 A, VGS = 0 V, dIS/dt = 100 A/ms) Reverse Recovery Stored Charge (IS = 2 A, dIS/dt = 100 A/ms, VGS = 0 V) 2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 2 mC NTMD4N03, NVMD4N03 TYPICAL MOSFET ELECTRICAL CHARACTERISTICS RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 7 ID, DRAIN CURRENT (AMPS) 3.6 V 4V 8V 6 6V 4.5 V 5V 4 VGS = 3 V 2 0 TJ = 25°C 0 0.2 0.10 0.6 0.4 1.0 0.8 5 4 3 TJ = 25°C 2 1 TJ = 125°C 0 1 TJ = −55°C 2 4 3 5 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics VGS = 10 0.075 T = 125°C T = 25°C 0.05 T = −55°C 0.025 0 VDS ≥ 10 V 6 0 2 3 5 4 6 7 8 0.10 TJ = 25°C 0.08 VGS = 4.5 V 0.06 VGS = 10 V 0.04 0.02 0 2 3 4 5 6 7 8 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Drain Current and Temperature Figure 4. On−Resistance versus Drain Current and Gate Voltage 10,000 1.5 1.375 VGS = 0 V ID = 2 A VGS = 10 V IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 10 V RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) ID, DRAIN CURRENT (AMPS) 8 1.25 1.125 1 1000 TJ = 150°C 100 TJ = 125°C 0.875 0.75 −50 −25 0 25 50 75 100 125 10 150 0 5 10 15 20 25 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 3 30 NTMD4N03, NVMD4N03 POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 800 TJ = 25°C C, CAPACITANCE (pF) Ciss 600 Crss 400 Ciss 200 0 Coss VDS = 0 V 10 Crss VGS = 0 V 5 0 5 10 15 20 VGS VDS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 4 25 30 QT VGS 8 20 6 VDS Q1 4 Q2 10 ID = 4 A TJ = 25°C 2 0 0 1 2 3 4 5 6 7 8 9 10 0 Qg, TOTAL GATE CHARGE (nC) 100 td(off) VDD = 15 V ID = 4 A VGS = 10 V tf tr t, TIME (ns) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) NTMD4N03, NVMD4N03 10 td(on) 1 1 10 100 RG, GATE RESISTANCE (W) Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS high di/dts. The diode’s negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 14. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by IS, SOURCE CURRENT (AMPS) 4 VGS = 0 V TJ = 25°C 3 2 1 0 0.5 0.6 0.7 0.8 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 0.9 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 5 NTMD4N03, NVMD4N03 SAFE OPERATING AREA ID, DRAIN CURRENT (AMPS) 100 10 VGS = 20 V SINGLE PULSE TC = 25°C 1.0 ms 10 ms 1 0.1 0.01 dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0 10 100 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RqJC). A power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 ms. In addition the Figure 11. Maximum Rated Forward Biased Safe Operating Area 80 ID = 4.45 A 60 40 20 0 25 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 6 NTMD4N03, NVMD4N03 TYPICAL ELECTRICAL CHARACTERISTICS Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE 1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.0106 W 0.0431 W 0.1643 W 0.3507 W 0.4302 W 0.01 CHIP JUNCTION 0.01 0.0253 F 0.1406 F 0.5064 F 2.9468 F 177.14 F AMBIENT SINGLE PULSE 0.001 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) 1.0E+00 Figure 13. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 7 1.0E+01 1.0E+02 1.0E+03 NTMD4N03, NVMD4N03 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X S M J SOLDERING FOOTPRINT* INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 1.52 0.060 7.0 0.275 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 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American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 http://onsemi.com 8 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NTMD4N03R2/D