K6X0808T1D Family CMOS SRAM Document Title 32Kx8 bit Low Power CMOS Static RAM Revision History Revision No. History Draft Data Remark 0.0 Initial draft October 09, 2002 Preliminary 0.1 revised - errata : corrected 28-SOP-525 to 28-SOP-450 in pakage type November 08, 2002 Preliminary 0.2 revised - Added commercial product. March 27, 2003 Preliminary 1.0 Finalized - Changed ICC from 3mA to 2mA - Changed ICC2 from 25mA to 20mA - Changed ISB from 3mA to 0.4mA - Changed ISB1 for K6X0808T1D-F from 10µA to 6µA - Changed ISB1 for K6X0808T1D-F from 20µA to 10µA - Changed IDR for K6X0808T1D-F 10µA to 6µA - Changed IDR for K6X0808T1D-Q 20µA to 10µA - Errata correction December 16, 2003 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices. 1 Revision 1.0 December 2003 K6X0808T1D Family CMOS SRAM 32Kx8 bit Super Low Power and Low Voltage full CMOS Static RAM FEATURES GENERAL DESCRIPTION • Process Technology: Full CMOS28• Organization: 32K x 8 • Power Supply Voltage: 2.7~3.6V • Low Data Retention Voltage: 1.5V(Min) • Three state outputs • Package Type: 28-SOP-450, 28-TSOP1-0813.4F/R The K6X0808T1D families are fabricated by SAMSUNG′s advanced CMOS process technology. The families support verious operating temperature ranges and have various package types for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family Operating Temperature Vcc Range K6X0808T1D-B Industrial(0~70°C) K6X0808T1D-F Industrial(-40~85°C) K6X0808T1D-Q Automotive(-40~125°C) Speed Standby (ISB1, Max) Operating (ICC2, Max) 6µA 2.7~3.6V 701)/85ns PKG Type 28-SOP-450, 28-TSOP1-0813.4F/R 25mA 28-SOP-450, 28-TSOP1-0813.4F 10µA 1. The parameters are tested with 30pF test load PIN DESCRIPTION A14 1 28 A12 2 27 A7 3 26 A6 4 25 A5 5 24 A4 6 23 A3 7 A2 8 A1 9 A0 10 19 I/O1 11 18 I/O2 12 17 28-SOP OE A11 A9 A8 VCC A13 WE WE VCC A13 A14 A12 A8 A7 A6 A9 A5 A4 A11 A3 22 OE 21 A10 20 CS I/O3 13 16 VSS 14 15 A3 A4 A5 A6 I/O8 A7 I/O7 A12 A14 I/O6 VCC WE I/O5 A13 A8 I/O4 A9 A11 OE FUNCTIONAL BLOCK DIAGRAM 1 28 2 27 3 26 4 25 24 5 6 28-TSOP Type1 - Forward 7 8 23 22 21 9 20 10 19 11 18 12 17 13 16 14 15 14 15 13 16 12 17 11 18 10 19 9 20 28-TSOP Type1 - Reverse 8 7 21 22 6 23 5 24 4 25 3 26 2 27 1 28 A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 Clk gen. Row Addresses A2 A1 A0 I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 I/O8 CS A10 I/O1 I/O8 Row select Data cont Precharge circuit. Memory array I/O Circuit Column select Data cont Column Addresses CS1 Pin Name A0~A14 Function Address Inputs Pin Name I/O1~I/O8 Function WE Control logic Data Inputs/Outputs OE WE Write Enable Input Vcc Power CS Chip Select Input Vss Ground OE Output Enable Input NC No connect SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 1.0 December 2003 K6X0808T1D Family CMOS SRAM PRODUCT LIST Commercial Temp. Products(0~70°C) Industrial Temp. Products(-40~85°C) Atomotive Temp. Products(-40~125°C) Part Name Function Part Name Function Part Name Function K6X0808T1D-GB70 K6X0808T1D-GB85 K6X0808T1D-YB70 K6X0808T1D-YB85 K6X0808T1D-NB70 K6X0808T1D-NB85 28-SOP, 70ns, LL 28-SOP, 85ns, LL 28-sTSOP-F, 70ns, LL 28-sTSOP-F, 85ns, LL 28-sTSOP-R, 70ns, LL 28-sTSOP-R, 85ns, LL K6X0808T1D-GF70 K6X0808T1D-GF85 K6X0808T1D-YF70 K6X0808T1D-YF85 K6X0808T1D-NF70 K6X0808T1D-NF85 28-SOP, 70ns, LL 28-SOP, 85ns, LL 28-sTSOP-F, 70ns, LL 28-sTSOP-F, 85ns, LL 28-sTSOP-R, 70ns, LL 28-sTSOP-R, 85ns, LL K6X0808T1D-GQ70 K6X0808T1D-GQ85 K6X0808T1D-YQ70 K6X0808T1D-YQ85 28-SOP, 70ns, L 28-SOP, 85ns, L 28-sTSOP-F, 70ns, L 28-sTSOP-F, 85ns, L FUNCTIONAL DESCRIPTION CS OE WE I/O Mode Power High-Z Deselected Standby H High-Z Output Disabled Active L H Dout Read Active X1) L Din Write Active H X X L H L L 1) 1) 1. X means don't care (Must be in high or low states) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol Ratings Unit Remark VIN,VOUT -0.2 to VCC+0.3V(Max. 3.9V) V - VCC -0.2 to 3.9 V - PD 1.0 W - TSTG -65 to 150 °C - -40 to 85 °C K6X0808T1D-F -40 to 125 °C K6X0808T1D-Q TA 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 Revision 1.0 December 2003 K6X0808T1D Family CMOS SRAM RECOMMENDED DC OPERATING CONDITIONS1) Item Symbol Min Typ Max Unit Supply voltage Vcc 2.7 3.0/3.3 3.6 V Ground Vss 0 0 0 Input high voltage VIH 2.2 - Input low voltage VIL -0.2 3) V Vcc+0.2 - V 2) 0.6 V Note: 1. Industrial Product: TA=-40 to 85°C, Otherwise specified Automotive Product: TA=-40 to 125°C, Otherwise specified 2. Overshoot: Vcc+3.0V in case of pulse width≤30ns. 3. Undershoot: -3.0V in case of pulse width≤30ns. 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f=1MHz, TA=25°C) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 10 pF 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Item Symbol Test Conditions Min Typ Max Unit Input leakage current ILI VIN=Vss to Vcc -1 - 1 µA Output leakage current ILO CS=VIH or OE=VIH or WE=VIL, VIO=VSS to Vcc -1 - 1 µA Operating power supply current ICC IIO=0mA, CS=VIL, VIN=VIH or VIL, Read - - 2 mA ICC1 Cycle time=1µs, 100% duty, IIO=0mA, CS≤0.2V, VIN≤0.2VIN≥Vcc -0.2V - - 3 mA ICC2 Cycle time=Min,100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL - - 20 mA Average operating current Output low voltage VOL IOL=2.1mA - - 0.4 V Output high voltage VOH IOH=-1.0mA 2.4 - - V Standby Current(TTL) ISB CS=VIH, Other inputs=VIH or VIL Standby Current(CMOS) ISB1 CS≥Vcc-0.2V, Other inputs=0~Vcc 4 - - 0.3 mA K6X0808T1D-F - - 6 µA K6X0808T1D-Q - - 10 µA Revision 1.0 December 2003 K6X0808T1D Family CMOS SRAM AC OPERATING CONDITIONS TEST CONDITIONS( Test Load and Input/Output Reference) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage:1.5V Output load(see right): CL=100pF+1TTL CL=30pF+1TTL AC CHARACTERISTICS CL1) 1. Including scope and jig capacitance (VCC=2.7~3.6V, Industrial product:TA=-40 to 85°C, Automotive product:TA=-40 to 125°C ) Speed Bins Parameter List Symbol Read Cycle Time Read tRC Units 85ns Min Max Min Max 70 - 85 - ns Address Access Time tAA - 70 - 85 ns Chip Select to Output tCO - 70 - 85 ns Output Enable to Valid Output tOE - 35 - 40 ns Chip Select to Low-Z Output tLZ 10 - 10 - ns Output Enable to Low-Z Output tOLZ 5 - 5 - ns Chip Disable to High-Z Output tHZ 0 25 0 25 ns tOHZ 0 25 0 25 ns Output Hold from Address Change tOH 10 - 15 - ns Write Cycle Time tWC 70 - 85 - ns Chip Select to End of Write tCW 60 - 70 - ns Address Set-up Time tAS 0 - 0 - ns Address Valid to End of Write tAW 60 - 70 - ns Write Pulse Width tWP 50 - 60 - ns Write Recovery Time tWR 0 - 0 - ns Write to Output High-Z tWHZ 0 25 0 30 ns Data to Write Time Overlap tDW 25 - 35 - ns Data Hold from Write Time tDH 0 - 0 - ns End Write to Output Low-Z tOW 5 - 5 - ns Output Disable to High-Z Output Write 70ns DATA RETENTION CHARACTERISTICS Item Symbol Test Condition Vcc for data retention VDR CS1≥Vcc-0.2V Data retention current IDR Vcc=3.0V, CS1≥Vcc-0.2V K6X0808T1D-F Min Typ Max Unit 2.0 - 3.6 V - - K6X0808T1D-Q Data retention set-up time tSDR Recovery time tRDR See data retention waveform 5 6 µA 10 µA 0 - - 5 - - ms Revision 1.0 December 2003 K6X0808T1D Family CMOS SRAM TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tOH tAA tCO CS tHZ tOE OE Data out High-Z tOHZ tOLZ tLZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 1.0 December 2003 K6X0808T1D Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) tWR(4) CS tAW tWP(1) WE tAS(3) tDW tDH Data Valid Data in tWHZ Data out tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled) tWC Address tCW(2) tAS(3) tWR(4) CS tAW tWP(1) WE tDW Data in Data out tDH Data Valid High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high. DATA RETENTION WAVE FORM CS controlled VCC tSDR Data Retention Mode tRDR 3.0V/2.7V 2.2V VDR CS≥VCC - 0.2V CS GND 7 Revision 1.0 December 2003 K6X0808T1D Family CMOS SRAM PACKAGE DIMENSIONS Units: millimeter(inch) 28 PIN PLASTIC SMALL OUTLINE PACKAGE(450mil) 0~8° #15 11.81±0.30 0.465±0.012 #1 8.38±0.20 0.330±0.008 #14 2.59±0.20 0.102±0.008 18.69 MAX 0.736 +0.10 -0.05 0.006 +0.004 -0.002 0.15 11.43 0.450 #28 1.02±0.20 0.040±0.008 3.00 0.118 MAX 18.29±0.20 0.720±0.008 0.10 MAX 0.004 MAX ( 0.89 ) 0.035 0.41±0.10 0.016±0.004 1.27 0.050 0.05 MIN 0.002 8 Revision 1.0 December 2003 K6X0808T1D Family CMOS SRAM PACKAGE DIMENSIONS Units: millimeter(inch) +0.10 -0.05 +0.004 0.008-0.002 0.20 0.10 MAX 0.004 MAX 28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4F) 13.40±0.20 0.528±0.008 #1 #28 0.55 0.0217 #14 0.25 0.010 TYP 0.425 ) 0.017 8.00 0.315 8.40 0.331 MAX ( #15 11.80±0.10 0.465±0.004 +0.10 -0.05 0.006+0.004 -0.002 0.15 1.00±0.10 0.039±0.004 0.05 0.002 MIN 0~8° 1.20 0.047 MAX 0.45 ~0.75 0.018 ~0.030 0.50 ) 0.020 0.10 MAX 0.004 MAX ( 28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4R) +0.10 -0.05 +0.004 0.008-0.002 0.20 13.40±0.20 0.528±0.008 #14 #15 0.55 0.0217 #1 0.25 0.010 TYP 0.425 ) 0.017 8.00 0.315 8.40 0.331 MAX ( #28 11.80±0.10 0.465±0.004 +0.10 -0.05 0.006+0.004 -0.002 0.15 1.00±0.10 0.039±0.004 0.05 0.002 MIN 1.20 0.047 MAX 0~8° 0.45 ~0.75 0.018 ~0.030 ( 9 0.50 ) 0.020 Revision 1.0 December 2003