K7M323625M K7M321825M 1Mx36 & 2Mx18 Flow-Through NtRAMTM Document Title 1Mx36 & 2Mx18-Bit Flow Through NtRAMTM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. May. 10. 2001 Preliminary 0.1 1. Add 165FBGA package Aug. 29. 2001 Preliminary 0.2 1. Update JTAG scan order Dec. 03. 2001 Preliminary 0.3 1. Change pin out for 165FBGA - x18/x36 ; 11B => from A to NC , 2R ==> from NC to A Feb. 14. 2002 Preliminary 0.4 1. Insert pin at JTAG scan order of 165FBGA in connection with pin out change - x18/x36 ; insert Pin ID of 2R to BIT number of 69 Apr. 20. 2002 Preliminary 0.5 1. Add Icc, Isb, Isb1 and Isb2 values. May. 10. 2002 Preliminary 1.0 1. Final datasheet release. Sep. 26. 2002 Final 1.1 1. Change the Stand-by current (Isb) Before After Isb - 65 : 100 140 - 75 : 90 130 - 85 : 80 130 Isb1 : 90 110 Isb2 : 80 100 Oct. 17. 2003 Final 2.0 1. Delete the 119BGA and 165FBGA package 2. Delete the 6.5ns and 8.5ns speed bin Nov. 18, 2003 Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Nov. 2003 Rev 2.0 K7M323625M K7M321825M 1Mx36 & 2Mx18 Flow-Through NtRAMTM 32Mb NtRAM(Flow Through / Pipelined) Ordering Information Org. Part Number K7M321825M-QC75 Mode VDD Speed FT ; Access Time(ns) Pipelined ; Cycle Time(MHz) FlowThrough 3.3 7.5ns 2Mx18 K7N321801M-Q(F)C25/20/16/13 Pipelined 3.3 250/200/167/133MHz K7N321845M-Q(F)C25/20/16/13 Pipelined 2.5 250/200/167/133MHz FlowThrough 3.3 7.5ns 1Mx36 K7N323601M-Q(F)C25/20/16/13 K7M323625M-QC75 Pipelined 3.3 250/200/167/133MHz K7N323645M-Q(F)C25/20/16/13 Pipelined 2.5 250/200/167/133MHz -2- PKG Temp C Q:100TQFP (Commercial F:165FBGA Temperature Range) Nov. 2003 Rev 2.0 K7M323625M K7M321825M 1Mx36 & 2Mx18 Flow-Through NtRAMTM 1Mx36 & 2Mx18-Bit Flow Through NtRAMTM FEATURES GENERAL DESCRIPTION • 3.3V+0.165V/-0.165V Power Supply. • I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O • Byte Writable Function. • Enable clock and suspend operation. • Single READ/WRITE control pin. • Self-Timed Write Cycle. • Three Chip Enable for simple depth expansion with no data contention . • A interleaved burst or a linear burst mode. • Asynchronous output enable control. • Power Down mode. • TTL-Level Three-State Outputs. • 100-TQFP-1420A . The K7M323625M and K7M321825M are 37,748,736-bits Synchronous Static SRAMs. The NtRAMTM, or No Turnaround Random Access Memory utilizes all bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. For read cycles, Flow-Through SRAM allows output data to simply flow freely from the memory array. The K7M323625M and K7M321825M are implemented with SAMSUNG′s high performance CMOS technology and is available in 100pin TQFP packages. Multiple power and ground pins minimize ground bounce. FAST ACCESS TIMES Parameter Symbol -75 Unit Cycle Time tCYC 8.5 ns Clock Access Time tCD 7.5 ns Output Enable Access Time tOE 3.5 ns LOGIC BLOCK DIAGRAM LBO A [0:19]or A [0:20] CKE ADDRESS REGISTER A2 ~A 19 or A2 ~A 20 CONTROL LOGIC CLK A0~A1 ADV WE BW x (x=a,b,c,d or a,b) A′0~A′1 1Mx36 , 2Mx18 MEMORY ARRAY WRITE ADDRESS REGISTER K K CONTROL REGISTER CS 1 CS 2 CS 2 BURST ADDRESS COUNTER DATA-IN REGISTER CONTROL LOGIC BUFFER OE ZZ 36 or 18 DQa0 ~ DQd7 or DQa 0 ~ DQb8 DQPa ~ DQPd NtRAM TM and No Turnaround Random Access Memory are trademarks of Samsung. -3- Nov. 2003 Rev 2.0 K7M323625M K7M321825M 1Mx36 & 2Mx18 Flow-Through NtRAMTM A6 A7 CS 1 CS 2 BWd BWc BWb BWa CS 2 V DD V SS CLK WE CK E OE ADV A 18 A 17 A8 A9 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 Pin TQFP (20mm x 14mm) 38 39 40 41 42 43 44 45 46 47 48 49 50 N.C. N.C. V SS V DD N.C. A 19 A 10 A 11 A 12 A 13 A 14 A 15 A 16 35 A2 37 34 A3 A0 33 A4 36 32 A1 31 K7M323625M(1Mx36) A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LBO DQPc DQc0 DQc1 V DDQ V SSQ DQc2 DQc3 DQc4 DQc5 V SSQ V DDQ DQc6 DQc7 Vss V DD V DD V SS DQd 0 DQd 1 V DDQ V SSQ DQd 2 DQd 3 DQd 4 DQd 5 V SSQ V DDQ DQd 6 DQd 7 DQPd 100 PIN CONFIGURATION(TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb DQb 7 DQb 6 V DDQ V SSQ DQb 5 DQb 4 DQb 3 DQb 2 V SSQ V DDQ DQb 1 DQb 0 V SS V SS V DD ZZ DQa 7 DQa 6 V DDQ V SSQ DQa 5 DQa 4 DQa 3 DQa 2 V SSQ V DDQ DQa 1 DQa 0 DQPa PIN NAME SYMBOL A 0 - A 19 PIN NAME TQFP PIN NO. SYMBOL Address Inputs 32,33,34,35,36,37,43 4445,46,47,48,49,50, 81,82,83,84,99,100 ADV Address Advance/Load 85 WE Read/Write Control Input 88 CLK Clock 89 CKE Clock Enable 87 CS 1 Chip Select 98 CS 2 Chip Select 97 CS 2 Chip Select 92 B Wx(x=a,b,c,d) Byte Write Inputs 93,94,95,96 OE Output Enable 86 ZZ Power Sleep Mode 64 LBO Burst Mode Control 31 PIN NAME TQFP PIN NO. V DD V SS Power Supply(+3.3V) 15,16,41,65,91 Ground 14,17,40,66,67,90 N.C. No Connect 38,39,42 DQa0~a7 DQb0~b7 DQc0 ~ c7 DQd0~d7 DQPa~P d Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 V DDQ Output Power Supply (2.5V or 3.3V) Output Ground 4,11,20,27,54,61,70,77 V SSQ 5,10,21,26,55,60,71,76 Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. -4- Nov. 2003 Rev 2.0 K7M323625M K7M321825M 1Mx36 & 2Mx18 Flow-Through NtRAMTM A7 CS 1 CS 2 N.C. N.C. BWb BWa CS 2 V DD V SS CLK WE CK E OE ADV A 19 A 18 A8 A9 98 97 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 96 A6 99 100 Pin TQFP (20mm x 14mm) 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A0 N.C. N.C. V SS V DD N.C. A 20 A 11 A 12 A 13 A 14 A 15 A 16 A 17 34 A3 A1 33 A4 35 32 A2 31 K7M321825M(2Mx18) A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LBO N.C. N.C. N.C. V DDQ V SSQ N.C. N.C. DQb 8 DQb 7 V SSQ V DDQ DQb 6 DQb 5 V SS V DD V DD V SS DQb 4 DQb 3 V DDQ V SSQ DQb 2 DQb 1 DQb 0 N.C. V SSQ V DDQ N.C. N.C. N.C. 100 PIN CONFIGURATION(TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A 10 N.C. N.C. V DDQ V SSQ N.C. DQa 0 DQa 1 DQa 2 V SSQ V DDQ DQa 3 DQa 4 V SS V SS V DD ZZ DQa 5 DQa 6 V DDQ V SSQ DQa 7 DQa 8 N.C. N.C. V SSQ V DDQ N.C. N.C. N.C. PIN NAME SYMBOL A 0 - A 20 PIN NAME Address Inputs TQFP PIN NO. 32,33,34,35,36,37,43 44,45,46,47,48,49,50, 80,81,82,83,84,99,100 ADV Address Advance/Load 85 WE Read/Write Control Input 88 CLK Clock 89 CKE Clock Enable 87 CS 1 Chip Select 98 CS 2 Chip Select 97 CS 2 Chip Select 92 BW x(x=a,b) Byte Write Inputs 93,94 OE Output Enable 86 ZZ Power Sleep Mode 64 LBO Burst Mode Control 31 SYMBOL PIN NAME TQFP PIN NO. V DD V SS Power Supply(+3.3V) Ground 15,16,41,65,91 14,17,40,66,67,90 N.C. No Connect 1,2,3,6,7,25,28,29,30, 38,39,42,51,52,53, 56,57,75,78,79,95,96 DQa0 ~a8 DQb0 ~b8 Data Inputs/Outputs Data Inputs/Outputs 58,59,62,63,68,69,72,73,74 8,9,12,13,18,19,22,23,24 V DDQ Output Power Supply (2.5V or 3.3V) Output Ground 4,11,20,27,54,61,70,77 V SSQ 5,10,21,26,55,60,71,76 Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. -5- Nov. 2003 Rev 2.0 K7M323625M K7M321825M 1Mx36 & 2Mx18 Flow-Through NtRAMTM FUNCTION DESCRIPTION The K7M323625M and K7M321825M are NtRAMTM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, or vice versa. All inputs (with the exception of O E, LBO and ZZ) are synchronized to rising clock edges. All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next operation. Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous inputs are ignored and the internal device registers will hold their previous values. NtRAM TM latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables( CS 1, CS 2, CS 2) are active . Output Enable(OE ) can be used to disable the output at any given time. Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, CKE is driven low, all three chip enables( CS 1, CS 2 , CS 2) are active, the write enable input signals WE are driven high, and ADV driven low. Data appears at the outputs within the same clock cycle as the address for the data. Also during read operation OE must be driven low for the device to drive out the requested data. Write operation occurs when WE is driven low at the rising edge of the clock. BW [d:a] can be used for byte write operation. The Flow Through NtRAMTM uses a late write cycle to utilize 100% of the bandwidth. At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required one cycle later. Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected. And when this pin is high, Interleaved burst sequence is selected. During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up time. BURST SEQUENCE TABLE LBO PIN HIGH First Address Fourth Address (Interleaved Burst, LBO=High) Case 1 A1 0 0 1 1 Case 2 A0 0 1 0 1 A1 0 0 1 1 Case 3 A0 1 0 1 0 A1 1 1 0 0 BQ TABLE LBO PIN Case 4 A0 0 1 0 1 A1 1 1 0 0 A0 1 0 1 0 (Linear Burst, LBO =Low) LOW First Address Fourth Address Case 1 A1 0 0 1 1 Case 2 A0 0 1 0 1 A1 0 1 1 0 Case 3 A0 1 0 1 0 A1 1 1 0 0 Case 4 A0 0 1 0 1 A1 1 0 0 1 A0 1 0 1 0 Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed . -6- Nov. 2003 Rev 2.0 K7M323625M K7M321825M 1Mx36 & 2Mx18 Flow-Through NtRAMTM STATE DIAGRAM FOR N tRAMTM WRITE READ READ BEGIN READ BEGIN WRITE DS RE AD W DS AD W R IT E ST BUR TE E R BURST DS BURST READ BURST WRITE COMMAND DS WRI DESELECT DS BURST TE BUR ST D R EA DS RI WRITE BURST ACTION DESELECT READ BEGIN READ WRITE BEGIN WRITE BURST BEGIN READ BEGIN WRITE CONTINUE DESELECT Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does not change the state of the device. 2. States change on the rising edge of the clock(CLK) -7- Nov. 2003 Rev 2.0 K7M323625M K7M321825M 1Mx36 & 2Mx18 Flow-Through NtRAMTM TRUTH TABLES SYNCHRONOUS TRUTH TABLE CS 1 CS2 CS 2 ADV WE BWx OE CKE CLK ADDRESS ACCESSED OPERATION H X X L X X X L ↑ N/A Not Selected X L X L X X X L ↑ N/A Not Selected X X H L X X X L ↑ N/A Not Selected X X X H X X X L ↑ N/A Not Selected Continue L H L L H X L L ↑ External Address Begin Burst Read Cycle X X X H X X L L ↑ Next Address Continue Burst Read Cycle L H L L H X H L ↑ External Address NOP/Dummy Read X X X H X X H L ↑ Next Address Dummy Read L H L L L L X L ↑ External Address Begin Burst Write Cycle X X X H X L X L ↑ Next Address Continue Burst Write Cycle L H L L L H X L ↑ N/A NOP/Write Abort X X X H X H X L ↑ Next Address Write Abort X X X X X X X H ↑ Current Address Ignore Clock Notes : 1. X means "Don ′t Care". 2. The rising edge of clock is symbolized by (↑). 3. A continue deselect cycle can only be enterd if a deselect cycle is executed first. 4. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 5. Operation finally depends on status of asynchronous input pins(ZZ and OE). WRITE TRUTH TABLE( x36) WE BWa BWb BW c BW d OPERATION H X X X X READ L L H H H WRITE BYTE a L H L H H WRITE BYTE b L H H L H WRITE BYTE c L H H H L WRITE BYTE d L L L L L WRITE ALL BYTEs L H H H H WRITE ABORT/NOP Notes : 1. X means "Don′t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑). WRITE TRUTH TABLE(x18) WE BWa BWb OPERATION H X X READ L L H WRITE BYTE a L H L WRITE BYTE b L L L WRITE ALL BYTEs L H H WRITE ABORT/NOP Notes : 1. X means "Don′t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK( ↑). -8- Nov. 2003 Rev 2.0 K7M323625M K7M321825M 1Mx36 & 2Mx18 Flow-Through NtRAMTM ASYNCHRONOUS TRUTH TABLE Operation ZZ OE I/O STATUS Sleep Mode H X High-Z L L DQ L H High-Z Write L X Din, High-Z Deselected L X High-Z Read Notes 1. X means "Don′ t Care". 2. Sleep Mode means power Sleep Mode of which stand-by current does not depend on cycle time. 3. Deselected means power Sleep Mode of which stand-by current depends on cycle time. ABSOLUTE MAXIMUM RATINGS* PARAMETER SYMBOL RATING UNIT V Voltage on V DD Supply Relative to V SS V DD -0.3 to 4.6 Voltage on Any Other Pin Relative to VSS V IN -0.3 to VDD+0.3 V Power Dissipation PD 1.6 W Storage Temperature TSTG -65 to 150 °C Operating Temperature T OPR 0 to 70 °C Storage Temperature Range Under Bias TBIAS -10 to 85 °C *Notes : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING CONDITIONS at 3.3V I/O(0°C ≤ TA ≤ 70°C) PARAMETER Supply Voltage Ground SYMBOL MIN Typ. MAX UNIT V DD 3.135 3.3 3.465 V V DDQ 3.135 3.3 3.465 V V SS 0 0 0 V OPERATING CONDITIONS at 2.5V I/O(0°C ≤ TA ≤ 70°C) PARAMETER Supply Voltage Ground SYMBOL MIN Typ. MAX UNIT V DD 3.135 3.3 3.465 V V DDQ 2.375 2.5 2.9 V V SS 0 0 0 V CAPACITANCE*(TA =25°C, f=1MHz) PARAMETER Input Capacitance Output Capacitance SYMBOL TEST CONDITION TYP MAX UNIT CIN V IN=0V - 5 pF C OUT V OUT=0V - 7 pF *Note : Sampled not 100% tested. -9- Nov. 2003 Rev 2.0 K7M323625M K7M321825M 1Mx36 & 2Mx18 Flow-Through NtRAMTM DC ELECTRICAL CHARACTERISTICS (VDD =3.3V+0.165V/-0.165V, TA =0°C to +70°C) MIN MAX Input Leakage Current(except ZZ) PARAMETER SYMBOL IIL V DD=Max ; V IN=VSS to V DD -2 +2 µA Output Leakage Current IOL Output Disabled, -2 +2 µA -75 - 290 mA -75 - 130 mA - 110 mA - 100 mA 0.4 V Operating Current ICC TEST CONDITIONS Device Selected, I OUT =0mA, ZZ ≤V IL , Cycle Time ≥ tCYC Min UNIT NOTES 1,2 Device deselected, I OUT =0mA, ISB ZZ ≤V IL , f=Max, All Inputs ≤0.2V or ≥ V DD-0.2V Device deselected, I OUT =0mA, Standby Current ISB1 ZZ ≤0.2V, f=0, All Inputs=fixed (VDD -0.2V or Device deselected, I OUT =0mA, ISB2 ZZ≥V DD-0.2V, f=Max, All Inputs ≤V IL or ≥V IH Output Low Voltage(3.3V I/O) V OL IOL=8.0mA - Output High Voltage(3.3V I/O) VO H IO H=-4.0mA 2.4 - V Output Low Voltage(2.5V I/O) V OL IOL=1.0mA - 0.4 V Output High Voltage(2.5V I/O) VO H IO H=-1.0mA Input Low Voltage(3.3V I/O) V IL Input High Voltage(3.3V I/O) 2.0 - V -0.3* 0.8 V VI H 2.0 V DD+0.3** V Input Low Voltage(2.5V I/O) V IL -0.3* 0.7 V Input High Voltage(2.5V I/O) VI H 1.7 V DD+0.3** V 3 3 Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing. 2. Data states are all zero. 3. In Case of I/O Pins, the Max. VIH =V DDQ +0.3V. VIH VSS VSS- 1.0V 20% tCYC (MIN) TEST CONDITIONS (VDD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0to70°C) PARAMETER VALUE Input Pulse Level(for 3.3V I/O) 0 to 3.0V Input Pulse Level(for 2.5V I/O) 0 to 2.5V Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O) 1.0V/ns Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O) 1.0V/ns Input and Output Timing Reference Levels for 3.3V I/O 1.5V Input and Output Timing Reference Levels for 2.5V I/O V DDQ/2 Output Load See Fig. 1 - 10 - Nov. 2003 Rev 2.0 K7M323625M K7M321825M 1Mx36 & 2Mx18 Flow-Through NtRAMTM Output Load(A) Output Load(B), (for tLZC, tLZOE, tHZOE & tHZC) +3.3V for 3.3V I/O /+2.5V for 2.5V I/O RL=50Ω Dout Zo=50Ω 30pF* VL=1.5V for 3.3V I/O V DDQ/2 for 2.5V I/O 319Ω / 1667Ω Dout 353Ω / 1538Ω 5pF* * Including Scope and Jig Capacitance Fig. 1 AC TIMING CHARACTERISTICS (VDD=3.3V+0.165V/-0.165V, T A=0°C to +70°C) -75 PARAMETER SYMBOL MIN MAX UNIT Cycle Time tCYC 8.5 - ns Clock Access Time tCD - 7.5 ns Output Enable to Data Valid tOE - 3.5 ns Clock High to Output Low-Z tLZC 2.5 - ns Output Hold from Clock High tOH 2.5 - ns Output Enable Low to Output Low-Z tLZOE 0 - ns Output Enable High to Output High-Z tHZOE - 3.5 ns Clock High to Output High-Z tHZC - 4.0 ns Clock High Pulse Width tCH 2.8 - ns Clock Low Pulse Width tCL 2.8 - ns Address Setup to Clock High tAS 2.0 - ns CKE Setup to Clock High tCES 2.0 - ns Data Setup to Clock High tDS 2.0 - ns Write Setup to Clock High (WE, BW X ) tWS 2.0 - ns Address Advance Setup to Clock High tADVS 2.0 - ns Chip Select Setup to Clock High tCSS 2.0 - ns Address Hold from Clock High tAH 0.5 - ns CKE Hold from Clock High tCEH 0.5 - ns Data Hold from Clock High tDH 0.5 - ns Write Hold from Clock High (WE , BW X) tWH 0.5 - ns Address Advance Hold from Clock High tADVH 0.5 - ns Chip Select Hold from Clock High tCSH 0.5 - ns ZZ High to Power Down tPDS 2 - cycle ZZ Low to Power Up tPUS 2 - cycle Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled. 3. A write cycle is defined by WE low having been registerd into the device at ADV Low, A Read cycle is defined by WE High with ADV Low, Both cases must meet setup and hold times. 4. To avoid bus contention, At a given vlotage and temperature tLZC is more than tHZC. The soecs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions (0°C,3.465V) than tH Z C, which is a Max. parameter(worst case at 70°C,3.135V) It is not possible for two SRAMs on the same board to be at such different voltage and temperatue. - 11 - Nov. 2003 Rev 2.0 K7M323625M K7M321825M 1Mx36 & 2Mx18 Flow-Through NtRAMTM SLEEP MODE SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of SLEEP MODE is dictated by the length of time the ZZ is in a High state. After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE. When the ZZ pin becomes a logic High, I SB2 is guaranteed after the time t ZZI is met. Any operation pending when entering SLEEP MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pending operations are completed. similarly, when exiting SLEEP MODE during t PUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SLEEP MODE. SLEEP MODE ELECTRICAL CHARACTERISTICS DESCRIPTION Current during SLEEP MODE CONDITIONS SYMBOL ZZ ≥ V IH ISB2 MIN MAX 60 UNITS mA ZZ active to input ignored tPDS 2 cycle ZZ inactive to input sampled tPUS 2 cycle ZZ active to SLEEP current tZZI ZZ inactive to exit SLEEP current tRZZI 2 cycle 0 SLEEP MODE WAVEFORM K t PDS ZZ setup cycle tPUS ZZ recovery cycle ZZ t ZZI Isupply ISB2 tRZZI All inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z DON′ T CARE - 12 - Nov. 2003 Rev 2.0 - 13 - Data Out OE ADV CS WRITE Address CKE Clock A1 tLZOE tOE tADVH tCSH tWH tAH Q 1-1 tHZOE A2 tCEH Q 2-1 tCD tOH Q2-2 Q 2-3 NO TE S : WRITE = L me ans WE = L, an d B Wx = L CS = L mean s CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS 2 = H, or CS 1 = L, and CS 2 = L tADVS tCSS tWS tAS tCES tCL tCYC tCH Q2-4 A3 TIMING WAVEFORM OF READ CYCLE Q 3-1 Q 3-2 Q3-3 Q3-4 tHZC Un defined Do n′t Care K7M323625M K7M321825M 1Mx36 & 2Mx18 Flow-Through NtRAMTM Nov. 2003 Rev 2.0 - 14 - Data Out Data In OE ADV CS WRITE Address CKE Clock tHZOE D1-1 A2 tCYC D2-1 tCL D2-2 NOTES : WRITE = L means WE = L, a nd BWx = L CS = L me ans CS1 = L, CS2 = H a nd CS 2 = L CS = H mean s CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L Q0-4 A1 tCES tCEH tCH D2-3 D2-4 A3 TIMING WAVEFORM OF WRTE CYCLE D3-1 tDS D3-2 tDH D3-3 D3-4 Undefined Don′t Ca re K7M323625M K7M321825M 1Mx36 & 2Mx18 Flow-Through NtRAMTM Nov. 2003 Rev 2.0 - 15 - Data In Data Out OE ADV CS WRITE Address CKE Clock Q1 A2 tDS D2 A3 tDH Q3 A4 NOTES : WRITE = L means WE = L, a nd BWx = L CS = L me ans CS1 = L, CS2 = H a nd CS 2 = L CS = H mean s CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L tOE tLZOE A1 tCES tCEH Q4 A5 D5 A6 Q6 A7 TIMING WAVEFORM OF SINGLE READ/WRITE tCH Q7 tCYC tCL Undefined Don′t Car e K7M323625M K7M321825M 1Mx36 & 2Mx18 Flow-Through NtRAMTM Nov. 2003 Rev 2.0 - 16 - Data In tCD tLZC A1 tCES tCEH Q1 A2 tHZC tDS D2 A3 tDH NO TE S : WRITE = L me ans WE = L, an d B Wx = L CS = L mean s CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS 2 = H, or CS 1 = L, and CS 2 = L Data Out OE ADV CS WRITE Address CKE Clock Q3 A4 TIMING WAVEFORM OF CKE OPERATION tCH Q4 tCYC tCL A5 Undefined Don′t Care K7M323625M K7M321825M 1Mx36 & 2Mx18 Flow-Through NtRAMTM Nov. 2003 Rev 2.0 - 17 - Data In Data Out OE ADV CS WRITE Address CKE Clock tOE tLZOE A1 tCEH Q1 A2 Q2 tHZC A3 D3 tDS tDH NO TE S : WRITE = L me ans WE = L, an d B Wx = L CS = L mean s CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS 2 = H, or CS 1 = L, and CS 2 = L tCES tCD tLZC A4 Q4 TIMING WAVEFORM OF CS OPERATION A5 D5 tCH tCYC tCL Undefined Don′t Care K7M323625M K7M321825M 1Mx36 & 2Mx18 Flow-Through NtRAMTM Nov. 2003 Rev 2.0 K7M323625M K7M321825M 1Mx36 & 2Mx18 Flow-Through NtRAMTM PACKAGE DIMENSIONS 100-TQFP-1420A Units ; millimeters/Inches 0~8° 22.00 ±0.30 20.00 ±0.20 0.127 16.00 + 0.10 - 0.05 ± 0.30 14.00 ± 0.20 0.10 MAX (0.83) 0.50 #1 0.65 ±0.10 (0.58) 0.30 ± 0.10 0.10 MAX 1.40 0.50 ± 0.10 - 18 - ± 0.10 1.60 MAX 0.05 MIN Nov. 2003 Rev 2.0