K7Q163662B K7Q161862B 512Kx36 & 1Mx18 QDRTM b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit QDRTM SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Jan. 27, 2004 Advance 1.0 1. Final spec release Mar. 18, 2004 Final Rev. No. The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Mar. 2004 Rev 1.0 K7Q163662B K7Q161862B 512Kx36 & 1Mx18 QDRTM b2 SRAM 512Kx36-bit, 1Mx18-bit QDRTM SRAM FEATURES • 1.8V/2.5V +0.1V/-0.1V Power Supply. • I/O Supply Voltage 1.5V +0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O. • Separate independent read and write data ports with concurrent read and write operation • HSTL I/O. • Full data coherency, providing most current data . • Synchronous pipeline read with self timed early write. • Registered address, control and data input/output. • DDR(Double Data Rate) Interface on read and write ports. • Fixed 2-bit burst for both read and write operation. • Clock-stop supports to reduce current. • Two input clocks(K and K) for accurate DDR timing at clock rising edges only. • Two Input clocks for output data(C and C) to minimize clock-skew and flight-time mismatches. • Single address bus. • Byte writable function. • Sepatate read/write control pin(R and W) • Simple depth expansion with no data contention. • Programmable output impedance. • JTAG 1149.1 compatible test access port. • 165FBGA(11x15 ball aray FBGA) with body size of 13x15mm Organization Part Number Cycle Time Access Unit Time X36 K7Q163662B-FC16 6.0 2.5 ns X18 K7Q161862B-FC16 6.0 2.5 ns FUNCTIONAL BLOCK DIAGRAM 36 (or 18) D(Data in) DATA REG 36 (or 18) 36 (or 18) WRITE DRIVER K K C 72 (or 36) OUTPUT DRIVER 72 (or 36) OUTPUT SELECT 4(or 2) CTRL LOGIC 512Kx36 1Mx18 MEMORY ARRAY OUTPUT REG R W BWX 18 (or 19) SENSE AMPS ADDRESS ADD REG WRITE/READ DECODE 18 (or 19) 36 (or 18) Q(Data Out) CLK GEN SELECT OUTPUT CONTROL C Notes: 1. Numbers in ( ) are for x18 device. QDR SRAM and Quad Data Rate comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC and Samsung technology. -2- Mar. 2004 Rev 1.0 K7Q163662B K7Q161862B 512Kx36 & 1Mx18 QDRTM b2 SRAM PIN CONFIGURATIONS(TOP VIEW) K7Q161862B(1Mx18) 1 2 3 4 5 6 7 8 9 10 11 A NC VSS NC W BW1 K NC R SA VSS NC B NC Q9 D9 SA NC K BW0 SA NC NC Q8 C NC NC D10 VSS SA SA SA VSS NC Q7 D8 D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7 E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5 H NC VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4 K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3 L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2 M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2 N NC D17 Q16 VSS SA SA SA VSS NC NC D1 P NC NC Q17 SA SA C SA SA NC D0 Q0 R TDO TCK SA SA SA C SA SA SA TMS TDI Notes: 1. * Checked pins are reserved for higher density address 2. BW0 controls write to D0:D8 and BW1 controls write to D9:D17. PIN NAME SYMBOL PIN NUMBERS DESCRIPTION K, K 6B, 6A Input Clock C, C 6P, 6R Input Clocks for Output data SA 9A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R Address Inputs D0-17 10P,11N,11M,10K,11J,11G,10E,11D,11C,3B,3C,2D, 3F,2G,3J,3L,3M,2N Data Inputs Q0-17 11P,10M,11L,11K,10J,11F,11E,10C,11B,2B,3D,3E, 2F,3G,3K,2L,3N,3P W 4A Write Control R 8A Read Control NOTE 1 Data Outputs BW0, BW1 7B, 5A Byte Write Control Pin VREF 2H,10H Input Reference Voltage ZQ 11H Output Driver Impedance Control Input VDD 5F,7F,5G,7G,5H,7H,5J,7J,5K,7K Power Supply ( 2.5V ) VDDQ 4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L Output Power Supply ( 1.5V or 1.8V ) VSS 2A,10A,4C,8C,4D-8D,5E-7E, 6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N Ground TMS 10R JTAG Test Mode Select TDI 11R JTAG Test Data Input TCK 2R JTAG Test Clock TDO 1R JTAG Test Data Output NC 3A,7A,1B,5B,9B,10B,1C,2C,9C,1D,9D, 10D,1E,2E,9E,1F,9F,10F,1G,9G,10G,1H,1J,2J,9J,1K, 2K,9J,1L,9L,10L,1M,2M,9M,1N,9N,10N,1P,2P,9P No Connect 2 3 Notes: 1. C, C, K or K cannot be set to VREF voltage. 2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected. 3. Not connected to chip pad internally. -3- Mar. 2004 Rev 1.0 K7Q163662B K7Q161862B 512Kx36 & 1Mx18 QDRTM b2 SRAM PIN CONFIGURATIONS(TOP VIEW) K7Q163662B(512Kx36) 1 2 3 4 5 6 7 8 9 10 11 A NC VSS NC W BW2 K BW1 R NC VSS NC B Q27 Q18 D18 SA BW3 K BW0 SA D17 Q17 Q8 C D27 Q28 D19 VSS SA SA SA VSS D16 Q7 D8 D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7 E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6 F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5 G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5 H NC VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4 K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3 L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2 M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2 N D34 D26 Q25 VSS SA SA SA VSS Q10 D9 D1 P Q35 D35 Q26 SA SA C SA SA Q9 D0 Q0 R TDO TCK SA SA SA C SA SA SA TMS TDI Notes : 1. * Checked pins are reserved for higher density address 2. BW0 controls write to D0:D8, BW1 controls write to D9:D17, BW2 controls write to D18:D26 and BW3 controls write to D27:D35. PIN NAME SYMBOL PIN NUMBERS DESCRIPTION K, K 6B, 6A Input Clock C, C 6P, 6R Input Clocks for Output data SA 4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R Address Inputs D0-35 10P,11N,11M,10K,11J,11G,10E,11D,11C,10N,9M,9L 9J,10G,9F,10D,9C,9B,3B,3C,2D,3F,2G,3J,3L,3M,2N 1C,1D,2E,1G,1J,2K,1M,1N,2P Data Inputs Q0-35 11P,10M,11L,11K,10J,11F,11E,10C,11B,9P,9N,10L 9K,9G,10F,9E,9D,10B,2B,3D,3E,2F,3G,3K,2L,3N 3P,1B,2C,1E,1F,2J,1K,1L,2M,1P Data Outputs W 4A Write Control Pin NOTES 1 R 8A Read Control Pin BW0,BW1,BW2,BW3 7B,7A,5A,5B Byte Write Control Pin VREF 2H,10H Input Reference Voltage ZQ 11H Output Driver Impedance Control Input VDD 5F,7F,5G,7G,5H,7H,5J,7J,5K,7K Power Supply ( 2.5V ) VDDQ 4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L Output Power Supply ( 1.5V or 1.8V ) VSS 2A,10A,4C,8C,4D-8D,5E-7E, 6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N Ground TMS 10R JTAG Test Mode Select TDI 11R JTAG Test Data Input TCK 2R JTAG Test Clock TDO 1R JTAG Test Data Output NC 3A,9A,1H No Connect 2 3 Notes: 1. C, C, K or K cannot be set to VREF voltage. 2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected. 3. Not connected to chip pad internally. -4- Mar. 2004 Rev 1.0 K7Q163662B K7Q161862B 512Kx36 & 1Mx18 QDRTM b2 SRAM GENERAL DESCRIPTION The K7Q163662B and K7Q161862B are 18,874,368-bits QDR(Quad Data Rate) Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for K7Q163662B and 1,048,576 words by 18 bits for K7Q161862B. The QDR operation is possible by supporting DDR read and write operations through separate data output and input ports with the same cycle. Memory bandwidth is maxmized as data can be transfered into sram on every rising edge of K and K, and transfered out of sram on every rising edge of C and C. And totally independent read and write ports eliminate the need for high speed bus turn around. Address, data inputs, and all control signals are synchronized to the input clock ( K or K ). Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high, the data outputs are synchronized to the input clocks ( K and K ). Read address is registered on rising edges of the input K clocks, and write address is registered on rising edges of the input K clocks. Common address bus is used to access address both for read and write operations. The internal burst counter is fiexd to 2-bit sequential for both read and write operations. Synchronous pipeline read and early write enable high speed operations. Simple depth expansion is accomplished by using R and W for port selection. Byte write operation is supported with BW0 and BW1 ( BW2 and BW3 ) pins. IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system. The K7Q163662B and K7Q161862B are implemented with SAMSUNG's high performance 6T CMOS technology and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce. Read Operations Read cycles are initiated by activating R at the rising edge of the positive input clock K. Address is presented and stored in the read address register synchronized with K clock. For 2-bit burst DDR operation, it will access two 36-bit or 18-bit data words with each read command. The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge. Next burst data is triggered by the rising edge of following C clock rising edge. Continuous read operations are initiated with K clock rising edge. And pipelined data are transferred out of device on every rising edge of both C and C clocks. In case C and C tied to high, output data are triggered by K and K instead of C and C. When the R is disabled after a read operation, the K7Q163662B and K7Q161862B will first complete burst read operation before entering into deselect mode at the next K clock rising edge. Then output drivers disabled automatically to high impedance state. -5- Mar. 2004 Rev 1.0 K7Q163662B K7Q161862B 512Kx36 & 1Mx18 QDRTM b2 SRAM Write Operations Write cycles are initiated by activating W at the rising edge of the positive input clock K. Address is presented and stored in the write address register synchronized with following K clock. For 2-bit burst DDR operation, it will write two 36-bit or 18-bit data words with each write command. The first "early" data is transfered and registered in to the device synchronous with same K clock rising edge with W presented. Next burst data is transfered and registered synchronous with following K clock rising edge. Continuous write operations are initiated with K rising edge. And "early writed" data is presented to the device on every rising edge of both K and K clocks. When the W is disabled, the K7Q163662B and K7Q161862B will enter into deselect mode. The device disregards input data presented on the same cycle W disabled. The K7Q163662B and K7Q161862B support byte write operations. With activating BW0 or BW1 ( BW2 or BW3 ) in write cycle, only one byte of input data is presented. In K7Q161862B, BW0 controls write operation to D0:D8, BW1 controls write operation to D9:D17. And in K7Q163662B BW2 controls write operation to D18:D26, BW3 controls write operation to D27:D35. Programmable Impedance Output Buffer Operation The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to VSS through a precision resistor(RQ). The value of RQ (within 15%) is five times the output impedance desired. For example, 250Ω resistor will give an output impedance of 50Ω. Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles. In all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior in the SRAM. There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the SRAM needs 1024 non-read cycles. Single Clock Mode The K7Q163662B and K7Q161862B can be used with the single clock pair K and K. In this mode, C and C must be tied high during power up and this single clock pair control both the input and output registers. C and C cannot be tied high during operation. System flight time and clock skew could not be compensated in single clock mode. Depth Expansion Separate input and output ports enables easy depth expansion. Each port can be selected and deselected independently and read and write operation do not affect each other. Before chip deselected, all read and write pending operations are completed. -6- Mar. 2004 Rev 1.0 K7Q163662B K7Q161862B 512Kx36 & 1Mx18 QDRTM b2 SRAM STATE DIAGRAM POWER-UP READ NOP WRITE READ READ READ WRITE LOAD NEW READ ADDRESS ALWAYS (FIXED) WRITE NOP LOAD NEW WRITE ADDRESS READ WRITE WRITE ALWAYS (FIXED) DDR WRITE DDR READ Notes: 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1. 2. "READ" refers to read active status with R=Low, "READ" refers to read inactive status with R=high. "WRITE" and "WRITE" are the same case. 3. Read and write state machine can be active simultaneously. 4. State machine control timing sequence is controlled by K. -7- Mar. 2004 Rev 1.0 K7Q163662B K7Q161862B 512Kx36 & 1Mx18 QDRTM b2 SRAM TRUTH TABLES SYNCHRONOUS TRUTH TABLE K R D W Q OPERATION D(A0) D(A1) Q(A0) Q(A1) Stopped X X Previous state Previous state Previous state Previous state Clock Stop ↑ H H X X High-Z High-Z No Operation ↑ L X X X DOUT at C(t+1) DOUT at C(t+1) Read ↑ X L Din at K(t) Din at K(t) X X Write Notes: 1. X means "Don′t Care". 2. The rising edge of clock is symbolized by ( ↑ ). 3. Before enter into clock stop status, all pending read and write operations will be completed. WRITE TRUTH TABLE(x18) K K ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ W BW0 BW1 OPERATION H X X READ/NOP H X X READ/NOP L L L WRITE ALL BYTEs ( K↑ ) L L L WRITE ALL BYTEs ( K↑ ) L L H WRITE BYTE 0 ( K↑ ) L L H WRITE BYTE 0 ( K↑ ) L H L WRITE BYTE 1 ( K↑ ) L H L WRITE BYTE 1 ( K↑ ) L H H WRITE NOTHING ( K↑ ) L H H WRITE NOTHING ( K↑ ) Notes: 1. X means "Don′t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK( ↑ ). WRITE TRUTH TABLE(x36) K K ↑ W BW0 BW1 BW2 BW3 OPERATION H X X X X READ/NOP ↑ H X X X X READ/NOP L L L L L WRITE ALL BYTEs ( K↑ ) ↑ L L L L L WRITE ALL BYTEs ( K↑ ) L L H H H WRITE BYTE 0 ( K↑ ) L L H H H WRITE BYTE 0 ( K↑ ) L H L H H WRITE BYTE 1 ( K↑ ) L H L H H WRITE BYTE 1 ( K↑ ) L H H L L WRITE BYTE 2 and BYTE 3 ( K↑ ) L H H L L WRITE BYTE 2 and BYTE 3 ( K↑ ) L H H H H WRITE NOTHING ( K↑ ) L H H H H WRITE NOTHING ( K↑ ) ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ Notes: 1. X means "Don′t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK( ↑ ). -8- Mar. 2004 Rev 1.0 K7Q163662B K7Q161862B 512Kx36 & 1Mx18 QDRTM b2 SRAM ABSOLUTE MAXIMUM RATINGS* PARAMETER SYMBOL RATING UNIT Voltage on VDD Supply Relative to VSS VDD -0.5 to 3.6 V Voltage on VDDQ Supply Relative to VSS VDDQ -0.5 to VDD V VIN -0.5 to VDD+0.3 V Voltage on Input Pin Relative to VSS Storage Temperature TSTG -65 to 150 °C Operating Temperature TOPR 0 to 70 °C Storage Temperature Range Under Bias TBIAS -10 to 85 °C *Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDDQ must not exceed VDD during normal operation. DC ELECTRICAL CHARACTERISTICS MIN MAX Input Leakage Current PARAMETER SYMBOL IIL VDD=Max ; VIN=VSS to VDDQ -2 +2 µA Output Leakage Current IOL Output Disabled, -2 +2 µA -16 - 400 mA 1,5 -16 - 500 mA 1,5 -16 - 240 mA 1,6 Operating Current (x18) : DDR ICC Operating Current (x36) : DDR ICC Standby Current(NOP) : DDR ISB1 TEST CONDITIONS VDD=Max , IOUT=0mA Cycle Time ≥ tKHKH Min VDD=Max , IOUT=0mA Cycle Time ≥ tKHKH Min UNIT NOTES Device deselected, IOUT=0mA, f=Max, All Inputs≤0.2V or ≥ VDD-0.2V Output High Voltage VOH1 VDDQ/2 VDDQ V 2,7 Output Low Voltage VOL1 VSS VDDQ/2 V 3,7 Output High Voltage VOH2 IOH=-1.0mA VDDQ-0.2 VDDQ V 4 VOL2 IOL=1.0mA VSS 0.2 V 4 Output Low Voltage Input Low Voltage VIL -0.3 VREF-0.1 V 8,9 Input High Voltage VIH VREF+0.1 VDDQ+0.3 V 8,10 Notes: 1. Minimum cycle. IOUT=0mA. 2. |IOH|=(VDDQ/2)/(RQ/5)±15% @VOH=VDDQ/2 for 175Ω ≤ RQ ≤ 350Ω. 3. |IOL|=(VDDQ/2)/(RQ/5)±15% @VOL=VDDQ/2 for 175Ω ≤ RQ ≤ 350Ω. 4. Minimum Impedance Mode when ZQ pin is connected to VDD. 5. Operating current is calculated with 50% read cycles and 50% write cycles. 6. Standby Current is only after all pending read and write burst opeactions are completed. 7. Programmable Impedance Mode. 8. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters. 9. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.5V(pulse width ≤ 3ns). 10. VIH (Max)DC=VDDQ+0.3, VIH (Max)AC=VDDQ+0.85V(pulse width ≤ 3ns). -9- Mar. 2004 Rev 1.0 K7Q163662B K7Q161862B 512Kx36 & 1Mx18 QDRTM b2 SRAM Overershoot Timing Undershoot Timing 20% tKHKH(MIN) VIH VDDQ+0.7V VDDQ+0.35V VSS VDDQ VSS-0.35V VSS-0.7V 20% tKHKH(MIN) VIL RECOMMENDED DC OPERATING CONDITIONS (0°C ≤ TA ≤ 70°C) PARAMETER Supply Voltage SYMBOL MIN TYP MAX UNIT VDD 1.7 2.5 2.6 V VDDQ 1.4 1.5 1.9 V Reference Voltage VREF 0.68 0.75 0.95 V Ground VSS 0 0 0 V UNITS NOTES AC TIMING CHARACTERISTICS PARAMETER SYMBOL -16 MIN MAX Clock Clock Cycle Time(K, K, C, C) tKHKH 6.0 ns Clock HIGH time (K, K, C, C) tKHKL 2.4 ns Clock Low time (K, K, C, C) tKLKH 2.4 ns Clock to clock (K↑ → K↑, C↑ → C↑) tKHKH 2.7 3.3 ns Clock to data clock (K↑ → C↑, K↑→ C↑) tKHCH 0.0 2.0 ns 2.5 ns ns 3 2.5 ns 3 3 Output Times C, C High to Output Valid tCHQV C, C High to Output Hold tCHQX C High to Output High-Z tCHQZ C High to Output Low-Z tCHQX1 1.2 ns Address valid to K rising edge tAVKH 0.7 ns Control inputs valid to K rising edge tIVKH 0.7 ns Data-in valid to K, K rising edge tDVKH 0.7 ns K rising edge to address hold tKHAX 0.7 v K rising edge to control inputs hold tKHIX 0.7 ns K, K rising edge to data-in hold tKHDX 0.7 ns 1.2 3 Setup Times 2 Hold Times Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges. 2. Control signals are R, W,BW0,BW1 and (BW2, BW3, also for x36) 3. If C,C are tied high, K,K become the references for C,C timing parameters. 4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention beacuse tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0°C, 2.6V) than tCHQZ, which is a MAX parameter(worst case at 70°C, 2.4V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature. - 10 - Mar. 2004 Rev 1.0 K7Q163662B K7Q161862B 512Kx36 & 1Mx18 QDRTM b2 SRAM AC TEST CONDITIONS Parameter Symbol Value Unit VDD 1.7~2.6 V VDDQ 1.4~1.9 V VIH/VIL 1.25/0.25 V Core Power Supply Voltage Output Power Supply Voltage Input High/Low Level Input Reference Level VREF 0.75 V Input Rise/Fall Time TR/TF 0.3/0.3 ns VDDQ/2 V Output Timing Reference Level AC TEST OUTPUT LOAD VREF 0.75V VDDQ/2 50Ω SRAM Zo=50Ω 250Ω ZQ Note: Parameters are tested with RQ=250Ω PIN CAPACITANCE PRMETER SYMBOL Address Control Input Capacitance TESTCONDITION TYP MAX Unit CIN VIN=0V 4 5 pF Input and Output Capacitance COUT VOUT=0V 6 7 pF Clock Capacitance CCLK - 5 6 pF NOTES Note: 1. Parameters are tested with RQ=250Ω and VDDQ=1.5V. 2. Periodically sampled and not 100% tested. APPLICATION INFORMATION 1Mx18 SRAM#1 SRAM#4 R=250Ω ZQ Q0-17 D0-17 SA R W BW0 BW1 C C K K Vt R Data In Data Out Address R W BW0-7 R=250Ω D0-17 SA R ZQ Q0-17 RW BW0 BW1 C C K K Vt Vt MEMORY CONTROLLER Return CLK Source CLK Return CLK Source CLK Vt Vt R=50Ω Vt=VREF - 11 - Mar. 2004 Rev 1.0 K7Q163662B K7Q161862B 512Kx36 & 1Mx18 QDRTM b2 SRAM TIMING WAVE FORMS OF READ AND NOP READ READ NOP READ tKHKH tKLKH K tKHKL tKHKH K tAVKH tKHAX A1 SA A2 A3 tIVKH tKHIX R tCHQX1 Q1-1 Q(Data Out) Q1-2 Q2-1 Q2-2 Q3-1 Q3-2 tCHQX tKHCH C tCHQZ tCHQV C tCHQV Don′t Care Undefined Note: 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0. 2. Outputs are disabled(High-Z) one cycle after a NOP. TIMING WAVE FORMS OF WRITE AND NOP WRITE WRITE NOP WRITE NOP tKHKH tKLKH K tKHKL tKHKH K tAVKH A1 SA tKHAX A2 A3 tIVKH tKHIX W tKHIX D(Data In) D1-1 D1-2 D2-1 D2-2 D3-1 tDVKH - 12 - D3-2 tKHDX Mar. 2004 Rev 1.0 K7Q163662B K7Q161862B 512Kx36 & 1Mx18 QDRTM b2 SRAM TIMING WAVE FORMS OF READ, WRITE AND NOP READ WRITE READ WRITE READ WRITE NOP WRITE K K SA A1 A2 A3 D2-1 D2-2 D4-1 A4 A5 A6 D4-2 D6-1 D6-2 A7 W R D(Data In) Q(Data Out) Q1-1 Q1-2 Q3-1 D7-1 Q3-2 D7-2 Q5-1 Q5-2 C C Don′t Care Undefined Note: 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0. 2. Outputs are disabled(High-Z) one cycle after a NOP. 3. If address A1=A2, data Q1-1=D2-1, data Q1-2=D2-2. Write data is forwarded immediately as read results. 4. BWx are assumed active. - 13 - Mar. 2004 Rev 1.0 K7Q163662B K7Q161862B 512Kx36 & 1Mx18 QDRTM b2 SRAM IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a resistor. TDO should be left unconnected. JTAG Block Diagram JTAG Instruction Coding IR2 IR1 IR0 TDO Output Notes 0 0 0 EXTEST Boundary Scan Register 1 0 0 1 IDCODE Identification Register 3 0 1 0 SAMPLE-Z Boundary Scan Register 2 A,D 0 1 1 RESERVED Do Not Use 6 K,K 1 0 0 SAMPLE Boundary Scan Register 5 1 0 1 RESERVED Do Not Use 6 1 1 0 RESERVED Do Not Use 6 1 1 1 BYPASS Bypass Register 4 C,C SRAM CORE Q CQ CQ TDI BYPASS Reg. TDO Identification Reg. Instruction Reg. Control Signals TMS TCK TAP Controller Instruction NOTE : 1. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. This instruction is not IEEE 1149.1 compliant. 2. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. 3. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The Bypass Register also holds serially loaded TDI when exiting the Shift DR states. 5. SAMPLE instruction dose not places DQs in Hi-Z. 6. This instruction is reserved for future use. TAP Controller State Diagram 1 Test Logic Reset 0 0 Run Test Idle 1 1 Select DR 0 Exit2 DR 1 1 Update DR 0 - 14 - 1 Capture IR 0 0 Shift IR 1 1 Exit1 DR 0 Pause DR 1 Select IR 0 1 Capture DR 0 Shift DR 1 1 1 0 0 0 Exit1 IR 0 Pause IR 1 Exit2 IR 1 Update IR 1 0 0 0 Mar. 2004 Rev 1.0 K7Q163662B K7Q161862B 512Kx36 & 1Mx18 QDRTM b2 SRAM SCAN REGISTER DEFINITION Part Instruction Register Bypass Register ID Register 512Kx36 3 bits 1 bit 32 bits Boundary Scan 107 bits 1Mx18 3 bits 1 bit 32 bits 107 bits ID REGISTER DEFINITION Part Revision Number (31:29) Part Configuration (28:12) Samsung JEDEC Code (11: 1) Start Bit(0) 512Kx36 000 00def0wx0t0q0b0s0 00001001110 1 1Mx18 000 00def0wx0t0q0b0s0 00001001110 1 Note : Part Configuration /def=001 for 16Mb, /wx=11 for x36, 10 for x18. /t=Don’t Care. /q=1 for QDR, 0 for DDR /b=1 for 4Bit Burst, 0 for 2Bit Burst /s=1 for Separate I/O, 0 for Common I/O BOUNDARY SCAN EXIT ORDER ORDER PIN ID ORDER PIN ID 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H 10G 9G 11F 11G 9F 10F 11E 10E 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A Internal 9A 8B 7C 6C 8A 7A 7B 6B 6A 5B 5A 4A 5C 4B 3A 1H 1A 2B 3B 1C 1B 3D 3C 1D ORDER 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 PIN ID 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R Note: 1. NC pins are read as "X" ( i.e. don′t care.) - 15 - Mar. 2004 Rev 1.0 K7Q163662B K7Q161862B 512Kx36 & 1Mx18 QDRTM b2 SRAM JTAG DC OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit Power Supply Voltage VDD 1.7 2.5 2.6 V Input High Level VIH 0.7*VDD - VDD+0.3 V Input Low Level VIL -0.3 - 0.3*VDD V Output High Voltage(IOH=-2mA) VOH 0.75*VDD - VDD V Output Low Voltage(IOL=2mA) VOL VSS - 0.25*VDD V Note Note: 1. The input level of SRAM pin is to follow the SRAM DC specification. JTAG AC TEST CONDITIONS Parameter Symbol Min Unit Input High/Low Level VIH/VIL VDD/0.0 V Input Rise/Fall Time TR/TF 1.0/1.0 ns VDD/2 V Input and Output Timing Reference Level Note 1 Note: 1. See SRAM AC test output load on page 11. JTAG AC Characteristics Parameter Symbol Min Max Unit TCK Cycle Time tCHCH 50 - ns TCK High Pulse Width tCHCL 20 - ns TCK Low Pulse Width tCLCH 20 - ns TMS Input Setup Time tMVCH 5 - ns TMS Input Hold Time tCHMX 5 - ns TDI Input Setup Time tDVCH 5 - ns TDI Input Hold Time tCHDX 5 - ns SRAM Input Setup Time tSVCH 5 - ns SRAM Input Hold Time tCHSX 5 - ns Clock Low to Output Valid tCLQV 0 10 ns Note JTAG TIMING DIAGRAM TCK tCHCH tCHCL tMVCH tCHMX tDVCH tCHDX tSVCH tCHSX tCLCH TMS TDI PI (SRAM) tCLQV TDO - 16 - Mar. 2004 Rev 1.0 K7Q163662B K7Q161862B 512Kx36 & 1Mx18 QDRTM b2 SRAM 165 FBGA PACKAGE DIMENSIONS 13mm x 15mm Body, 1.0mm Bump Pitch, 11x15 Ball Array B Top View A C Side View D A G E B F Bottom View ∅H E Symbol Value Units Note Symbol Value Units A 13 ± 0.1 mm E 1.0 mm B 15 ± 0.1 mm F 14.0 mm C 1.3 ± 0.1 mm G 10.0 mm D 0.35 ± 0.05 mm H 0.5 ± 0.05 mm - 17 - Note Mar. 2004 Rev 1.0