SAMSUNG KBE00G003M

KBE00G003M-D411
MCP MEMORY
NNDD512512256256BBFF
NAND 512Mb*2 + Mobile SDRAM 256Mb*2
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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MCP MEMORY
Document Title
Multi-Chip Package MEMORY
512M Bit(64Mx8) Nand Flash*2 / 256M Bit(8Mx8x4Banks) Mobile SDRAM*2
Revision History
Revision No. History
Draft Date
0.0
Initial issue.
- 1Gb NAND Flash DDP B-Die _ Ver 0.1
- 512Mb Mobile SDRAM DDP F-Die _ Ver 1.0
0.1
<Mobile SDRAM> .... Ver 1.1
- Corrected Errata in Capacitance value
Remark
November 26, 2004 Preliminary
July 15, 2005
Revision
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s web site.
http://samsungelectronics.com/semiconductors/products/products_index.html
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
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KBE00G003M-D411
MCP MEMORY
Multi-Chip Package MEMORY
512M Bit(64Mx8) Nand Flash*2 / 256M Bit(8Mx8x4Banks) Mobile SDRAM*2
FEATURES
<Common>
• Operating Temperature : -25°C ~ 85°C
• Package : 107ball FBGA Type - 10.5mmx13mm, 0.8mm pitch
<NAND>
• Power Supply Voltage : 1.7~ 1.95V
• Organization
- Memory Cell Array : (128M + 4096K)bit x 8 bit
- Data Register : (512 + 16)bit x 8bit
• Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase : (16K + 512)Byte
• Page Read Operation
- Page Size : (512 + 16)Byte
- Random Access : 15µs(Max.)
- Serial Page Access : 50ns(Min.)
• Fast Write Cycle Time
- Program time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
• Command Register Operation
• Intelligent Copy-Back
• Unique ID for Copyright Protection
<Mobile SDRAM>
• Power Supply Voltage : 1.7~1.95V
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
-. DS (Driver Strength)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (8K cycle).
• 1/CS Support.
Address configuration
Organization
Bank
Row
Column Address
32M x 16
BA0, BA1
A0 - A12
A0 - A9
GENERAL DESCRIPTION
The KBE00G003M is a Multi-Chip Package Memory which combines 1Gbit Nand Flash Memory(organized with two pieces of
512Mbit Nand Flash Memory) and 512Mbit synchronous high data rate Dynamic RAM. (organized with two pieces of 256Mbit Mobile
SDRAM) 1Gbit NAND Flash memory is organized as 128M x8 bits and 512Mbit Mobile SDRAM is organized as 8M x16 bits x4 banks
In 1Gbit NAND Flash, its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program
operation can be performed in typically 200µs on the 528-byte page and an erase operation can be performed in typically 2ms on a
16K-byte block. Data in the data register can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and
data input/output as well as command inputs. The on-chip write controller automates all program and erase functions including pulse
repetition, where required, and internal verify and margining of data. Even the write-intensive systems can take advantage of the
extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm.
This device is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.
In 512Mbit SDRAM, Synchronous design make a device controlled precisely with the use of system clock and I/O transactions are
possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the
same device to be useful for a variety of high bandwidth, high performance memory system applications.
The KBE00G003A is suitable for use in data memory of mobile communication system to reduce not only mount area but also power
consumption. This device is available in 107-ball FBGA Type.
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MCP MEMORY
PIN CONFIGURATION
1
A
B
2
3
4
5
6
7
8
DNU
9
10
DNU
DNU
DNU
NC
DQ0
Vdd
Vss
Vcc
NC
A3
NC
C
Vss
DQ2
DQ1
CLE
CE
A0
A1
A2
D
Vddq
DQ4
DQ3
ALE
WE
BA0
BA1
A10
E
Vssq
DQ6
DQ5
RE
R/B
RAS
NC
CS
F
Vddq
NC
DQ7
WP
NC
CAS
WEd
Vss
G
Vss
LDQM
NC
NC
NC
A12
CKE
Vdd
H
Vdd
UDQM
CLK
NC
NC
A8
A9
A11
J
Vssq
NC
DQ8
IO0
IO2
IO4
IO6
A7
K
Vddq
DQ9
DQ10
NC
NC
NC
NC
A6
L
Vssq
DQ11
DQ12
IO1
IO3
IO5
IO7
A5
M
Vdd
DQ13
DQ14
NC
NC
NC
NC
A4
DQ15
Vss
Vss
Vccq
Vcc
Vss
NC
DNU
DNU
DNU
DNU
N
DNU
NC
P
DNU
DNU
107 FBGA: Top View (Ball Down)
NAND
M-SDR
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MCP MEMORY
PIN DESCRIPTION
Pin Name
Pin Name
Pin Function(Mobile SDRAM)
Pin Function(NAND Flash)
CLK
System Clock
CE
Chip Enable
CKE
Clock Enable
RE
Read Enable
Write Protection
Chip Select
WP
RAS
Row Address Strobe
WE
Write Enable
CAS
Column Address Strobe
ALE
Address Latch Enable
WEd
Write Enable
CLE
Command Latch Enable
A0 ~ A12
Address Input
R/B
Ready/Busy Output
CS
BA0 ~ BA1
IO0 ~ IO7
Bank Address Input
Data Input/Output
LDQM
Lower Input/Output Data Mask
Vcc
Power Supply
UDQM
Upper Input/Output Data Mask
Vccq
Data Out Power
Data Input/Output
Vss
Ground
DQ0 ~ DQ15
Vdd
Power Supply
Vddq
Data Out Power
Pin Name
NC
Vss
Ground
Vssq
DQ Ground
DNU
Pin Function
No Connection
Do Not Use
ORDERING INFORMATION
KB E
00 G 0 0 3 M - D 411
Samsung
MCP Memory(4chips)
Access Time
411 : NAND Flash 50ns
NAND Flash 50ns
Mobile SDRAM 9ns
Mobile SDRAM 9ns
Device Type
NAND + NAND + SDRAM+SDRAM
NOR Flash Density, Voltage,
Organization, Bank Size, Boot Block
00 = None
Package
D = FBGA(Lead-Free)
NAND Flash Density, Voltage, Organization
F = 512M+512M, 1.8V/1.8V, x8
Version
M = 1st Generation
UtRAM Density, Voltage, Organization
0 = None
SDRAM Interface, Density,
Voltage, Organization, Option
3 = M-SDR, 256M+256M, 1.8V/1.8V, x16
SRAM Density, Voltage, Organization
0 = None
NOTE :
1. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.
Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific purpose,
such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
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MCP MEMORY
FUNCTIONAL BLOCK DIAGRAM
Vcc
Vccq
Vss
CE
RE
WP
1Gb NAND
Flash Memory
WE
IO0 to IO7
ALE
CLE
R/B
Vdd
Vddq
Vss
Vssq
CLK
CKE
CS
RAS
CAS
WEd
512Mb Mobile
SDRAM
DQ0 to DQ15
A0~A12
BA0~BA1
LDQM
UDQM
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MCP MEMORY
1Gb(128Mb x 8)
NAND Flash DDP B-Die
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MCP MEMORY
PIN DESCRIPTION
Pin Name
Pin Function
I/O0 ~ I/O7
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
CLE
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ALE
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CE
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase operation. Regarding CE control during
read operation, refer to ’Page read’ section of Device operation .
RE
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WE
WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WP
WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
R/B
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
VccQ
OUTPUT BUFFER POWER
VccQ is the power supply for Output Buffer.
VccQ is internally connected to Vcc, thus should be biased to Vcc.
Vcc
POWER
VCC is the power supply for device.
Vss
GROUND
N.C
NO CONNECTION
Lead is not internally connected.
DNU
DO NOT USE
Leave it disconnected.
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
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MCP MEMORY
Figure 1. Functional Block Diagram
VCC
VSS
A9 - A26
X-Buffers
Latches
& Decoders
A0 - A7
Y-Buffers
Latches
& Decoders
1,024M + 32M Bit
NAND Flash
ARRAY
(512 + 16)Byte x 262,144
Page Register & S/A
A8
Y-Gating
Command
Command
Register
Control Logic
& High Voltage
Generator
CE
RE
WE
VCC
VSS
I/O Buffers & Latches
Output
Driver
Global Buffers
I/0 0
I/0 7
CLE ALE WP
Figure 2. Array Organization
1 Block = 32 Pages
(16K + 512) Byte
256K Pages
(=8,192 Blocks)
1st half Page Register
2nd half Page Register
(=256 Bytes)
(=256 Bytes)
1 Page = 528 Bytes
1 Block = 528 B x 32 Pages
= (16K + 512) Bytes
1 Device = 528B x 32Pages x 8,192 Blocks
= 1,056 Mbits
8 bit
512B Bytes
16 Bytes
I/O 0 ~ I/O 7
Page Register
512 Bytes
16 Bytes
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
1st Cycle
A0
A1
A2
A3
A4
A5
A6
A7
2nd Cycle
A9
A10
A11
A12
A13
A14
A15
A16
3rd Cycle
A17
A18
A19
A20
A21
A22
A23
A24
4th Cycle
A25
A26
*L
*L
*L
*L
*L
*L
Column Address
Row Address
(Page Address)
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* L must be set to "Low".
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MCP MEMORY
Product Introduction
This device is a 1,026Mbit(1,107,296,436 bit) memory organized as 262,144 rows(pages) by 528 columns. Spare sixteen columns
are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data
transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16
cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two
NAND structured strings. A NAND structure consists of 16 cells. Total 135168 NAND cells reside in a block. The array organization is
shown in Figure 2. The program and read operations are executed on a page basis, while the erase operation is executed on a block
basis. The memory array consists of 8,192 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is prohibited on this device.
This device has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems upgrades to
future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch
Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. The 128M byte physical space requires 27
addresses, thereby requiring four cycles for byte-level addressing: column address, low row address and high row address, in that
order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the
command register. Table 1 defines the specific commands of this device.
The device provides simultaneous program/erase capability up to four pages/blocks. By dividing the memory array into eight 128Mbit
separate planes, simultaneous multi-plane operation dramatically increases program/erase performance by 4X while still maintaining
the conventional 512 byte structure.
The extended pass/fail status for multi-plane program/erase allows system software to quickly identify the failing page/block out of
selected multiple pages/blocks. Usage of multi-plane operations will be described further throughout this document.
In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
of the same plane without the need for transporting the data to and from the external buffer memory. Since the time-consuming burstreading and data-input cycles are removed, system performance for solid-state disk application is significantly increased.
Table 1. Command Sets
1st. Cycle
2nd. Cycle
3rd. Cycle
Read 1
Function
00h/01h(1)
-
-
Read 2
50h
-
-
Read ID
90h
-
-
Reset
FFh
-
-
Page Program (True)(2)
80h
10h
-
80h
11h
-
Page Program (Dummy)(2)
Acceptable Command during Busy
O
Copy-Back Program(True)
00h
8Ah
10h
Copy-Back Program(Dummy)(2)
03h
8Ah
11h
Block Erase
60h
D0h
-
60h---60h
D0h
-
70h
-
-
O
-
-
O
(2)
Multi-Plane Block Erase
Read Status
Read Multi-Plane Status
(3)
71h
NOTE : 1. The 00h command defines starting address of the 1st half of registers.
The 01h command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the status pointer is
automatically moved to the 1st half register(00h) on the next cycle.
2. Page Program(True) and Copy-Back Program(True) are available on 1 plane operation.
Page Program(Dummy) and Copy-Back Program(Dummy) are available on the 2nd,3rd,4th plane of multi plane operation.
3. The 71h command should be used for read status of Multi Plane operation.
4. Multi plane operation and Copy-Back Program are not supported with 1.8V device.
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
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MCP MEMORY
Memory Map
The device is arranged in eight 128Mbit memory planes. Each plane contains 1,024 blocks and 528 byte page registers. This allows it
to perform simultaneous page program and block erase by selecting one page or block from each plane. The block address map is
configured so that multi-plane program/erase operations can be executed for every four sequential blocks by dividing the memory
array into plane 0~3 or plane 4~7 separately. For example, multi-plane program/erase operations into plane 2,3,4 and 5 are prohibited.
Figure 3. Memory Array Map
Plane 0
(1024 Block)
Block 0
Page 0
Page 1
Page 30
Page 31
Block 4092
Plane 2
(1024 Block)
Plane 1
(1024 Block)
Block 2
Block 1
Plane 3
(1024 Block)
Block 3
Page 0
Page 0
Page 0
Page 1
Page 1
Page 1
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Block 4094
Block 4093
Block 4095
Page 0
Page 0
Page 0
Page 0
Page 1
Page 1
Page 1
Page 1
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
528byte Page Registers
528byte Page Registers
528byte Page Registers
528byte Page Registers
Plane 4
(1024 Block)
Plane 5
(1024 Block)
Plane 6
(1024 Block)
Plane 7
(1024 Block)
Block 4096
Block 4098
Block 4097
Block 4099
Page 0
Page 0
Page 0
Page 0
Page 1
Page 1
Page 1
Page 1
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Block 8188
Block 8190
Block 8189
Block 8191
Page 0
Page 0
Page 0
Page 0
Page 1
Page 1
Page 1
Page 1
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
528byte Page Registers
528byte Page Registers
528byte Page Registers
528byte Page Registers
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MCP MEMORY
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to VSS
Symbol
Rating
VIN/OUT
-0.6 to + 4.6
VCC
-0.6 to + 4.6
Unit
V
VCCQ
-0.6 to + 4.6
Temperature Under Bias
TBIAS
-40 to +125
Storage Temperature
TSTG
-65 to +150
°C
Short Circuit Current
Ios
5
mA
°C
NOTE :
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND,TA=-25 to 85°C)
Symbol
Min
Typ.
Max
Unit
Supply Voltage
Parameter
VCC
1.70
1.8
1.95
V
Supply Voltage
VCCQ
1.70
1.8
1.95
V
Supply Voltage
VSS
0
0
0
V
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MCP MEMORY
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Parameter
Operating
Current
Symbol
Test Conditions
tRC=50ns, CE=VIL
IOUT=0mA
Min
Typ
Max
-
8
20
Sequential Read
ICC1
Program
ICC2
-
-
8
20
Erase
ICC3
-
-
8
20
Stand-by Current(TTL)
ISB1
CE=VIH, WP=0V/VCC
-
-
1
Stand-by Current(CMOS)
ISB2
CE=VCC-0.2, WP=0V/VCC
-
10
50
Unit
mA
Input Leakage Current
ILI
VIN=0 to Vcc(max)
-
-
±10
Output Leakage Current
ILO
VOUT=0 to Vcc(max)
-
-
±10
I/O pins
VCCQ
-0.4
-
VCCQ
+0.3
Except I/O pins
VCC
-0.4
-
VCC
+0.3
-0.3
-
0.4
VCCQ
-0.1
-
-
Input High Voltage
VIH*
Input Low Voltage, All inputs
VIL*
-
Output High Voltage Level
VOH
IOH=-100µA
Output Low Voltage Level
VOL
IOL=100uA
-
-
0.1
Output Low Current(R/B)
IOL(R/B)
VOL=0.1V
3
4
-
µA
V
mA
NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.
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MCP MEMORY
VALID BLOCK
Parameter
Valid Block Number
Symbol
Min
Typ.
Max
Unit
NVB
4,026
-
4,096
Blocks
NOTE :
1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program
factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase
cycles.
3. Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.
AC TEST CONDITION
(TA=-25 to 85°C, Vcc=1.65V~1.95V unless otherwise noted)
Parameter
Value
Input Pulse Levels
0V to VccQ
Input Rise and Fall Times
5ns
Input and Output Timing Levels
VccQ/2
Output Load (VccQ:1.8V +/-10%)
1 TTL GATE and CL=30pF
CAPACITANCE(TA=25°C, VCC=1.8V, f=1.0MHz)
Symbol
Test Condition
Min
Max
Input/Output Capacitance
Item
CI/O
VIL=0V
-
10
Unit
pF
Input Capacitance
CIN
VIN=0V
-
10
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
ALE
CE
RE
WP
H
L
L
WE
H
X
Mode
L
H
L
H
X
H
L
L
H
H
L
H
L
H
H
L
L
L
H
H
L
L
L
H
X
X
X
X
H
X
X
X
X
X
H
During Program(Busy)
X
X
X
X
X
H
During Erase(Busy)
X
X(1)
X
X
X
L
Write Protect
X
X
H
X
X
Read Mode
Command Input
Address Input(4clock)
Write Mode
Command Input
Address Input(4clock)
Data Input
X
Data Output
X
During Read(Busy)
0V/VCC(2) Stand-by
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
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MCP MEMORY
PROGRAM / ERASE CHARACTERISTICS
Parameter
Program Time
Dummy Busy Time for Multi Plane Program
Min
Typ
Max
tPROG(1)
-
200
500
µs
1
10
µs
-
1
cycle
-
-
2
cycles
-
2
3
ms
tDBSY
Main Array
Number of Partial Program Cycles
in the Same Page
Symbol
Spare Array
Block Erase Time
-
Nop
tBERS
Unit
NOTE : 1.Typical program time is defined as the time within more than 50% of the whole pages are programmed at Vcc of 3.3V and 25’C
AC TIMING CHARACTERISTICS FOR COMMAND / ADDRESS / DATA INPUT
Parameter
Symbol
Min
Max
Unit
CLE setup Time
tCLS
0
0
0
-
-
-
ns
CLE Hold Time
tCLH
10
10
10
-
-
-
ns
CE setup Time
tCS
0
0
0
-
-
-
ns
CE Hold Time
tCH
10
10
10
-
-
-
ns
WE Pulse Width
tWP
25
25(1)
25(1)
-
-
-
ns
ALE setup Time
tALS
0
0
0
-
-
-
ns
ALE Hold Time
tALH
10
10
10
-
-
-
ns
Data setup Time
tDS
20
20
20
-
-
-
ns
Data Hold Time
tDH
10
10
10
-
-
-
ns
Write Cycle Time
tWC
45
45
45
-
-
-
ns
WE High Hold Time
tWH
15
15
15
-
-
-
ns
NOTE: 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
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MCP MEMORY
AC CHARACTERISTICS FOR OPERATION
Symbol
Min
Max
Unit
Data Transfer from Cell to Register
Parameter
tR
-
15
µs
ALE to RE Delay
tAR
10
-
ns
CLE to RE Delay
tCLR
10
-
ns
Ready to RE Low
tRR
20
-
ns
RE Pulse Width
tRP
25
-
ns
WE High to Busy
tWB
-
100
ns
Read Cycle Time
tRC
50
-
ns
RE Access Time
tREA
-
35
ns
CE Access Time
tCEA
-
45
ns
RE High to Output Hi-Z
tRHZ
-
30
ns
CE High to Output Hi-Z
tCHZ
-
20
ns
RE or CE High to Output hold
tOH
15
-
ns
RE High Hold Time
tREH
15
-
ns
tIR
0
-
ns
WE High to RE Low
tWHR
60
-
ns
Device resetting time(Read/Program/Erase)
tRST
-
5/10/500(1)
µs
Output Hi-Z to RE Low
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MCP MEMORY
NAND Flash Technical Notes
Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.
The information regarding the initial invalid block(s) is so called as the initial invalid block information. Devices with initial invalid
block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid
block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a
select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is
placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase cycles.
Identifying Initial Invalid Block(s)
All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The
initial invalid block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of
every initial invalid block has non-FFh data at the column address of 517. Since the initial invalid block information is also erasable
in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize
the initial invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 4). Any intentional erasure of the initial invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Create (or update)
Initial Invalid Block(s) Table
No
*
Check "FFh" at the column address 512
of the 1st and 2nd page in the block
Check "FFh" ?
Yes
No
Last Block ?
Yes
End
Figure 4. Flow chart to create initial invalid block table.
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MCP MEMORY
NAND Flash Technical Notes (Continued)
Error in write or read operation
Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the block
failure rate.The following possible failure modes should be considered to implement a highly reliable system. In the case of status
read failure after erase or program, block replacement should be done. Because program status fail during a page program does not
affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be
employed. To improve the efficiency of memory space, it is recommended that the read failure due to single bit error should be
reclaimed by ECC without any block replacement. The block failure ratein the qualification report does not include those reclaimed
blocks.
Failure Mode
Write
Read
ECC
Detection and Countermeasure sequence
Erase Failure
Status Read after Erase --> Block Replacement
Program Failure
Status Read after Program --> Block Replacement
Single Bit Failure
Verify ECC -> ECC Correction
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
Program Flow Chart
Start
Write 80h
Write Address
Write Data
Write 10h
Read Status Register
I/O 6 = 1 ?
or R/B = 1 ?
*
Program Error
No
Yes
No
I/O 0 = 0 ?
Yes
Program Completed
*
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
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MCP MEMORY
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60h
Write 00h
Write Block Address
Write Address
Write D0h
Read Data
Read Status Register
ECC Generation
I/O 6 = 1 ?
or R/B = 1 ?
*
Erase Error
No
Reclaim the Error
Verify ECC
Yes
Yes
No
No
Page Read Completed
I/O 0 = 0 ?
Yes
Erase Completed
*
: If erase operation results in an error, map out
the failing block and replace it with another block.
Block Replacement
Buffer
memory
error occurs
Page a
Block A
When the error happens with page "a" of Block "A", try
to write the data into another Block "B" from an external buffer. Then, prevent further system access to
Block "A" (by creating a "invalid block" table or other
appropriate scheme.)
Block B
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Pointer Operation
Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’
command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets
the pointer to ’C’ area(512~527byte). With these commands, the starting column address can be set to any of a whole
page(0~527byte). ’00h’ or ’50h’ is sustained until another address pointer command is inputted. ’01h’ command, however, is effective
only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ’01h’ command, the
address pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be inputted
before ’80h’ command is written. A complete read operation prior to ’80h’ command is not necessary. To program data starting from
’B’ area, ’01h’ command must be inputted right before ’80h’ command is written.
Table 2. Destination of the pointer
Command
Pointer position
Area
00h
01h
50h
0 ~ 255 byte
256 ~ 511 byte
512 ~ 527 byte
1st half array(A)
2nd half array(B)
spare array(C)
"A" area
(00h plane)
"B" area
(01h plane)
256 Byte
256 Byte
"A"
"B"
"C" area
(50h plane)
16 Byte
"C"
Internal
Page Register
Pointer select
commnad
(00h, 01h, 50h)
Pointer
Figure 5. Block Diagram of Pointer Operation
(1) Command input sequence for programming ’A’ area
The address pointer is set to ’A’ area(0~255), and sustained
Address / Data input
00h
80h
Address / Data input
10h
00h
’A’,’B’,’C’ area can be programmed.
It depends on how many data are inputted.
80h
10h
’00h’ command can be omitted.
(2) Command input sequence for programming ’B’ area
The address pointer is set to ’B’ area(256~511), and will be reset to
’A’ area after every program operation is executed.
Address / Data input
01h
80h
Address / Data input
10h
01h
80h
10h
’01h’ command must be rewritten before
every program operation
’B’, ’C’ area can be programmed.
It depends on how many data are inputted.
(3) Command input sequence for programming ’C’ area
The address pointer is set to ’C’ area(512~527), and sustained
Address / Data input
50h
80h
Address / Data input
10h
50h
Only ’C’ area can be programmed.
80h
10h
’50h’ command can be omitted.
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MCP MEMORY
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte page registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant savings in power consumption.
Figure 6. Program Operation with CE don’t-care.
CLE
CE don’t-care
WE
≈
≈
CE
ALE
I/OX
80h
Start Add.(4Cycle)
tCS
Data Input
tCH
Data Input
10h
tCEA
CE
CE
tREA
RE
tWP
WE
I/OX
out
Figure 7. Read Operation with CE don’t-care.
CLE
CE don’t-care
≈
CE
RE
ALE
tR
R/B
WE
I/OX
00h
Data Output(sequential)
Start Add.(4Cycle)
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MCP MEMORY
I/O
DATA
I/Ox
Data In/Out
I/O 0 ~ I/O 7
~528byte
Command Latch Cycle
CLE
tCLS
tCLH
tCS
tCH
CE
tWP
WE
tALS
tALH
ALE
tDH
tDS
Command
I/O0~7
Address Latch Cycle
tCLS
CLE
tWC
tCS
tWC
tWC
CE
tWP
tWP
tWP
tWP
WE
tWH
tALH tALS
tWH
tALH tALS
tALS
tWH
tALH tALS
tALH
ALE
tDS
I/O0~7
tDH
A0~A7
tDS
tDH
A9~A16
22
tDS
tDH
A17~A24
tDS
tDH
A25,,A26
Revision 0.1
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KBE00G003M-D411
MCP MEMORY
Input Data Latch Cycle
tCLH
CLE
tCH
CE
tWC
tALS
tWP
≈
ALE
tWP
tWP
WE
tWH
tDH
tDS
tDH
tDS
tDH
≈
tDS
I/O0~7
DIN 511
DIN 1
≈
DIN 0
Serial access Cycle after Read(CLE=L, WE=H, ALE=L)
tRC
≈
CE
tCHZ*
tREH
≈
tREA
tREA
tOH
tREA
RE
tRHZ*
tRHZ*
I/Ox
Dout
Dout
≈
tOH
Dout
≈
tRR
R/B
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
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MCP MEMORY
Status Read Cycle
tCLR
CLE
tCLS
tCLH
tCS
CE
tCH
tWP
WE
tCEA
tCHZ
tOH
tWHR
RE
tDH
tDS
I/OX
tRHZ
tREA
tIR
tOH
Status Output
70h
Read1 Operation(Read One Page)
CLE
CE
tCHZ
tWC
tOH
WE
tWB
tAR2
ALE
tR
tRHZ
tOH
tRC
≈
RE
I/O0~7
00h or 01h A0 ~ A7
A9 ~ A16
Column
Address
R/B
A17 ~ A24
Dout N
A25,A26
Page(Row)
Address
Dout N+1 Dout N+2
≈ ≈
tRR
Dout 527
Busy
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MCP MEMORY
Read1 Operation(Intercepted by CE)
CLE
CE
WE
tWB
tCHZ
tAR
ALE
tRC
tR
RE
tRR
I/O0~7
00h or 01h
A9 ~ A16
A0 ~ A7
A17 ~ A24
Dout N
A25,A26
Dout N+1
Dout N+2
Page(Row)
Address
Column
Address
Busy
R/B
Read2 Operation(Read One Page)
CLE
CE
WE
tR
tWB
tAR
ALE
≈
tRR
I/O0~7
50h
A0 ~ A7
A9 ~ A16 A17 ~ A24
Dout
511+M
A25,A26
R/B
≈
RE
Dout 527
Selected
Row
M Address
A0~A3 : Valid Address
A4~A7 : Don′t care
512
16
Start
address M
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MCP MEMORY
Page Program Operation
CLE
CE
tWC
tWC
≈
tWC
WE
tWB
tPROG
ALE
I/O0~7
80h
A0 ~ A7 A9 ~ A16 A17 ~ A24 A25,A26
Sequential Data Column
Input Command Address
Page(Row)
Address
≈ ≈
RE
Din
Din
10h
N
527
1 up to 528 Byte Data Program
Command
Serial Input
≈
R/B
70h
I/O0
Read Status
Command
I/O0=0 Successful Program
I/O0=1 Error in Program
BLOCK ERASE OPERATION (ERASE ONE BLOCK)
CLE
CE
tWC
WE
tBERS
tWB
ALE
RE
I/O0~7
60h
A9 ~ A16 A17 ~ A24 A25,A26
DOh
70h
I/O 0
Busy
R/B
Auto Block Erase Setup Command
Erase Command
26
≈
Page(Row)
Address
Read Status
Command
I/O0=0 Successful Erase
I/O0=1 Error in Erase
Revision 0.1
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R/B
I/O0~7
RE
ALE
WE
Sequential Data
Input Command
80h
tWC
27
Max. three times repeatable
Page(Row)
Address
Din
527
tDBSY :
typ. 1us
max. 10us
tDBSY
80h
I/O0~7
R/B
80h
A0 ~ A7 & A9 ~ A26
528 Byte Data
Address &
Data Input
11h
tDBSY
80h
A0 ~ A7 & A9 ~ A26
528 Byte Data
Address &
Data Input
11h
80h
Din
N
A0 ~ A7 & A9 ~ A26
528 Byte Data
Address &
Data Input
11h
tDBSY
Last Plane Input & Program
A0 ~ A7 A9 ~ A16 A17 ~ A24 A25,A26
tDBSY
Ex.) Four-Plane Page Program into Plane 0~3 or Plane 4~7
Column
Address
Din
N
≈
≈ ≈
11h
Program
1 up to 528 Byte Data Command
(Dummy)
Serial Input
A0 ~ A7 A9 ~ A16 A17 ~ A24 A25,A26
tWB
≈
CE
≈
≈ ≈
CLE
tPROG
A0 ~ A7 & A9 ~ A26
528 Byte Data
Address &
Data Input
10h
Program Confirm
Command
(True)
80h
Din
527
tWB
≈
Multi-Plane Page Program Operation
71h
tPROG
10h
I/O
71h
Read Multi-Plane
Status Command
KBE00G003M-D411
MCP MEMORY
Revision 0.1
July 2005
KBE00G003M-D411
MCP MEMORY
Multi-Plane Block Erase Operation into Plane 0~3 or Plane 4~7
CLE
CE
tWC
WE
tBERS
tWB
ALE
RE
60h
I/O0~7
A9 ~ A16 A17 ~ A24 A25,A26
DOh
71h
I/O 0
Busy
R/B
Block Erase Setup Command
≈
Page(Row)
Address
Erase Confirm Command
Read Multi-Plane
Status Command
Max. 4 times repeatable
* For Multi-Plane Erase operation, Block address to be erased should be repeated before "D0H" command.
Ex.) Four-Plane Block Erase Operation
R/B
I/O0~7
tBERS
60h
Address
60h
Address
60h
Address
60h
Address
D0h
71h
A9 ~ A26
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MCP MEMORY
Read ID Operation
CLE
CE
WE
ALE
RE
tREAD
I/O 0 ~ 7
90h
Read ID Command
00h
ECh
Address. 1cycle
Maker Code
79h
Device Code
A5h
C0h
Multi Plane Code
ID Defintition Table
90 ID : Access command = 90H
1st Byte
2nd Byte
3rd Byte
4th Byte
Value
Description
ECh
79h
A5h
C0h
Maker Code
Device Code
Must be don’t -cared
Supports Multi Plane Operation
(Must be don’t-cared for 1.8V device)
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MCP MEMORY
Copy-Back Program Operation
CLE
CE
tWC
WE
tWB
tWB tPROG
ALE
tR
RE
R/B
8Ah
A0~A7 A9~A16 A17~A24 A25,A26
Column
Address
A0~A7 A9~A16 A17~A24 A25,A26 10h
Column
Address
Page(Row)
Address
70h
I/O0
Read Status
Command
Page(Row)
Address
≈
00h
≈
I/O0~7
Busy
Busy
Copy-Back Data
Input Command
30
I/O0=0 Successful Program
I/O0=1 Error in Program
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MCP MEMORY
Device Operation
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command register along with four address cycles. Once the command is latched, it does not need to be written for the following page read operation. Three types of operations are available : random read, serial page read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred to the data registers in less than 15µs(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially
pulsing RE. High to low transitions of the RE clock output the data stating from the selected column address up to the last column
address.
The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of
bytes 512 to 527 may be selectively accessed by writing the Read2 command. Addresses A0 to A3 set the starting address of the
spare area while addresses A4 to A7 are ignored. Unless the operation is aborted, the page address is automatically incremented for
sequential row read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 command(00h/01h) is needed to move the pointer back to the main area. Figures 9 to 12 show typical sequence and timings for each
read operation.
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Figure 8. Read1 Operation
CLE
CE
WE
ALE
tR
R/B
RE
I/O0~7
00h
Data Output(Sequential)
Start Add.(4Cycle)
A0 ~ A7 & A9 ~ A26
(00h Command)
1st half array
(01h Command)*
2st half array
Data Field
Spare Field
1st half array
2st half array
Data Field
Spare Field
* After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half
array (00h) at next cycle.
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Figure 9. Read2 Operation
CLE
CE
WE
ALE
tR
R/B
RE
I/O0~7
50h
Data Output(Sequential)
Start Add.(4Cycle)
A0 ~ A3 & A9 ~ A26
Spare Field
(A4 ~ A7 :
Don′t Care)
1st half array
2nd half array
Data Field
Spare Field
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MCP MEMORY
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes
up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 1 for main array and 2 for spare array. The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded
into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell.
Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to the attached
technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address input and
then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state control automatically executes the algorithms and timings necessary for program and
verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command
may be entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle
by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are
valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 10).
The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in
Read Status command mode until another valid command is written to the command register.
Figure 10. Program & Read Status Operation
tPROG
R/B
I/O0~7
80h
Address & Data Input
10h
70h
A0 ~ A7 & A9 ~ A26
528 Byte Data
I/O0
Pass
Fail
BLOCK ERASE
The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in three cycles initiated by an Erase
Setup command(60h). Only address A14 to A26 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the
block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command
ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 11 details the sequence.
Figure 11. Block Erase Operation
tBERS
R/B
I/O0~7
60h
Address Input(3Cycle)
70h
D0h
I/O0
Pass
Block Add. : A14 ~ A26
Fail
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MCP MEMORY
Multi-Plane Page Program into Plane 0~3 or Plane 4~7
Multi-Plane Page Program is an extension of Page Program, which is executed for a single plane with 528 byte page registers. Since
the device is equipped with eight memory planes, activating the four sets of 528 byte page registers into plane 0~3 or plane 4~7
enables a simultaneous programming of four pages. Partial activation of four planes is also permitted.
After writing the first set of data up to 528 byte into the selected page register, Dummy Page Program command (11h) instead of
actual Page Program (10h) is inputted to finish data-loading of the current plane and move to the next plane. Since no programming
process is involved, R/B remains in Busy state for a short period of time(tDBSY). Read Status command (standard 70h or alternate
71h) may be issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). Then the next set
of data for one of the other planes is inputted with the same command and address sequences. After inputting data for the last plane,
actual True Page Program (10h) instead of dummy Page Program command (11h) must be followed to start the programming process. The operation of R/B and Read Status is the same as that of Page Program. Since maximum four pages into plane 0~3 or plane
4~7 are programmed simultaneously, pass/fail status is available for each page when the program operation completes. The
extended status bits (I/O1 through I/O 4) are checked by inputting the Read Multi-Plane Status Register. Status bit of I/O 0 is set to "1"
when any of the pages fails.
Multi-Plane page Program with "01h" pointer is not supported, thus prohibited.
Figure 12. Four-Plane Page Program
tDBSY
R/B
I/O0~7
80h
Address &
11h
Data Input
A0 ~ A7 & A9 ~ A26
528 Byte Data
80h
11h
Data
input
tDBSY
80h
Address &
11h
Data Input
A0 ~ A7 & A9 ~ A26
528 Byte Data
Address &
11h
Data Input
A0 ~ A7 & A9 ~ A26
528 Byte Data
80h
80h
80h
11h
tPROG
tDBSY
11h
Address &
10h
Data Input
A0 ~ A7 & A9 ~ A26
528 Byte Data
80h
80h
10h
Plane 3
(1024 Block)
Plane 0
(1024 Block)
Plane 1
(1024 Block)
Block 0
Block 1
Block 2
Block 3
Block 4
Block 5
Block 6
Block 7
Block 4088
Block 4092
Block 4089
Block 4093
Block 4090
Block 4094
Plane 2
(1024 Block)
35
71h
Block 4091
Block 4095
Revision 0.1
July 2005
KBE00G003M-D411
MCP MEMORY
Restirction in addressing with Multi Plane Page Program
While any block in each plane may be addressable for Multi-Plane Page Program, the four least significant addresses(A9-A13) for
the selected pages at one operation must be the same. Figure 13 shows an example where 2nd page of each addressed block is
selected for four planes. However, any arbitrary sequence is allowed in addressing multiple planes as shown in Figure17.
Figure 13. Multi-Plane Program & Read Status Operation
Block 0
Plane 3
(1024 Block)
Plane 2
(1024 Block)
Plane 1
(1024 Block)
Plane 0
(1024 Block)
Block 2
Block 1
Block 3
Page 0
Page 0
Page 0
Page 0
Page 1
Page 1
Page 1
Page 1
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Figure 14. Addressing Multiple Planes
80h
Plane 2
11h
80h
Plane 0
80h
11h
Plane3
80h
11h
Plane 1
10h
Figure 15. Multi-Plane Page Program & Read Status Operation
tPROG
R/B
Last Plane input
I/O0~7
80h
Address & Data Input
10h
Pass
I/O
71h
A0 ~ A7 & A9 ~ A26
528 Byte Data
Fail
Multi-Plane Block Erase into Plane 0~3 or Plane 4~7
Basic concept of Multi-Plane Block Erase operation is identical to that of Multi-Plane Page Program. Up to four blocks, one from each
plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command followed by three
address cycles) may be repeated up to four times for erasing up to four blocks. Only one block should be selected from each plane.
The Erase Confirm command initiates the actual erasing process. The completion is detected by analyzing R/B pin or Ready/Busy
status (I/O 6). Upon the erase completion, pass/fail status of each block is examined by reading extended pass/fail status(I/O 1
through I/O 4).
Figure 16. Four Block Erase Operation
R/B
I/O0~7
tBERS
60h
Address
(3 Cycle)
60h
Address
(3 Cycle)
60h
Address
(3 Cycle)
60h
Address
(3 Cycle)
D0h
71h
I/O
Pass
A0 ~ A7 & A9 ~ A26
Fail
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KBE00G003M-D411
MCP MEMORY
Copy-Back Program
The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the plane to another page within
the same plane without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are
removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of
the block also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a sequential
execution of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read operation with "00h" command and the address of the source page moves the whole 528byte data into the internal buffer. As soon as the
device returns to Ready state, Page-Copy Data-input command (8Ah) with the address cycles of destination page followed may be
written. The Program Confirm command (10h) is required to actually begin the programming operation. Copy-Back Program operation is allowed only within the same memory plane. Once the Copy-Back Program is finished, any additional partial page programming into the copied pages is prohibited before erase. A14, A15 and A26 must be the same between source and target page.
Figure20 shows the command sequence for single plane operation. "When there is a program-failure at Copy-Back operation,
error is reported by pass/fail status. But if the soure page has a bit error for charge loss, accumulated copy-back operations
could also accumulate bit errors. For this reason, two bit ECC is recommended for copy-back operation. "
Figure 17. One Page Copy-Back program Operation
tR
tPROG
R/B
I/O0~7
00h
Add.(4Cycles)
A0 ~ A7 & A9 ~ A26
Source Address
8Ah
Add.(4Cycles)
A0 ~ A7 & A9 ~ A26
Destination Address
37
10h
70h
I/O0
Pass
Fail
Revision 0.1
July 2005
KBE00G003M-D411
MCP MEMORY
Multi-Plane Copy-Back Program
Multi-Plane Copy-Back Program is an extension of one page Copy-Back Program into four plane operation. Since the device is
equipped with four memory planes, activating the four sets of 528 bytes page registers enables a simultaneous Multi-Plane CopyBack programming of four pages. Partial activation of four planes is also permitted.
First, normal read operation with the "00h"command and address of the source page moves the whole 528 byte data into internal
page buffers. Any further read operation for transferring the addressed pages to the corresponding page register must be executed
with "03h" command instead of "00h" command. Any plane may be selected without regard to "00h" or "03h". Up to four planes may
be addressed. Data moved into the internal page registers are loaded into the destination plane addresses. After the input of command sequences for reading the source pages, the same procedure as Multi-Plane Page programming except for a replacement
address command with "8Ah" is executed. Since no programming process is involved during data loading at the destination plane
address , R/B remains in Busy state for a short period of time(tDBSY). Read Status command (standard 70h or alternate 71h) may be
issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). After inputting data for the last
plane, actual True Page Program (10h) instead of dummy Page Program command (11h) must be followed to start the programming
process. The operation of R/B and Read Status is the same as that of Page Program. Since maximum four pages are programmed
simultaneously, pass/fail status is available for each page when the program operation completes. No pointer operation is supported
with Multi-Plane Copy-Back Program. Once the Multi-Plane Copy-Back Program is finished, any additional partial page programming into the copied pages is prohibited before erase once the Multi-Plane Copy-Back Program is finished.
Figure 18. Four-Plane Copy-Back Program
Max Three Times Repeatable
Source
Address
Input
00h
Plane 0
(1024 Block)
03h
03h
03h
Plane 3
(1024 Block)
Plane 2
(1024 Block)
Plane 1
(1024 Block)
Block 0
Block 4
Block 1
Block 5
Block 2
Block 3
Block 6
Block 7
Block 4088
Block 4092
Block 4089
Block 4093
Block 4090
Block 4094
Block 4091
Block 4095
Max Three Times Repeatable
8Ah
11h
8Ah
11h
8Ah
11h
8Ah
10h
Destination
Address
Input
Plane 3
(1024 Block)
Plane 0
(1024 Block)
Plane 1
(1024 Block)
Block 0
Block 1
Block 2
Block 3
Block 4
Block 5
Block 6
Block 7
Block 4088
Block 4092
Block 4089
Block 4093
Block 4090
Block 4094
38
Plane 2
(1024 Block)
Block 4091
Block 4095
Revision 0.1
July 2005
I/OX
R/B
00h
03h
tR
A0 ~ A7 & A9 ~ A25
Source Address
Add.( 4Cyc.)
03h
Add.( 4Cyc.)
tR
8Ah
tDBSY
≈
≈
A0 ~ A7 & A9 ~ A25
Source Address
≈
≈
Add.(4Cyc.)
11h
tDBSY
A0 ~ A7 & A9 ~ A25
Destination Address
8Ah
Add.(4Cyc.)
tPROG
10h
A0 ~ A7 & A9 ~ A25
Destination Address
8Ah
Max. 4 times (4 Cycle Destination Address Input) repeatable
tDBSY : Typical 1us, Max 10us
A0 ~ A7 & A9 ~ A25
Destination Address
Add.(4Cyc.) 11h
≈
≈
Max. 4 times ( 4 Cycle Source Address Input) repeatable
tR : Normal Read Busy
A0 ~ A7 & A9 ~ A25
Source Address
Add.(4Cyc.)
tR
Figure 19. Four-Plane Copy-Back Page Program (Continued)
71h
KBE00G003M-D411
MCP MEMORY
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MCP MEMORY
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00h or 50h) should be given before sequential page read cycle.
For Read Status of Multi Plane Program/Erase, the Read Multi-Plane Status command(71h) should be used to find out whether
multi-plane program or erase operation is completed, and whether the program or erase operation is completed successfully. The
pass/fail status data must be checked only in the Ready condition after the completion of Multi-Plane program or erase operation.
Table4. Read Staus Register Definition
I/O No.
Status
I/O 0
Total Pass/Fail
Definition by 70h Command
I/O 1
Plane 0 Pass/Fail
Must be don’t -cared
(2)
Pass : "0"
Fail : "1"
I/O 2
Plane 1 Pass/Fail
Must be don’t -cared
Pass : "0"(2)
Fail : "1"
I/O 3
Plane 2 Pass/Fail
Must be don’t -cared
Pass : "0"(2)
Fail : "1"
I/O 4
Plane 3 Pass/Fail
Must be don’t -cared
Pass : "0"(2)
Fail : "1"
I/O 5
Reserved
Must be don’t -cared
Must be don’t-cared
I/O 6
Device Operation
I/O 7
Write Protect
Pass : "0"
Fail : "1"
Busy : "0"
Protected : "0"
Ready : "1"
Not Protected : "1"
Definition by 71h Command
Pass : "0"(1)
Busy : "0"
Protected : "0"
Fail : "1"
Ready : "1"
Not Protected : "1"
NOTE : 1. I/O 0 describes combined Pass/Fail condition for all planes. If any of the selected multiple pages/blocks fails in Program/
Erase operation, it sets "Fail" flag.
2. The pass/fail status applies only to the corresponding plane.
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Revision 0.1
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KBE00G003M-D411
MCP MEMORY
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Four read cycles sequentially output the manufacture code(ECh), and the device code*, Reserved(A5h), Multi plane operation
code(C0h) respectively. A5h must be don’t-cared. C0h means that device supports Multi Plane operation but must be don’t-cared for
1.8V device. The command register remains in Read ID mode until further commands are issued to it. Figure 20 shows the operation
sequence.
Figure 20. Read ID Operation 1
CLE
tCEA
CE
WE
tAR
ALE
RE
I/O0~7
tWHR
90h
tREA
00h
ECh
79h
Address. 1cycle
Maker code
Device code
41
A5h
C0h
Multi-Plane code
Revision 0.1
July 2005
KBE00G003M-D411
MCP MEMORY
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 5 for device status after reset operation. If the device is
already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST
after the Reset command is written. Refer to Figure 21 below.
Figure 21. RESET Operation
tRST
R/B
I/O0~7
FFh
Table5. Device Status
Operation Mode
After Power-up
After Reset
Read 1
Waiting for next command
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KBE00G003M-D411
MCP MEMORY
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is
an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and
current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 25). Its value can be
determined by the following guidance.
Rp
ibusy
VCC
0.4V, VOH : VccQ-0.4V
Ready Vcc
R/B
open drain output
VOH
CL
VOL
Busy
tf
tr
GND
Device
Figure 22. Rp vs tr ,tf & Rp vs ibusy
300n
3m
2.3
Ibusy
200n
100n
2m
1.1
30
tr
2.3 tf
2.3
1K
2K
120
90
60
0.75
2.3
Ibusy [A]
tr,tf [s]
@ Vcc = 2.7V, Ta = 25°C , CL = 30pF
1m
2.3
0.55
4K
3K
Rp(ohm)
Rp value guidance
Rp(min, 2.7V part) =
2.5V
VCC(Max.) - VOL(Max.)
IOL + ΣIL
=
3mA + ΣIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr
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Revision 0.1
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KBE00G003M-D411
MCP MEMORY
Data Protection & Power up sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 1.8V. WP pin provides hardware protection and is recommended to be kept at
VIL during power-up and power-down and recovery time of minimum 10µs is required before internal circuit gets ready for any command sequences as shown in Figure 23. The two step command sequence for program/erase provides additional software protection.
≈
Figure 23. AC Waveforms for Power Transition
~ 2.0V
~ 2.0V
VCC
≈
High
≈
WP
WE
≈
10µs
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Revision 0.1
July 2005
KBE00G003M-D411
MCP MEMORY
512Mb(32Mb x 16)
Mobile SDRAM DDP F-Die
45
Revision 0.1
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KBE00G003M-D411
MCP MEMORY
FUNCTIONAL BLOCK DIAGRAM
I/O Control
Data Input Register
LWE
LDQM
Bank Select
8M x 16
8M x 16
Output Buffer
Sense AMP
Row Decoder
Row Buffer
Refresh Counter
ADD
Address Register
CLK
8M x 16
DQi
8M x 16
Col. Buffer
LCBR
LRAS
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LRAS
LCBR
LWE
LCAS
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
46
L(U)DQM
Revision 0.1
July 2005
KBE00G003M-D411
MCP MEMORY
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, VOUT
-1.0 ~ 2.6
V
Voltage on VDD supply relative to Vss
VDD, VDDQ
-1.0 ~ 2.6
V
TSTG
-55 ~ +150
°C
Power dissipation
PD
1.0
W
Short circuit current
IOS
50
mA
Storage temperature
NOTES:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C)
Parameter
Symbol
Min
Typ
Max
Unit
VDD
1.7
1.8
1.95
V
VDDQ
1.7
1.8
1.95
V
VIH
0.8 x VDDQ
1.8
VDDQ + 0.3
V
Note
Supply voltage
Input logic high voltage
1
Input logic low voltage
VIL
-0.3
0
0.3
V
2
Output logic high voltage
VOH
VDDQ -0.2
-
-
V
IOH = -0.1mA
Output logic low voltage
VOL
-
-
0.2
V
IOL = 0.1mA
ILI
-2
-
2
uA
3
Input leakage current
NOTES :
1. VIH (max) = 2.2V AC.The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -1.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
4. Dout is disabled, 0V ≤ VOUT ≤ VDDQ.
CAPACITANCE (VDD = 1.8V, TA = 23°C, f = 1MHz, VREF =0.9V ± 50 mV)
Pin
Symbol
Min
Max
Unit
CCLK
2.5
6
pF
RAS, CAS, WE, CS, CKE
CIN
2.5
6
pF
DQM
CIN
1.5
3
pF
Address
CADD
2.5
6
pF
DQ0 ~ DQ15
COUT
3
5
pF
Clock
47
Note
Revision 0.1
July 2005
KBE00G003M-D411
MCP MEMORY
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C)
Parameter
Operating Current
(One Bank Active)
Precharge Standby Current in
power-down mode
Symbol
ICC1
ICC2P
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
KBE00G003M-D411
Unit
Note
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
80
mA
1
CKE ≤ VIL(max), tCC = 10ns
0.6
mA
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞
ICC2N
Precharge Standby Current
in non power-down mode
Test Condition
0.6
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
20
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
ICC2NS
Input signals are stable
ICC3P
2
CKE ≤ VIL(max), tCC = 10ns
10
mA
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞
ICC3N
ICC3NS
2
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
40
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
10
mA
Operating Current
(Burst Mode)
ICC4
IO = 0 mA
Page burst
4Banks Activated
tCCD = 2CLKs
120
mA
Refresh Current
ICC5
tARFC ≥ tARFC(min)
130
mA
Self Refresh Current
ICC6
CKE ≤ 0.2V
TCSR Range
Max 40
Max 85
Full Array
300
800
1/2 of Full Array
240
600
1/4 of Full Array
200
500
1
°C
uA
NOTES:
1. Measured with outputs open.
2. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
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KBE00G003M-D411
MCP MEMORY
AC OPERATING TEST CONDITIONS(VDD = 1.7V ∼ 1.95V, TA =
Parameter
AC input levels (Vih/Vil)
-25 to 85°C)
Value
Unit
0.9 x VDDQ / 0.2
V
0.5 x VDDQ
V
tr/tf = 1/1
ns
0.5 x VDDQ
V
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
See Figure 2
1.8V
13.9KΩ
Vtt=0.5 x VDDQ
VOH (DC) = VDDQ - 0.2V, IOH = -0.1mA
Output
VOL (DC) = 0.2V, IOL = 0.1mA
10.6KΩ
50Ω
30pF
Output
Z0=50Ω
30pF
Figure 1. DC Output Load Circuit
Figure 2. AC Output Load Circuit
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Revision 0.1
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KBE00G003M-D411
MCP MEMORY
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
KBE00G003M-D411
Unit
Note
Row active to row active delay
tRRD(min)
18
ns
1
RAS to CAS delay
tRCD(min)
27
ns
1
Row precharge time
tRP(min)
27
ns
1
tRAS(min)
50
ns
1
tRAS(max)
100
us
Row cycle time
tRC(min)
77
ns
1
Last data in to row precharge
tRDL(min)
15
ns
2
Last data in to Active delay
tDAL(min)
tRDL + tRP
-
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Auto refresh cycle time
tARFC(min)
80
ns
Exit self refresh to active command
tSRFX(min)
120
ns
Col. address to col. address delay
tCCD(min)
1
CLK
3
2
ea
4
Row active time
Number of valid output data
CAS latency=3
NOTES:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next
higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
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KBE00G003M-D411
MCP MEMORY
AC CHARACTERISTICS(AC operating conditions unless otherwise noted)
KBE00F003M-D411
Parameter
Symbol
CLK cycle time
CAS latency=3
tCC
CLK to valid output delay
CAS latency=3
tSAC
Output data hold time
CAS latency=3
Unit
Note
1000
ns
1
7
ns
1,2
Min
Max
9
tOH
2.0
ns
2
CLK high pulse width
tCH
3.0
ns
3
CLK low pulse width
tCL
3.0
ns
3
Input setup time
tSS
2.0
ns
3
Input hold time
tSH
1.5
ns
3
CLK to output in Low-Z
tSLZ
1
ns
2
CLK to output in Hi-Z
CAS latency=3
tSHZ
7
ns
NOTES :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
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KBE00G003M-D411
MCP MEMORY
SIMPLIFIED TRUTH TABLE
COMMAND
Register
CKEn-1 CKEn
Mode Register Set
H
Auto Refresh
X
Self
Refresh
RAS
CAS
WE
L
L
L
L
X
OP CODE
L
L
L
H
X
X
Exit
3
L
L
3
L
H
H
H
H
X
X
X
H
3
X
X
3
Bank Active & Row Addr.
H
X
L
L
H
H
X
V
Read &
Auto Precharge Disable
Column Address
Auto Precharge Enable
H
X
L
H
L
H
X
V
Write &
Auto Precharge Disable
Column Address
Auto Precharge Enable
H
X
L
H
L
L
X
V
Burst Stop
H
X
L
H
H
L
X
H
X
L
L
H
L
X
H
Exit
L
H
Entry
H
L
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
H
X
V
L
X
H
4
4, 5
4
4, 5
6
X
X
X
X
X
X
Exit
No Operation Command
H
L
Precharge Power Down
Mode
DQM
Column
Address
(A0~A9)
Column
Address
(A0~A9)
H
L
All Banks
Entry
Row Address
L
Bank Selection
Precharge
Clock Suspend or
Active Power Down
1, 2
H
H
Entry
Refresh
DQM BA0,1 A10/AP
A12,A11,
Note
A9 ~ A0
CS
L
H
X
H
H
X
H
X
X
X
L
H
H
H
X
V
X
X
X
7
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
NOTES :
1. OP Code : Operand Code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are the same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
Partial self refresh can be issued only after setting partial self refresh mode of EMRS.
4. BA0 ~ BA1 : Bank select addresses.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency
is 0), but in read operation, it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).
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A. MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with Normal MRS
Address
Function
BA0 ~ BA1
A12 ~ A10/AP
A9*2
"0" Setting for
Normal MRS
RFU*1
W.B.L
A8
A7
A6
Test Mode
A5
A4
A3
CAS Latency
A2
BT
A1
A0
Burst Length
Normal MRS Mode
Test Mode
CAS Latency
Burst Type
Burst Length
A8
A7
Type
A6
A5
A4
Latency
A3
Type
A2
A1
A0
BT=0
BT=1
0
0
Mode Register Set
0
0
0
Reserved
0
Sequential
0
0
0
1
1
0
1
Reserved
0
0
1
1
1
Interleave
0
0
1
2
2
1
0
Reserved
0
1
0
2
0
1
0
4
4
1
Reserved
0
1
1
3
0
1
1
8
8
Write Burst Length
1
0
0
Reserved
1
0
0
Reserved
Reserved
1
0
1
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full Page
Reserved
1
A9
Length
Mode Select
BA1 BA0
0
0
Burst
1
1
0
Reserved
1
Single Bit
1
1
1
Reserved
Mode
Setting
for Normal MRS
0
Full Page Length x16 : 512Mb(1024)
Register Programmed with Extended MRS
Address
BA1
Function
BA0
A12 ~ A10/AP
Mode Select
A9
A8
A7
A6
A5
A4
DS
RFU*1
A3
A2
A1
A0
PASR
RFU*1
EMRS for PASR(Partial Array Self Ref.) & DS(Driver Strength)
Mode Select
Driver Strength
PASR
BA1
BA0
Mode
A6
A5
Driver Strength
A2
A1
A0
Size of Refreshed Area
0
0
Normal MRS
0
0
Full
0
0
0
Full Array
0
1
Reserved
0
1
1/2
0
0
1
1/2 of Full Array
1
0
EMRS for Mobile SDRAM
1
0
1/4
0
1
0
1/4 of Full Array
1
1
Reserved
1
1
1/8
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Reserved Address
A12~A10/AP
A9
A8
A7
A4
A3
0
0
0
0
0
0
NOTES:
1.RFU(Reserved for future use) should stay "0" during MRS cycle.
2.If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
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Partial Array Self Refresh
1. In order to save power consumption, Mobile SDRAM has PASR option.
2. Mobile SDRAM supports 3 kinds of PASR in self refresh mode : Full Array, 1/2 of Full Array, 1/4 of Full Array
BA1=0
BA0=0
BA1=0
BA0=1
BA1=0
BA0=0
BA1=0
BA0=1
BA1=0
BA0=0
BA1=0
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
- Full Array
- 1/2 Array
- 1/4 Array
Partial Self Refresh Area
Internal Temperature Compensated Self Refresh (TCSR)
Note :
1. In order to save power consumption, Mobile-SDRAM includes the internal temperature sensor and control units to control the
self refresh cycle automatically according to the two temperature range ; Max. 40 °C, Max. 85 °C.
2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.
Self Refresh Current (Icc 6)
Temperature Range
Unit
Full Array
1/2 of Full Array
1/4 of Full Array
Max. 40 °C
300
240
200
Max. 85 °C
800
600
500
uA
B. POWER UP SEQUENCE
1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.
- Apply VDD before or at the same time as VDDQ.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS.
EMRS cycle is not mandatory and the EMRS command needs to be issued only when DS or PASR is used.
The default state without EMRS command issued is the half driver strength and full array refreshed.
The device is now ready for the operation selected by EMRS.
For operating with DS or PASR , set DS or PASR mode in EMRS setting stage.
In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not
needed again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set.
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C. BURST SEQUENCE
1. BURST LENGTH = 4
Initial Address
Sequential
Interleave
A1
A0
0
0
0
1
2
3
0
1
2
3
0
1
1
2
3
0
1
0
3
2
1
0
2
3
0
1
2
3
0
1
1
1
3
0
1
2
3
2
1
0
2. BURST LENGTH = 8
Initial Address
Sequential
Interleave
A2
A1
A0
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
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D. DEVICE OPERATIONS
ADDRESSES of 256Mb
ADDRESSES of 512Mb
BANK ADDRESSES (BA0 ~ BA1)
BANK ADDRESSES (BA0 ~ BA1)
: In case x 16
: In case x 16
This SDRAM is organized as four independent banks of
4,194,304 words x 16 bits memory arrays. The BA0 ~ BA1 inputs
This SDRAM is organized as four independent banks of
8,388,608 words x 16 bits memory arrays. The BA0 ~ BA1 inputs
are latched at the time of assertion of RAS and CAS to select the
bank to be used for the operation. The bank addresses BA0 ~
are latched at the time of assertion of RAS and CAS to select the
bank to be used for the operation. The bank addresses BA0 ~
BA1 are latched at bank active, read, write, mode register set
and precharge operations.
BA1 are latched at bank active, read, write, mode register set
and precharge operations.
: In case x 32
: In case x 32
This SDRAM is organized as four independent banks of
2,097,152 words x 32 bits memory arrays. The BA0 ~ BA1 inputs
are latched at the time of assertion of RAS and CAS to select the
bank to be used for the operation. The bank addresses BA0 ~
BA1 are latched at bank active, read, write, mode register set
and precharge operations.
This SDRAM is organized as four independent banks of
ADDRESS INPUTS (A0 ~ A12)
ADDRESS INPUTS (A0 ~ A12)
: In case x 16
: In case x 16
The 22 address bits are required to decode the 4,194,304 word
locations are multiplexed into 13 address input pins (A0 ~ A12).
The 13 bit row addresses are latched along with RAS and BA0 ~
BA1 during bank activate command. The 9 bit column addresses
are latched along with CAS, WE and BA0 ~ BA1 during read or
write command.
The 23 address bits are required to decode the 8,388,608 word
locations are multiplexed into 13 address input pins (A0 ~ A12).
The 13 bit row addresses are latched along with RAS and BA0 ~
BA1 during bank activate command. The 10 bit column
addresses are latched along with CAS, WE and BA0 ~ BA1 during read or write command.
: In case x 32
: In case x 32
The 21 address bits are required to decode the 2,097,152 word
locations are multiplexed into 12 address input pins (A0 ~ A11).
The 12 bit row addresses are latched along with RAS and BA0 ~
BA1 during bank activate command. The 9 bit column addresses
The 22 address bits are required to decode the 8,388,608 word
locations are multiplexed into 13 address input pins (A0 ~ A12).
The 13 bit row addresses are latched along with RAS and BA0 ~
BA1 during bank activate command. The 9 bit column addresses
are latched along with CAS, WE and BA0 ~ BA1 during read or
write command.
are latched along with CAS, WE and BA0 ~ BA1 during read or
write command.
56
4,194,304 words x 32 bits memory arrays. The BA0 ~ BA1 inputs
are latched at the time of assertion of RAS and CAS to select the
bank to be used for the operation. The bank addresses BA0 ~
BA1 are latched at bank active, read, write, mode register set
and precharge operations.
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D. DEVICE OPERATIONS (continued)
CLOCK (CLK)
DQM OPERATION
The clock input is used as the reference for all SDRAM operations. All operations are synchronized to the positive going edge
The DQM is used to mask input and output operations. It works
similar to OE during read operation and inhibits writing during
write operation. The read latency is two cycles from DQM and
of the clock. The clock transitions must be monotonic between
VIL and VIH. During operation with CKE high all inputs are
assumed to be in a valid state (low or high) for the duration of
set-up and hold time around positive edge of the clock in order to
function well Q perform and ICC specifications.
CLOCK ENABLE (CKE)
The clock enable(CKE) gates the clock onto SDRAM. If CKE
goes low synchronously with clock (set-up and hold time are the
same as other inputs), the internal clock is suspended from the
next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored
from the next clock cycle after CKE goes low. When all banks are
in the idle state and CKE goes low synchronously with clock, the
SDRAM enters the power down mode from the next clock cycle.
The SDRAM remains in the power down mode ignoring the other
inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes
high at least "1CLK + tSS" before the high going edge of the
clock, then the SDRAM becomes active from the same clock
edge accepting all the input commands.
NOP and DEVICE DESELECT
When RAS, CAS and WE are high, the SDRAM performs no
operation (NOP). NOP does not initiate any new operation, but is
needed to complete operations which require more than single
clock cycle like bank activate, burst read, auto refresh, etc. The
device deselect is also a NOP and is entered by asserting CS
high. CS high disables the command decoder so that RAS, CAS,
WE and all the address inputs are ignored.
zero cycle for write, which means DQM masking occurs two
cycles later in read cycle and occurs in the same cycle during
write cycle. DQM operation is synchronous with the clock. The
DQM signal is important during burst interruptions of write with
read or precharge in the SDRAM. Due to asynchronous nature of
the internal write, the DQM operation is critical to avoid unwanted
or incomplete writes when the complete burst write is not
required. Please refer to DQM timing diagram also.
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the various
operating modes of SDRAM. It programs the CAS latency, burst
type, burst length, test mode and various vendor specific options
to make SDRAM useful for variety of different applications. The
default value of the mode register is not defined, therefore the
mode register must be written after power up to operate the
SDRAM. The mode register is written by asserting low on CS,
RAS, CAS and WE (The SDRAM should be in active mode with
CKE already high prior to writing the mode register). The state of
address pins A0 ~ An and BA0 ~ BA1 in the same cycle as CS,
RAS, CAS and WE going low is the data written in the mode register. Two clock cycles is required to complete the write in the
mode register. The mode register contents can be changed using
the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register
is divided into various fields depending on the fields of functions.
The burst length field uses A0 ~ A2, burst type uses A3, CAS
latency (read latency from column address) use A4 ~ A6, vendor
specific options or test mode use A7 ~ A8, A10/AP ~ An and BA0
~ BA1. The write burst length is programmed using A9. A7 ~ A8,
A10/AP ~ An and BA0 ~ BA1 must be set to low for normal
SDRAM operation. Refer to the table for specific codes for various burst length, burst type and CAS latencies.
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D. DEVICE OPERATIONS (continued)
EXTENDED MODE REGISTER SET (EMRS)
The SDRAM has four internal banks in the same chip and shares
The extended mode register stores the data for selecting driver
strength and partial self refresh. EMRS cycle is not mandatory
and the EMRS command needs to be issued only when DS or
PASR is used. The default state without EMRS command issued
is the half driver strength, and full array refreshed.
The
extended mode register is written by asserting low on CS, RAS,
CAS, WE and high on BA1 ,low on BA0(The SDRAM should be
in all bank precharge with CKE already high prior to writing into
the extended mode register). The state of address pins A0 ~ A12
in the same cycle as CS, RAS, CAS and WE going low is written
in the extended mode register. Two clock cycles are required to
complete the write operation in the extended mode register. The
mode register contents can be changed using the same command and clock cycle requirements during operation as long as
all banks are in the idle state. A0 - A2 are used for partial self
refresh , A5 - A6 are used for Driver strength, "Low" on BA0 and
"High" on BA1 are used for EMRS. All the other address pins
except A0-A2, A5-A6, and BA1, BA0 must be set to low for
proper EMRS operation. Refer to the table for specific codes.
BANK ACTIVATE.
The bank activate command is used to select a random row in an
idle bank. By asserting low on RAS and CS with desired row and
bank address, a row access is initiated. The read or write operation can occur after a time delay of tRCD(min) from the time of
bank activation. tRCD is an internal timing parameter of SDRAM,
therefore it is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate and
read or write command should be calculated by dividing
tRCD(min) with cycle time of the clock and then rounding off the
result to the next higher integer.
part of the internal circuitry to reduce chip area, therefore it
restricts the activation of four banks simultaneously. Also the
noise generated during sensing of each bank of SDRAM is high,
requiring some time for power supplies to recover before another
bank can be sensed reliably. tRRD(min) specifies the minimum
time required between activating different bank. The number of
clock cycles required between different bank activation must be
calculated similar to tRCD specification. The minimum time
required for the bank to be active to initiate sensing and restoring
the complete row of dynamic cells is determined by tRAS(min).
Every SDRAM bank activate command must satisfy tRAS(min)
specification before a precharge command to that active bank
can be asserted. The maximum time any bank can be in the
active state is determined by tRAS(max). The number of cycles for
both tRAS(min) and tRAS(max) can be calculated similar to tRCD
specification.
BURST READ
The burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The
burst read command is issued by asserting low on CS and CAS
with WE being high on the positive edge of the clock. The bank
must be active for at least tRCD(min) before the burst read command is issued. The first output appears in CAS latency number
of clock cycles after the issue of burst read command. The burst
length, burst sequence and latency from the burst read command
is determined by the mode register which is already programmed. The burst read can be initiated on any column address
of the active row. The address wraps around if the initial address
does not start from a boundary such that number of outputs from
each I/O are equal to the burst length programmed in the mode
register. The output goes into high-impedance at the end of the
burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another
burst read or burst write in the same bank or the other active
bank or a precharge command to the same bank. The burst stop
command is valid at every page burst length.
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D. DEVICE OPERATIONS (continued)
BURST WRITE
AUTO PRECHARGE
The burst write command is similar to burst read command and
is used to write data into the SDRAM on consecutive clock cycles
in adjacent addresses depending on burst length and burst
sequence. By asserting low on CS, CAS and WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst
write command. The input buffer is deselected at the end of the
burst length, even though the internal writing can be completed
yet. The writing can be completed by issuing a burst read and
DQM for blocking data inputs or burst write in the same or
another active bank. The burst stop command is valid at every
burst length. The write burst can also be terminated by using
DQM for blocking data and procreating the bank tRDL after the
last data input to be written into the active row. See DQM OPERATION also.
The precharge operation can also be performed by using auto
precharge. The SDRAM internally generates the timing to satisfy
tRAS(min) and "tRP" for the programmed burst length and CAS
latency. The auto precharge command is issued at the same time
as burst read or burst write by asserting high on A10/AP. If burst
read or burst write by asserting high on A10/AP, the bank is left
active until a new command is asserted. Once auto precharge
command is given, no new commands are possible to that particular bank until the bank achieves idle state.
ALL BANKS PRECHARGE
All banks can be precharged at the same time by using Precharge all command. Asserting low on CS, RAS, and WE with
high on A10/AP after all banks have satisfied tRAS(min) requirement, performs precharge on all banks. At the end of tRP after
performing precharge to all the banks, all banks are in idle state.
PRECHARGE
The precharge operation is performed on an active bank by
asserting low on CS, RAS, WE and A10/AP with valid BA0 ~ BA1
of the bank to be precharged. The precharge command can be
asserted anytime after tRAS(min) is satisfied from the bank active
command in the desired bank. tRP is defined as the minimum
number of clock cycles required to complete row precharge is
calculated by dividing tRP with clock cycle time and rounding up
to the next higher integer. Care should be taken to make sure
that burst write is completed or DQM is used to inhibit writing
before precharge command is asserted. The maximum time any
bank can be active is specified by tRAS(max). Therefore, each
bank activate command. At the end of precharge, the bank
enters the idle state and is ready to be activated again. Entry to
Power down, Auto refresh, Self refresh and Mode register set
etc. is possible only when all banks are in idle state.
59
AUTO REFRESH
The storage cells of 64Mb, 128Mb, 256Mb and 512Mb SDRAM
need to be refreshed every 64ms to maintain data. An auto
refresh cycle accomplishes refresh of a single row of storage
cells. The internal counter increments automatically on every
auto refresh cycle to refresh all the rows. An auto refresh command is issued by asserting low on CS, RAS and CAS with high
on CKE and WE. The auto refresh command can only be
asserted with all banks being in idle state and the device is not in
power down mode (CKE is high in the previous cycle). The time
required to complete the auto refresh operation is specified by
tARFC(min). The minimum number of clock cycles required can be
calculated by driving tARFC with clock cycle time and them rounding up to the next higher integer. The auto refresh command
must be followed by NOP's until the auto refresh operation is
completed. All banks will be in the idle state at the end of auto
refresh operation. The auto refresh is the preferred refresh mode
when the SDRAM is being used for normal data transactions.
The 64Mb and 128Mb SDRAM’s auto refresh cycle can be performed once in 15.6us or a burst of 4096 auto refresh cycles
once in 64ms. The 256Mb and 512Mb SDRAM’s auto refresh
cycle can be performed once in 7.8us or a burst of 8192 auto
refresh cycles once in 64ms.
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D. DEVICE OPERATIONS(continued)
SELF REFRESH
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for data
retention and low power operation of SDRAM. In self refresh
mode, the SDRAM disables the internal clock and all the input
buffers except CKE. The refresh addressing and timing are internally generated to reduce power consumption.
The self refresh mode is entered from all banks idle state by
asserting low on CS, RAS, CAS and CKE with high on WE. Once
the self refresh mode is entered, only CKE state being low matters, all the other inputs including the clock are ignored in order to
remain in the self refresh mode.
The self refresh is exited by restarting the external clock and then
asserting high on CKE. This must be followed by NOP's for a
minimum time of tSRFX before the SDRAM reaches idle state to
begin normal operation. In case that the system uses burst auto
refresh during normal operation, it is recommended to use burst
8192 auto refresh cycles for 256Mb and 512Mb, and burst 4096
auto refresh cycles for 128Mb and 64Mb immediately before
entering self refresh mode and after exiting in self refresh mode.
On the other hand, if the system uses the distributed auto
refresh, the system only has to keep the refresh duty cycle.
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E. BASIC FEATURE AND FUNCTION DESCRIPTIONS
1. CLOCK Suspend
2) Clock Suspended During Read (BL=4)
1) Clock Suspended During Write
CLK
CLK
CMD
CMD
WR
RD
CKE
CKE
Masked by CKE
Masked by CKE
Internal
CLK
Internal
CLK
DQ(CL2)
D0
D1
D2
D3
DQ(CL2)
DQ(CL3)
D0
D1
D2
D3
DQ(CL3)
Q0
Not Written
D
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Suspended Dout
2. DQM Operation
1) Write Mask (BL=4)
2) Read Mask (BL=4)
CLK
CLK
CMD
CMD
WR
DQM
RD
DQM
Masked by CKE
DQ(CL2)
D0
DQ(CL3)
D0
D1
DQ(CL2)
D3
D1
Q0
Hi-Z
DQ(CL3)
D3
Masked by CKE
Hi-Z
DQM to Data-in Mask = 0
Q2
Q3
Q1
Q2
Q3
DQM to Data-out Mask = 2
3) DQM with Clock Suspended (Full Page Read) *2
CLK
CMD
RD
CKE
DQM
DQ(CL2)
DQ(CL3)
Q0
Hi-Z
Hi-Z
Q2
Q1
Hi-Z
Hi-Z
Q4
Q3
Hi-Z
Hi-Z
Q6
Q7
Q8
Q5
Q6
Q7
*NOTE :
1. CKE to CLK disable/enable = 1CLK.
2. DQM makes data out Hi-Z after 2CLKs which should masked by CKE " L"
3. DQM masks both data-in and data-out.
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3. CAS Interrupt (I)
1) Read interrupted by Read (BL=4) *1
CLK
CMD
RD
RD
ADD
A
B
QA0 QB0 QB1 QB1 QB3
DQ(CL2)
QA0 QB0 QB1 QB1 QB3
DQ(CL3)
tCCD *2
2) Write interrupted by Write (BL=2)
3) Write interrupted by Read (BL=2)
CLK
CLK
CMD
WR WR
CMD
WR
ADD
A
tCCD *2
tCCD *2
ADD
DQ
A
RD
B
DA0 DB0 DB1
tCDL *3
B
DQ(CL2)
DA0
DQ(CL3)
DA0
QB0 QB1
QB0 QB1
tCDL *3
*NOTE:
1. By " Interrupt", It is meant to stop burst read/write by external command before the end of burst.
By "CAS Interrupt", to stop burst read/write by CAS access ; read and write.
2. tCCD : CAS to CAS delay. (=1CLK)
3. tCDL : Last data in to new column address delay. (=1CLK)
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MCP MEMORY
4. CAS Interrupt (II) : Read Interrupted by Write & DQM
(a) CL=2, BL=4
CLK
i) CMD
RD
WR
DQM
DQ
ii) CMD
D0
RD
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
WR
DQM
Hi-Z
DQ
iii) CMD
D0
RD
WR
DQM
Hi-Z
DQ
iv) CMD
D0
RD
WR
DQM
Q0
DQ
Hi-Z
*1
D0
D3
(b) CL=3, BL=4
CLK
i) CMD
RD
WR
DQM
D0
DQ
ii) CMD
RD
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
WR
DQM
DQ
iii) CMD
D0
RD
WR
DQM
DQ
iv) CMD
D0
RD
WR
DQM
Hi-Z
DQ
v) CMD
D0
RD
WR
DQM
DQ
Q0
Hi-Z
*1
D0
D3
*NOTE:
1. To prevent bus contention, there should be at least one gap between data in and data out.
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5. Write Interrupted by Precharge & DQM
1) tRDL = 2CLK
CLK
CMD
WR
PRE
*2
DQM
DQ
*3
D0
D1
D2
Masked by DQM
*NOTE:
1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
2. To inhibit invalid write, DQM should be issued.
3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of four banks operation.
6. Precharge
1) Normal Write
BL=4 & tRDL=2CLK
CLK
CMD
WR
DQ
D0
PRE
D1
D2
D3
tRDL*1
2) Normal Read (BL=4)
CLK
*2
RD
CMD
PRE
Q0
DQ(CL2)
DQ(CL3)
Q1
Q2
Q3
Q0
Q1
Q2
1
Q3
2
7. Auto Precharge
1) Normal Write (BL=4)
2) Normal Read (BL=4)
CLK
CLK
CMD
WR
DQ
D0
ACT
D1
D2
CMD
DQ(CL2)
D3
DQ(CL3)
tRDL =2CLK
RD
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
tDAL =tRDL + tRP*4
Auto Precharge Starts *3
Auto Precharge Starts@tRDL=2CLK *3
*NOTE:
1. SAMSUNG can support tRDL=2CLK .
2. Number of valid output data after row precharge : 1, 2 for CAS Latency = 2, 3 respectively.
3. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same bank is illegal
4. tDAL defined Last data in to Active delay. SAMSUNG can support tDAL=tRDL+ tRP .
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8. Burst Stop & Interrupted by Precharge
1) Normal Write
BL=4 & tRDL=2CLK
CLK
CMD
WR
PRE
DQM
DQ
D1
D0
D2
tRDL*1
2) Write Burst Stop (BL=8)
3) Read Interrupted by Precharge (BL=4)
CLK
CMD
CLK
WR
STOP
CMD
DQ(CL2)
DQM
DQ
RD
D0
D1
D2
D3
DQ(CL3)
PRE
Q0
Q1
Q0
1
Q1
2
tBDL *2
4) Read Burst Stop (BL=4)
CLK
CMD
RD
STOP
Q0
DQ(CL2)
Q1
Q0
DQ(CL3)
1
Q1
2
9. MRS
1) Mode Register Set
CLK
*4
CMD
PRE
MRS
tRP
ACT
2CLK
*NOTE:
1. SAMSUNG can support tRDL=2CLK.
2. tBDL : 1 CLK ; Last data in to burst stop delay.
Read or write burst stop command is valid at every burst length.
3. Number of valid output data after row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectively.
4. PRE : All banks precharge is necessary.
MRS can be issued only at all banks precharge state.
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10. Clock Suspend Exit & Power Down Exit
1) Clock Suspend (=Active Power Down) Exit
2) Power Down (=Precharge Power Down) Exit
CLK
CLK
CKE
Internal
CLK
CKE
tSS
Internal
CLK
*1
RD
CMD
CMD
tSS
*2
NOP ACT
11. Auto Refresh & Self Refresh
Auto Refresh
An auto refresh command is issued by having CS, RAS and CAS held low with CKE and WE high at the rising edge of the
clock(CLK). All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. No control of the external
address pins is required once this cycle has started because of the internal address counter. When the refresh cycle has completed,
all banks will be in the idle state. A delay between the auto refresh command and the next activate command or subsequent auto
refresh command must be greater than or equal to the tARFC(min).
∼
Auto
Refresh
PRE
CMD
∼
Command
∼
CLK
CKE = High
tRP(min)
tARFC(min)
Self Refresh
Command
Self
Refresh
NOP
∼ ∼
Stable Clock
∼
CLK
∼
∼ ∼
A Self Refresh command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. Once
the self Refresh command is initiated, CKE must be held low to keep the device in Self Refresh mode. After 1 clock cycle from the self
refresh command, all of the external control signals including system clock(CLK) can be disabled except CKE. The clock is internally
disabled during Self Refresh operation to reduce power. To exit the Self Refresh mode, supply stable clock input before returning CKE
high, assert deselect or NOP command and then assert CKE high. In case that the system uses burst auto refresh during normal
opreation, it is recommended to use burst auto refresh cycle immediately before entering self refresh mode and after exiting in self
refresh mode. On the other hand, if the system uses the distributed auto refresh, the system only has to keep the refresh duty cycle.
ACT
∼
tSRFX(min)
∼
CKE
tSS
tSS
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12. About Burst Type Control
Sequential Counting
At MRS A3 = "0". See the BURST SEQUENCE TABLE. (BL=4, 8)
BL=1, 2, 4, 8 and full page.
Interleave Counting
At MRS A3 = "1". See the BURST SEQUENCE TABLE. (BL=4, 8)
BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting.
Basic
MODE
Random
MODE
Random column Access
tCCD = 1 CLK
Every cycle Read/Write Command with random column address can realize Random
Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
13. About Burst Length Control
Basic
MODE
1
At MRS A2,1,0 = "000".
At auto precharge, tRAS should not be violated.
2
At MRS A2,1,0 = "001".
At auto precharge, tRAS should not be violated.
4
At MRS A2,1,0 = "010".
8
At MRS A2,1,0 = "011".
Full Page
Special
MODE
BRSW
Random
MODE
Burst Stop
RAS Interrupt
(Interrupted by Precharge)
Interrupt
MODE
CAS Interrupt
At MRS A2,1,0 = "111".
Wrap around mode(infinite burst length) should be stopped by burst stop.
RAS interrupt or CAS interrupt.
At MRS A9 = "1".
Read burst =1, 2, 4, 8, full page write Burst =1.
At auto precharge of write, tRAS should not be violated.
tBDL= 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively
Using burst stop command, any burst length control is possible.
Before the end of burst, Row precharge command of the same bank stops read/write
burst with Row precharge.
tRDL= 2 with DQM, valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
During read/write burst with auto precharge, RAS interrupt can not be issued.
Before the end of burst, new read/write stops read/write burst and starts new
read/write burst.
During read/write burst with auto precharge, CAS interrupt can not be issued.
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FUNCTION TRUTH TABLE (TABLE 1)
Current
State
IDLE
Row
Active
Read
Write
Read with
Auto
Precharge
Write with
Auto
Precharge
CS
RAS
CAS
WE
BA
Address
Action
Note
H
X
X
X
X
X
NOP
L
H
H
H
X
X
NOP
L
H
H
L
X
X
ILLEGAL
2
L
H
L
X
BA
CA, A10/AP ILLEGAL
2
L
L
H
H
BA
RA
L
L
H
L
BA
A10/AP
L
L
L
H
X
X
L
L
L
L
OP code
OP code
H
X
X
X
X
X
NOP
L
H
H
H
X
X
NOP
L
H
H
L
X
X
ILLEGAL
L
H
L
H
BA
CA, A10/AP Begin Read ; latch CA ; determine AP
L
H
L
L
BA
CA, A10/AP Begin Read ; latch CA ; determine AP
L
L
H
H
BA
RA
ILLEGAL
L
L
H
L
BA
A10/AP
Precharge
Row (& Bank) Active ; Latch RA
NOP
4
Auto Refresh or Self Refresh
5
Mode Register Access
5
L
L
L
X
X
X
ILLEGAL
H
X
X
X
X
X
NOP (Continue Burst to End --> Row Active)
L
H
H
H
X
X
NOP (Continue Burst to End --> Row Active)
L
H
H
L
X
X
Term burst --> Row active
L
H
L
H
BA
CA, A10/AP Term burst, New Read, Determine AP
L
H
L
L
BA
CA, A10/AP Term burst, New Write, Determine AP
L
L
H
H
BA
RA
L
L
H
L
BA
A10/AP
ILLEGAL
2
2
3
2
Term burst, Precharge timing for Reads
L
L
L
X
X
X
ILLEGAL
H
X
X
X
X
X
NOP (Continue Burst to End --> Row Active)
L
H
H
H
X
X
NOP (Continue Burst to End --> Row Active)
L
H
H
L
X
X
Term burst --> Row active
L
H
L
H
BA
CA, A10/AP Term burst, New read, Determine AP
3
L
H
L
L
BA
CA, A10/AP Term burst, New Write, Determine AP
3
L
L
H
H
BA
RA
L
L
H
L
BA
A10/AP
L
L
L
X
X
X
ILLEGAL
ILLEGAL
2
Term burst, precharge timing for Writes
3
H
X
X
X
X
X
NOP (Continue Burst to End --> Precharge)
L
H
H
H
X
X
NOP (Continue Burst to End --> Precharge)
L
H
H
L
X
X
ILLEGAL
L
H
L
X
BA
L
L
H
X
BA
RA, RA10
ILLEGAL
L
L
L
X
X
X
ILLEGAL
CA, A10/AP ILLEGAL
H
X
X
X
X
X
NOP (Continue Burst to End --> Precharge)
L
H
H
H
X
X
NOP (Continue Burst to End --> Precharge)
L
H
H
L
X
X
ILLEGAL
L
H
L
X
BA
L
L
H
X
BA
RA, RA10
ILLEGAL
L
L
L
X
X
X
ILLEGAL
2
CA, A10/AP ILLEGAL
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MCP MEMORY
FUNCTION TRUTH TABLE (TABLE 1)
Current
Precharging
Row
Activating
Refreshing
Mode
Register
Accessing
CS
RAS
CAS
WE
BA
Address
Action
Note
H
X
X
X
X
X
NOP --> Idle after tRP
L
H
H
H
X
X
NOP --> Idle after tRP
L
H
H
L
X
X
ILLEGAL
2
L
H
L
X
BA
CA
ILLEGAL
2
L
L
H
H
BA
RA
ILLEGAL
2
L
L
H
L
BA
A10/AP
NOP --> Idle after tRP
4
L
L
L
X
X
X
ILLEGAL
H
X
X
X
X
X
NOP --> Row Active after tRCD
L
H
H
H
X
X
NOP --> Row Active after tRCD
L
H
H
L
X
X
ILLEGAL
2
L
H
L
X
BA
CA
ILLEGAL
2
L
L
H
H
BA
RA
ILLEGAL
2
L
L
H
L
BA
A10/AP
ILLEGAL
2
L
L
L
X
X
X
ILLEGAL
H
X
X
X
X
X
NOP --> Idle after tRC
L
H
H
X
X
X
NOP --> Idle after tRC
L
H
L
X
X
X
ILLEGAL
L
L
H
X
X
X
ILLEGAL
L
L
L
X
X
X
ILLEGAL
H
X
X
X
X
X
NOP --> Idle after 2 clocks
L
H
H
H
X
X
NOP --> Idle after 2 clocks
L
H
H
L
X
X
ILLEGAL
L
H
L
X
X
X
ILLEGAL
L
L
X
X
X
X
ILLEGAL
Abbreviations : RA = Row Address
NOP = No Operation Command
BA = Bank Address
CA = Column Address
AP = Auto Precharge
*NOTE:
1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle.
2. Illegal to bank in specified state ; Function may be Iegal in the bank indicated by BA, depending on the
state of that bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and A10/AP).
5. Illegal if any bank is not idle.
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MCP MEMORY
FUNCTION TRUTH TABLE (TABLE 2)
Current
State
Self
Refresh
All
Banks
Precharge
Power
Down
All
Banks
Idle
Any State
other than
Listed
above
CKE
(n-1)
CKE
n
CS
RAS
CAS
WE
Address
Action
Note
H
X
X
X
X
X
X
Exit Self Refresh --> Idle after tsRFX(ABI)
L
H
H
X
X
X
X
Exit Self Refresh --> Idle after tsRFX (ABI)
6
L
H
L
H
H
H
X
Exit Self Refresh --> Idle after tsRFX (ABI)
6
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP (Maintain Self Refresh)
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit Power Down --> ABI
L
H
L
H
H
H
X
Exit Power Down --> ABI
7
L
H
L
H
H
L
X
ILLEGAL
7
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP (Maintain Low Power Mode)
H
H
X
X
X
X
X
Refer to Table 1
H
L
H
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
Enter Power Down
8
H
L
L
H
H
L
X
ILLEGAL
8
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
H
H
RA
H
L
L
L
L
H
X
H
L
L
L
L
L
Row (& Bank) Active
Enter Self Refresh
8
OP Code Mode Register Access
L
L
X
X
X
X
X
NOP
H
H
X
X
X
X
X
Refer to Operations in Table 1
H
L
X
X
X
X
X
Begin Clock Suspend next cycle
9
L
H
X
X
X
X
X
Exit Clock Suspend next cycle
9
L
L
X
X
X
X
X
Maintain Clock Suspend
Abbreviations : ABI = All Banks Idle, RA = Row Address
*NOTE:
6. CKE low to high transition is asynchronous.
7. CKE low to high transition is asynchronous if restarts internal clock.
A minimum setup time 1CLK + tSS must be satisfied before any command other than exit.
8. Power down and self refresh can be entered only from the all banks idle state.
9. Must be a legal command.
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Power Up Sequence
Single Bit Read - Write - Read Cycle(Same Page) @CAS Latency=3, Burst Length=1
Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK
Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK
Page Read Cycle at Different Bank @Burst Length=4
Page Write Cycle at Different Bank @Burst Length=4, tRDL=2CLK
Read & Write Cycle at Different Bank @Burst Length=4
Read & Write Cycle With Auto Precharge l @Burst Length=4
Read & Write Cycle With Auto Precharge ll @Burst Length=4
Clock Suspension & DQM Operation Cycle @CAS Letency=2, Burst Length=4
Read Interrupted by Precharge Command & Read Burst Stop Cycle @ Full Page Burst
Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Full Page Burst, tRDL=2CLK
Burst Read Single bit Write Cycle @Burst Length =2
Active/precharge Power Dower Down Mode @CAS Latency=2 Burst Length=4
Self Refresh Entry & Exit Cycle & Exit Cycle
Mode Register Set Cycle and Auto Refresh Cycle
Extended Mode Register Set Cycle
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MCP MEMORY
Power Up Sequence for Mobile SDRAM
0
1
2
3
4
5
≈ ≈
≈ ≈
≈ ≈
≈ ≈
≈ ≈
≈ ≈
≈
tARFC
Auto
Refresh
13
14 15 16
Key
17 18 19 20 21 22 23 24 25
Key
RAa
RAa
≈
Precharge
(All Bank)
≈ ≈
tRP
≈
High level is necessary
≈
DQM
Hi-Z
≈ ≈
WE
≈
Hi-Z
≈
DQ
≈ ≈
A10/AP
≈ ≈
BA1
≈ ≈
BA0
≈ ≈
ADDR
≈ ≈
CAS
12
≈ ≈
RAS
10 11
≈ ≈
CS
9
≈
Hi
8
≈
CKE
7
≈ ≈
CLOCK
6
tARFC
Auto
Refresh
Normal
MRS
Extended
MRS
Row Active
(A-Bank)
: Don’t care
*NOTE:
1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.
- Apply VDD before or at the same time as VDDQ.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS.
EMRS cycle is not mandatory and the EMRS command needs to be issued only when DS or PASR is used.
The default state without EMRS command issued is the half driver strength and full array refreshed.
The device is now ready for the operation selected by EMRS.
For operating with DS or PASR , set DS or PASR mode in EMRS setting stage.
In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not needed again
at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set.
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MCP MEMORY
Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1
0
1
2
tCH
4
3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
tCC
tCL
CKE
HIGH
tRAS
tRC
tRP
tSH
*Note 1
CS
tRCD
tSS
tSH
RAS
tSS
tSH
CAS
tSH
ADDR
Ra
tSS
Ca
Cb
Cc
*Note 2,3
*Note 2,3
Rb
tSS
*Note 2
BA0,BA1
BS
A10/AP
Ra
BS
BS
*Note 3
*Note 2,3 *Note 4
BS
*Note 3
*Note 2
BS
*Note 3
BS
*Note 4
Rb
tSAC
DQ
Qa
tSLZ
tOH
tSH
Db
Qc
tSS
tSS tSH
WE
tSS tSH
DQM
Row Active
Read
Write
Read
Row Active
Precharge
: Don’t care
*NOTE:
1. All input except CKE & DQM can be don't care when CS is high at the CLK high going edge.
2. Bank active & read/write are controlled by BA0,BA1.
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MCP MEMORY
Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
tRC
*Note 1
CS
RAS
*Note 2
CAS
ADDR
Ra
Rb
Ca
Cb
BA0
BA1
A10/AP
Rb
Ra
tOH
{
CL=2
Qa0
tRCD
DQ
Qa1
Qa2
Qa3
Db0
tSHZ
tSAC
Db1
Db2
Db3
tRDL
*Note 4
tOH
CL=3
Qa0
Qa1
Qa2
Qa3
Db0
tSHZ
tSAC
Db1
Db2
Db3
tRDL
*Note 4
WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
: Don’t care
*NOTE:
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output data
is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clcok.
3. Ouput will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
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MCP MEMORY
Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
*Note 2
CAS
ADDR
Ra
Ca
Cb
Cc
Cd
Rb
BA0
BA1
A10/AP
Rb
Ra
tRDL
{
CL=2
Qa0
Qa1
Qb0
Qb1
Qb2
Dc0
Dc1
Dd0
Dd1
tRCD
DQ
tDAL
*Note 4
CL=3
Qa0
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
Dd1
tCDL
WE
*Note 1
*Note 3
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
: Don’t care
*NOTE:
1. To write data before burst read ends, DQM should be asserted three cycle prior to write
command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
4. tDAL ,last data in to active delay, is 2CLK + tRP.
75
Revision 0.1
July 2005
KBE00G003M-D411
MCP MEMORY
Page Read Cycle at Different Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
*Note 1
CS
RAS
*Note 2
CAS
ADDR
RAa
RBb
RAa
RBb
CAa
RCc
CBb
RDd
CCc
CDd
BA0
BA1
A10/AP
RCc
{
CL=2
RDd
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
DQ
CL=3
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Row Active
(B-Bank)
Read
(B-Bank)
Row Active
(C-Bank)
Read
(C-Bank)
Row Active
(D-Bank)
Precharge
(A-Bank)
Read
(D-Bank)
Precharge
(D-Bank)
Precharge
(C-Bank)
Precharge
(B-Bank)
: Don’t care
*NOTE:
1. CS can be don't cared when RAS, CAS and WE are high at the clock high going dege.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
76
Revision 0.1
July 2005
KBE00G003M-D411
MCP MEMORY
Page Write Cycle at Different Bank @Burst Length=4, tRDL=2CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
*Note 2
CAS
ADDR
RAa
RAb
RAa
RBb
CAa
CBb
RCc
RDd
RCc
RDd
CCc
CDd
BA0
BA1
A10/AP
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DCc0 DCc1 DDd0 DDd1 DDd2
DQ
tCDL
tRDL
WE
*Note 1
DQM
Row Active
(A-Bank)
Write
(A-Bank)
Row Active
(B-Bank)
Write
(B-Bank)
Row Active
(D-Bank)
Row Active
(C-Bank)
Write
(D-Bank)
Precharge
(All Banks)
Write
(C-Bank)
: Don’t care
*NOTE:
1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
77
Revision 0.1
July 2005
KBE00G003M-D411
MCP MEMORY
Read & Write Cycle at Different Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
CAa
CDb
RDb
RBc
CBc
BA0
BA1
A10/AP
RAa
RBc
RDb
tCDL
{
CL=2
QAa0 QAa1 QAa2 QAa3
*Note 1
DDb0 DDb1 DDb2 DDb3
QBc0 QBc1 QBc2
DDb0 DDb1 DDb2 DDb3
QBc0 QBc1
DQ
CL=3
QAa0 QAa1 QAa2 QAa3
WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Write
(D-Bank)
Row Active
(D-Bank)
Read
(B-Bank)
Row Active
(B-Bank)
: Don’t care
*NOTE:
1. tCDL should be met to complete write.
78
Revision 0.1
July 2005
KBE00G003M-D411
MCP MEMORY
Read & Write Cycle with Auto Precharge I @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
RBb
RAa
RBb
CAa
CBb
RAc
CAc
BA0
BA1
A10/AP
RAc
DAc0 DAc1
QAa0 QAa1 QBb0 QBb1 QBb2 DBb3
DQ CL=2
CL=3
DAc0 DAc1
QAa0 QAa1 QBb0 QBb1 QBb2 DBb3
WE
DQM
Row Active
(A-Bank)
Read with
Auto Pre
charge
(A-Bank)
Row Active
(B-Bank)
Read without Auto
Precharge(B-Bank)
Auto Precharge
Start Point
(A-Bank) *Note1
Precharge
(B-Bank)
Row Active
(A-Bank)
Write with
Auto Precharge
(A-Bank)
: Don’t care
*NOTE:
1. When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation.
- if Read(Write) command without auto precharge is issued at B-Bank before A-Bank auto precharge starts, A-Bank
auto precharge will start at B-Bank read command input point .
- any command can not be issued at A-Bank during tRP after A-Bank auto precharge starts.
79
Revision 0.1
July 2005
KBE00G003M-D411
MCP MEMORY
Read & Write Cycle with Auto Precharge II @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Qb0
Qb1
Qb2
Qb3
Qb0
Qb1
Qb2
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
Ra
Ca
Rb
Cb
BA0
BA1
A10/AP
Ra
Rb
DQ CL=2
Qa0
CL=3
Qa1
Qa2
Qa3
Qa0
Qa1
Qa2
Qa3
Qb3
WE
DQM
*Note1
Row Active
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Auto Precharge
Start Point
(A-Bank)
Row Active
(B-Bank)
Read with
Auto Precharge
(B-Bank)
Auto Precharge
Start Point
(B-Bank)
: Don’t care
*NOTE:
1. Any command to A-bank is not allowed in this period.
tRP is determined from at auto precharge start point
80
Revision 0.1
July 2005
KBE00G003M-D411
MCP MEMORY
Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
Ra
Ca
Cc
Cb
BA0
BA1
A10/AP
Ra
Qa0
DQ
Qa1
Qa2
Qa3
Qb0
tSHZ
Qb1
Dc0
Dc2
tSHZ
WE
*Note 1
DQM
Row Active
Read
Clock
Suspension
Read
Read DQM
Write
DQM
Write
Write
DQM
Clock
Suspension
: Don’t care
*NOTE:
1. DQM is needed to prevent bus contention.
81
Revision 0.1
July 2005
KBE00G003M-D411
MCP MEMORY
Read Interrupted by Precharge Command & Read Burst Stop Cycle @Full Page Burst
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
CAa
CAb
BA0
BA1
A10/AP
{
RAa
CL=2
1
1
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
DQ
CL=3
2
2
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Burst Stop
Read
(A-Bank)
Precharge
(A-Bank)
: Don’t care
*NOTE:
1. At full page mode, burst is finished by burst stop or precharge.
2. About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1, 2 on them.
But at burst write, Burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of "Full page write burst stop cycle".
3. Burst stop is valid at every burst length.
82
Revision 0.1
July 2005
KBE00G003M-D411
MCP MEMORY
Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Full Page Burst,
tRDL=2CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
CAa
CAb
BA0
BA1
A10/AP
RAa
*Note 1
tBDL
DAa0 DAa1 DAa2 DAa3 DAa4
DQ
*Note 1,2
tRDL
DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
WE
DQM
Row Active
(A-Bank)
Write
(A-Bank)
Burst Stop
Write
(A-Bank)
Precharge
(A-Bank)
: Don’t care
*NOTE:
1. At full page mode, burst is finished by burst stop or precharge.
2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding
memory cell. It is defined by AC parameter of tRDL.
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
3. Burst stop is valid at every burst length.
83
Revision 0.1
July 2005
KBE00G003M-D411
MCP MEMORY
Burst Read Single bit Write Cycle @Burst Length=2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
*Note 2
CAS
ADDR
RAa
CAa
RBb
CAb
RCc
CBc
CCd
BA0
BA1
A10/AP
{
RAa
RBb
CL=2
DAa0
CL=3
DAa0
RCc
QAb0 QAb1
DBc0
QCd0 QCd1
DQ
QAb0 QAb1
DBc0
QCd0 QCd1
WE
DQM
Row Active
(A-Bank)
Row Active
(B-Bank)
Row Active
(C-Bank)
Write
Read with
(A-Bank) Auto Precharge
(A-Bank)
Read
(C-Bank)
Precharge
(C-Bank)
Write with
Auto Precharge
(B-Bank)
: Don’t care
*NOTE:
1. BRSW modes is enabled by setting A9 "High" at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to "1" regardless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,
the next cycle starts the precharge.
84
Revision 0.1
July 2005
KBE00G003M-D411
MCP MEMORY
Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4
0
1
2
6
7
*Note 1
8
tSS
17
18
19
Ra
Ca
Ra
≈ ≈
≈
≈
Qa0
Qa1
Qa2
tSHZ
≈ ≈
≈ ≈
≈ ≈
≈ ≈
Precharge
Power-down
Entry
16
≈ ≈
≈ ≈
DQ
15
tSS
≈ ≈
≈ ≈
A10/AP
14
≈ ≈
≈ ≈
BA
13
≈ ≈
≈ ≈
ADDR
12
≈ ≈
≈ ≈
CAS
11
≈
≈ ≈
RAS
DQM
10
*Note 2
*Note 3
CS
WE
9
*Note 2
≈
CKE
5
≈
tSS
4
≈ ≈
CLOCK
3
Row Active
Precharge
Power-down
Exit
Active
Power-down
Entry
Read
Precharge
Active
Power-down
Exit
: Don’t care
*NOTE:
1. All banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1CLK + tSS prior to Row active command.
3. Can not violate minimum refresh specification. (64ms)
85
Revision 0.1
July 2005
KBE00G003M-D411
MCP MEMORY
Self Refresh Entry & Exit Cycle
0
1
2
3
4
5
8
9
10
11
12
*Note 4
CKE
15
16
17
18
19
tSRFX
*Note 6
≈
*Note 3
tSS
≈
≈ ≈
CS
≈ ≈
≈ ≈
RAS
≈ ≈
≈ ≈
CAS
≈ ≈
≈ ≈
ADDR
≈ ≈
≈ ≈
BA0,BA1
Hi-Z
≈ ≈
≈ ≈
WE
≈ ≈
≈ ≈
DQM
≈
≈
Hi-Z
≈ ≈
≈ ≈
A10/AP
DQ
14
≈
*Note 1
13
≈
*Note 2
7
≈ ≈
CLOCK
6
Self Refresh Entry
Self Refresh Exit
Auto Refresh
: Don’t care
*NOTE:
TO ENTER SELF REFRESH MODE
1. CS, RAS & CAS with CKE should be low at the same clcok cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in self refresh mode as long as CKE stays "Low".
cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum tSRFX is required after CKE going high to complete self refresh exit.
7. 4K cycle(64Mb ,128Mb) or 8K cycle(256Mb, 512Mb) of burst auto refresh is required before self refresh entry and
after self refresh exit if the system uses burst refresh.
86
Revision 0.1
July 2005
KBE00G003M-D411
MCP MEMORY
Mode Register Set Cycle
0
1
2
3
4
Auto Refresh Cycle
5
6
0
1
2
3
4
5
7
8
9
10
≈
CLOCK
6
HIGH
≈
HIGH
CKE
≈
CS
tARFC
*Note 2
≈ ≈
RAS
≈ ≈
*Note 1
CAS
*Note 3
ADDR
Key
Ra
BA0
BA1
Hi-Z
≈
Hi-Z
DQ
≈ ≈
WE
≈ ≈
DQM
MRS
New Command
Auto Refresh
New Command
* All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
: Don’t care
*NOTE:
MODE REGISTER SET CYCLE
1. CS, RAS, CAS, BA0, BA1 & WE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
87
Revision 0.1
July 2005
KBE00G003M-D411
MCP MEMORY
Extended Mode Register Set Cycle
0
1
2
3
4
5
6
CLOCK
HIGH
CKE
CS
*Note 2
RAS
*Note 1
CAS
*Note 3
ADDR
Key
Ra
BA0
BA1
Hi-Z
DQ
WE
DQM
EMRS
New Command
: Don’t care
*NOTE:
EXTENDED MODE REGISTER SET CYCLE
1. CS, RAS, CAS, BA0, BA1 & WE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
88
Revision 0.1
July 2005
KBE00G003M-D411
MCP MEMORY
PACKAGE DIMENSION
107-Ball Fine pitch Ball Grid Array Package (measured in millimeters)
Units:millimeters
#A1 INDEX MARK
10.50±0.10
0.10 MAX
10.50±0.10
A
0.80x9=7.20
(Datum A)
B
10 9 8 7 6 5 4 3 2 1
A
B
#A1
D
0.80
(Datum B)
0.80
E
0.80x13=10.40
13.00±0.10
0.45±0.05
13.00±0.10
13.00±0.10
C
F
G
H
5.20
J
K
L
M
N
P
0.32±0.05
3.60
1.30±0.10
TOP VIEW
107-∅ 0.45±0.05
BOTTOM VIEW
∅ 0.20 M A B
89
Revision 0.1
July 2005