KM416C254D, KM416V254D CMOS DRAM 256K x 16Bit CMOS Dynamic RAM with Extended Data Out DESCRIPTION This is a family of 262,144 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row. Power supply voltage(+5.0V or +3.3V), Access time (-5,-6 or -7), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RASonly refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 256Kx16 EDO Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines. • Extended Data Out Mode operation FEATURES • 2 CAS Byte/Wrod Read/Write operation • Part Identification • CAS-before-RAS refresh capability • RAS-only and Hidden refresh capability - KM416C254D/DL (5V, 512 Ref.) - KM416V254D/DL (3.3V, 512 Ref.) • Self-refresh capability (L-ver only) • TTL(5V)/LVTTL(3.3V) compatible inputs and outputs • Early Write or output enable controlled write • Active Power Dissipation • JEDEC Standard pinout Unit : mW Speed 3.3V(512 Ref.) 5V(512 Ref.) -5 - 605 -6 255 495 -7 235 440 • Available in 40-pin SOJ 400mil and 44(40)-pin packages • Triple +5V±10% power supply (5V product) • Triple +3.3V±0.3V power supply (3.3V product) FUNCTIONAL BLOCK DIAGRAM • Refresh Cycles VCC C254D 5V V254D 3.3V Refresh cycle Refresh period Normal 512 8ms L-ver 128ms RAS UCAS LCAS W Control Clocks Refresh Timer Refresh Control tRAC tCAC tRC tHPC Remark -5 50ns 15ns 84ns 20ns 5V only -6 60ns 15ns 104ns 25ns 5V/3.3V -7 70ns 20ns 124ns 30ns 5V/3.3V Refresh Counter Memory Array 262,144 x16 Cells Row Address Buffer A0~A8 Col. Address Buffer Lower Data in Buffer Row Decoder • Performance Range Speed Vcc Vss VBB Generator Column Decoder SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. Sense Amps & I/O Part NO. Lower Data out Buffer Upper Data in Buffer Upper Data out Buffer DQ0 to DQ7 OE DQ8 to DQ15 KM416C254D, KM416V254D CMOS DRAM PIN CONFIGURATION (Top Views) •KM416C/V254DJ •KM416C/V254DT VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 1 2 3 4 5 6 7 8 9 10 40 39 38 37 36 35 34 33 32 31 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 1 2 3 4 5 6 7 8 9 10 40 39 38 37 36 35 34 33 32 31 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 N.C N.C W RAS N.C A0 A1 A2 A3 VCC 11 12 13 14 15 16 17 18 19 20 30 29 28 27 26 25 24 23 22 21 N.C LCAS UCAS OE A8 A7 A6 A5 A4 VSS N.C N.C W RAS N.C A0 A1 A2 A3 VCC 11 12 13 14 15 16 17 18 19 20 30 29 28 27 26 25 24 23 22 21 N.C LCAS UCAS OE A8 A7 A6 A5 A4 VSS (SOJ) (TSOP-II) Pin Name A0 - A8 DQ0 - 15 Pin Function Address Inputs Data In/Out VSS Ground RAS Row Address Strobe UCAS Upper Column Address Strobe LCAS Lower Column Address Strobe W Read/Write Input OE Data Output Enable VCC Power(+5V) Power(+3.3V) N.C No Connection KM416C254D, KM416V254D CMOS DRAM ABSOLUTE MAXIMUM RATINGS Parameter Rating Symbol Units 3.3V 5V VIN,VOUT -0.5 to +4.6 -1.0 to +7.0 V Voltage on VCC supply relative to VSS VCC -0.5 to +4.6 -1.0 to +7.0 V Storage Temperature Tstg -55 to +150 -55 to +150 °C Power Dissipation PD 1 1 W Short Circuit Output Current IOS 50 50 mA Voltage on any pin relative to VSS * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C) Parameter 3.3V Symbol 5V Units Min Typ Max Min Typ Max Supply Voltage VCC 3.0 3.3 3.6 4.5 5.0 5.5 V Ground VSS 0 0 0 0 0 0 V Input High Voltage VIH 2.0 - VCC+0.3*1 2.4 - VCC+1.0*1 V Input Low Voltage VIL -0.3*2 - 0.8 -1.0*2 - 0.8 V *1 : VCC+1.3V/15ns(3.3V), VCC+2.0V/20ns(5V), Pulse width is measured at VCC *2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at VSS DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Max 3.3V 5V Parameter Symbol Min Max Units Input Leakage Current (Any input 0≤VIN≤VIN+0.3V, all other input pins not under test=0 Volt) II(L) -5 5 uA Output Leakage Current (Data out is disabled, 0V≤VOUT ≤VCC) IO(L) -5 5 uA Output High Voltage Level(IOH=-2mA) VOH 2.4 - V Output Low Voltage Level(IOL=2mA) VOL - 0.4 V Input Leakage Current (Any input 0≤VIN≤VIN+0.5V, all other input pins not under test=0 Volt) II(L) -5 5 uA Output Leakage Current (Data out is disabled, 0V≤VOUT ≤VCC) IO(L) -5 5 uA Output High Voltage Level(IOH=-5mA) VOH 2.4 - V Output Low Voltage Level(IOL=4.2mA) VOL - 0.4 V KM416C254D, KM416V254D CMOS DRAM DC AND OPERATING CHARACTERISTICS (Continued) Symbol Power Max Speed Units KM416V254D KM416C254D ICC1 Don′t care -5 -6 -7 70 65 110 90 80 mA mA mA ICC2 Don′t care Don′t care 1 2 mA ICC3 Don′t care -5 -6 -7 70 65 110 90 80 mA mA mA ICC4 Don′t care -5 -6 -7 60 55 90 80 70 mA mA mA ICC5 Normal L Don′t care 0.5 100 1 150 mA uA ICC6 Don′t care -5 -6 -7 70 65 110 90 80 mA mA mA ICC7 L Don′t care 200 300 uA ICCS L Don′t care 100 200 uA ICC1 * : Operating Current (RAS and UCAS, LCAS, Address cycling @tRC=min.) ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH) ICC3 * : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS, Address cycling @tRC=min.) ICC4 * : Extended Data Out Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tHPC =min.) ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V) ICC6 * : CAS-Before-RAS Refresh Current (RAS and UCAS or LCAS cycling @tRC=min.) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, UCAS, LCAS=0.2V, DQ=Don′t care, TRC=125us, TRAS =TRAS min~300ns ICCS : Self Refresh Current RAS=UCAS=LCAS=VIL, W=OE=A0 ~ A8=VCC-0.2V or 0.2V, DQ0 ~ DQ15=VCC-0.2V, 0.2V or Open *Note : ICC1 , ICC3 , ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 , ICC3 , ICC6 and ICC7, address can be changed maximum once while RAS=VIL. In ICC4 , address can be changed maximum once within one Hyper page mode cycle time, tHPC . KM416C254D, KM416V254D CMOS DRAM CAPACITANCE (TA=25°C, VCC=5V or 3.3V, f=1MHz) Parameter Symbol Min Max Units Input capacitance [A0 ~ A8] CIN1 - 5 pF Input capacitance [RAS, UCAS, LCAS, W, OE] CIN2 - 7 pF Output capacitance [DQ0 - DQ15] CDQ - 7 pF AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2) Test condition (5V device) : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V Test condition (3.3V device) : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V Parameter -6 -5*1 Symbol Min Max Min -7 Max Min Units Notes Max Random read or write cycle time tRC 84 104 124 ns Read-modify-write cycle time tRWC 116 138 163 ns Access time from RAS tRAC Access time from CAS Access time from column address CAS to output in Low-Z tCLZ 3 Output buffer turn-off delay from CAS tCEZ 3 13 3 13 3 Transition time (rise and fall) tT 2 50 2 50 2 RAS precharge time tRP 30 RAS pulse width tRAS 50 RAS hold time tRSH 15 15 20 ns CAS hold time tCSH 40 50 60 ns CAS pulse width tCAS 8 10K 10 10K 15 10K ns RAS to CAS delay time 50 60 70 ns 3,4,10 tCAC 15 15 20 ns 3,4,5 tAA 25 30 35 ns 3,10 ns 3 18 ns 6,12 50 ns 2 3 3 40 10K 60 50 10K 70 ns 10K ns tRCD 20 35 20 45 20 50 ns 4 RAS to column address delay time tRAD 15 25 15 30 15 35 ns 10 CAS to RAS precharge time tCRP 5 5 5 ns Row address set-up time tASR 0 0 0 ns Row address hold time tRAH 10 10 10 ns Column address set-up time tASC 0 0 0 ns 13 Column address hold time tCAH 8 10 15 ns 13 Column address to RAS lead time tRAL 25 30 35 ns Read command set-up time tRCS 0 0 0 ns Read command hold time referenced to CAS tRCH 0 0 0 ns 8 Read command hold time referenced to RAS tRRH 0 0 0 ns 8 Write command set-up time 7 tWCS 0 0 0 ns Write command hold time tWCH 10 10 10 ns Write command pulse width tWP 10 10 10 ns Write command to RAS lead time tRWL 13 15 15 ns Write command to CAS lead time tCWL 8 10 15 ns Note) *1 : 5V only 16 KM416C254D, KM416V254D CMOS DRAM AC CHARACTERISTICS (Continued) Parameter Min Data set-up time tDS 0 Data hold time tDH 8 Refresh period (Normal) Refresh period (L-ver) -6 -5*1 Symbol Max Min -7 Max 0 Min 0 10 Units Notes ns 9,19 ns 9,19 Max 15 tREF 8 8 8 ms tREF 128 128 128 ms CAS to W delay time tCWD 32 32 42 ns 7,15 RAS to W delay time tRWD 67 77 92 ns 7 Column address to W delay time tAWD 42 47 57 ns 7 CAS precharge to W delay time tCPWD 45 52 62 ns 7 CAS set-up time (CAS -before-RAS refresh) tCSR 5 5 5 ns 17 CAS hold time (CAS -before-RAS refresh) tCHR 10 10 10 ns 18 RAS to CAS precharge time tRPC 5 5 5 ns CAS precharge time (C-B-R counter test cycle) tCPT 20 20 25 ns Access time from CAS precharge tCPA Hyper Page mode cycle time ns 3 tHPC 20 25 30 ns 11 Hyper Page read-modify-write cycle time tHPRWC 57 66 81 ns 11 CAS precharge time (Hyper Page cycle) tCP 8 RAS pulse width (Hyper Page cycle) tRASP 50 ns 14 RAS hold time from CAS precharge tRHCP 30 OE access time tOEA OE to data delay tOED Output buffer turn off delay time from OE 28 35 10 100K 60 10 100K 35 15 13 40 70 100K 40 15 13 ns ns 20 18 ns tOEZ 3 OE command hold time tOEH 15 15 20 ns Output data hold time tDOH 5 5 5 ns Output buffer turn off delay from RAS 13 3 13 3 3 ns 18 ns 6 tREZ 3 15 3 15 3 20 ns 6,12 Output buffer turn off delay from W tWEZ 3 13 3 13 3 18 ns 6 W to data delay tWED 13 13 18 ns OE to CAS hold time tOCH 5 5 5 ns CAS hold time to OE tCHO 5 5 5 ns OE precharge time tOEP 5 5 5 ns W pulse width (Hyper Page Cycle) tWPE 5 5 5 ns RAS pulse width (C-B-R self refresh) tRASS 100 100 100 us 20,21,22 RAS precharge time (C-B-R self refresh) tRPS 90 110 130 ns 20,21,22 tCHS -50 -50 -50 ns 20,21,22 CAS hold time (C-B-R self refresh) Note) *1 : 5V only KM416C254D, KM416V254D CMOS DRAM NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 2ns for all inputs. 3. Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 50pF. 4. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 5. Assumes that tRCD ≥tRCD (max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol. 7. tWCS , tRWD , tCWD , tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥tWCS (min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD ≥tCWD (min), tRWD ≥tRWD (min), tAWD ≥tAWD (min) and tCPWD ≥tCPWD (min) then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to the first CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle and read-modify-write cycles. 10. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled by tAA. 11. tASC ≥6ns, Assume tT = 2.0ns 12. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes high before RAS high going, the open circuit condition of the output is achieved by RAS going. KM416C/V254D/DL Truth Table RAS LCAS UCAS W OE DQ0 - DQ7 DQ8-DQ15 STATE H H H H H Hi-Z Hi-Z Standby L H H H H Hi-Z Hi-Z Refresh L L H H L DQ-OUT Hi-Z Byte Read L H L H L Hi-Z DQ-OUT Byte Read L L L H L DQ-OUT DQ-OUT Word Read L L H L H DQ-IN - Byte Write L H L L H - DQ-IN Byte Write L L L L H DQ-IN DQ-IN Word Write L L L H H Hi-Z Hi-Z - KM416C254D, KM416V254D CMOS DRAM 13. tASC , tCAH are referenced to the earlier CAS rising edge. 14. tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle. 15. tCWD is referenced to the later CAS falling edge at word red-modify-write cycle. 16. tCWL is specified from W falling edge to the earlier CAS rising edge. 17. tCSR is referenced to earlier CAS falling low before RAS transition low. 18. tCHR is referenced to the later CAS rising high after RAS transition low. RAS LCAS UCAS tCSR tCHR 19. tDS, tDH are specified for the earlier CAS falling low. LCAS UCAS tDS DQ0 ~ DQ15 tDH Din W 20. f tRASS ≥100us, then RAS precharge time must use tRPS instead of tRP. 21. For RAS-only refresh and burst CAS-before-RAS refresh mode, 512(512K) cycle of burst refresh must be executed within 8ms before and after self refresh, in order to meet refresh specification. 22. For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification. KM416C254D, KM416V254D CMOS DRAM WORD READ CYCLE tRC tRAS RAS VIL - tCSH tCRP UCAS tRCD tCRP tRSH VIH - tCAS VIL - tCSH tCRP LCAS tRP VIH - tRCD tCRP tRSH tCAS VIH VIL - tRAD tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tRCH tRCS W tRRH VIH VIL - tAA tOLZ OE VIH - tOEA VIL - DQ0 ~ DQ7 VOH VOL - tRAC tCAC tCLZ OPEN tCEZ tOEZ DATA-OUT tCAC DQ8 ~ DQ15 VOH VOL - tRAC OPEN tCLZ tCEZ tOEZ DATA-OUT Don′t care Undefined KM416C254D, KM416V254D CMOS DRAM LOWER BYTE READ CYCLE NOTE : DIN = OPEN tRC tRAS RAS tRP VIH VIL - tRPC tCRP UCAS VIH VIL - tCSH tCRP LCAS tRSH tCAS VIH VIL - tRAD tASR A tRCD VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tRCH tRCS W tRRH VIH VIL - tCEZ tAA OE VIH - tOEA VIL - DQ0 ~ DQ7 VOH VOL - tOEZ tRAC tCAC tCLZ OPEN DATA-OUT tOLZ DQ8 ~ DQ15 VOH VOL - OPEN Don′t care Undefined KM416C254D, KM416V254D CMOS DRAM UPPER BYTE READ CYCLE NOTE : DIN = OPEN tRC tRAS RAS VIL - tCSH tCRP UCAS tRP VIH - tRCD tCAS VIL - tRPC tCRP LCAS tCRP tRSH VIH - VIH VIL - tRAD tRAL tASR A VIH VIL - tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tRCH tRCS W tRRH VIH VIL - tCEZ tAA OE VIH - tOEZ tOEA VIL - tOLZ DQ0 ~ DQ7 VOH - OPEN VOL DQ8 ~ DQ15 VOH VOL - tCAC tRAC OPEN tCLZ DATA-OUT Don′t care Undefined KM416C254D, KM416V254D CMOS DRAM WORD WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS VIL - tCSH tCRP UCAS tRCD tCAS tCSH tRCD tRSH VIL - VIH VIL - OE tCRP tCAS VIH - tRAD tRAH tRAL tASC ROW ADDRESS tCAH COLUMN ADDRESS tWCS W tCRP VIL - tASR A tRSH VIH - tCRP LCAS tRP VIH - VIH - tWCH tWP VIL - VIH VIL - DQ0 ~ DQ7 VIH - tDS DATA-IN VIL - DQ8 ~ DQ15 VIH - tDH tDS tDH DATA-IN VIL - Don′t care Undefined KM416C254D, KM416V254D CMOS DRAM LOWER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS tRP VIH VIL - tCRP UCAS VIH VIL - tCSH tCRP LCAS tRCD tRSH tCRP tCAS VIH VIL - tRAD tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tWCS W OE VIH - tWCH tWP VIL - VIH VIL - DQ0 ~ DQ7 VIH VIL - tDS tDH DATA-IN DQ8 ~ DQ15 VIH VIL - Don′t care Undefined KM416C254D, KM416V254D CMOS DRAM UPPER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS VIL - tCSH tCRP UCAS tRP VIH - tRCD tRSH VIH - tCRP tCAS VIL - tCRP LCAS VIH VIL - tRAD tASR A VIH VIL - tRAH tRAL tASC tCAH COLUMN ADDRESS ROW ADDRESS tWCS W OE VIH - tWCH tWP VIL - VIH VIL - DQ0 ~ DQ7 VIH VIL - DQ8 ~ DQ15 VIH VIL - tDS tDH DATA-IN Don′t care Undefined KM416C254D, KM416V254D CMOS DRAM WORD WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS VIL - tCSH tCRP UCAS tRCD tCRP tCAS VIL - tCSH tRCD tRSH VIL - VIH VIL - tCRP tCAS VIH - tRAD tASR A tRSH VIH - tCRP LCAS tRP VIH - tRAH tRAL tASC tCAH COLUMN ADDRESS ROW ADDRESS tCWL tRWL W OE VIH - tWP VIL - VIH VIL - DQ0 ~ DQ7 VIH - tOEH tOED tDS DATA-IN VIL - DQ8 ~ DQ15 VIH - tDH tDS tDH DATA-IN VIL - Don′t care Undefined KM416C254D, KM416V254D CMOS DRAM LOWER BYTE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS tRP VIH VIL - tRPC tCRP UCAS VIH VIL - tCSH tCRP LCAS tRCD tRSH tCRP tCAS VIH VIL - tRAD tASR A VIH VIL - tRAH tRAL tASC ROW ADDRESS tCAH COLUMN ADDRESS tCWL tRWL W OE tWP VIH VIL - VIH VIL - DQ0 ~ DQ7 VIH VIL - tOEH tOED tDS tDH DATA-IN DQ8 ~ DQ15 VIH VIL - Don′t care Undefined KM416C254D, KM416V254D CMOS DRAM UPPER BYTE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS VIL - tCSH tCRP UCAS tRP VIH - tRCD VIL - tCRP LCAS W OE tCRP VIH VIL - tRAD tASR A tCRP tRSH tCAS VIH - VIH VIL - tRAH tRAL tASC ROW ADDRESS tCAH COLUMN ADDRESS tCWL tRWL VIH - tWP VIL - VIH VIL - tOEH tOED DQ0 ~ DQ7 VIH VIL - DQ8 ~ DQ15 VIH VIL - tDS tDH DATA-IN Don′t care Undefined KM416C254D, KM416V254D CMOS DRAM WORD READ - MODIFY - WRITE CYCLE tRWC tRAS RAS UCAS LCAS tRP VIH VIL - tCRP tRCD tRSH tCAS tCRP tRCD tRSH VIH VIL - tCAS VIH VIL - tRAD tCSH tASR A VIH VIL - tRAH ROW ADDR. tASC tCAH COLUMN ADDRESS tAWD tRWL tCWD W OE tCWL VIH - tWP VIL - tRWD tOEA VIH VIL - tOLZ tCLZ tCAC tAA DQ0 ~ DQ7 VI/OH - tOED tOEZ tRAC VALID DATA-OUT VI/OL - tDS tDH VALID DATA-IN tOLZ tCLZ tCAC tAA DQ8 ~ DQ15 VI/OH VI/OL - tRAC tOED tOEZ VALID DATA-OUT tDS tDH VALID DATA-IN Don′t care Undefined KM416C254D, KM416V254D CMOS DRAM LOWER-BYTE READ - MODIFY - WRITE CYCLE tRWC tRAS RAS tRP VIH VIL - tRPC tCRP UCAS VIH VIL - tCRP LCAS tRCD tRSH VIH - tCAS VIL - tRAD tCSH tASR A VIH VIL - tRAH ROW ADDR. tASC tCAH COLUMN ADDRESS tAWD tRWL tCWD W OE tCWL VIH - tWP VIL - tRWD tOEA VIH VIL - tOLZ tCLZ tCAC tAA DQ0 ~ DQ7 VI/OH VI/OL DQ8 ~ DQ15 VOH VOL - tOED tOEZ tRAC VALID DATA-OUT tDS tDH VALID DATA-IN OPEN Don′t care Undefined KM416C254D, KM416V254D CMOS DRAM UPPER-BYTE READ - MODIFY - WRITE CYCLE tRWC tRAS RAS VIL - tCRP UCAS tRP VIH - tRCD tRSH VIH - tCAS VIL - tRPC tCRP LCAS VIH VIL - tRAD tCSH tASR A VIH VIL - tRAH ROW ADDR tASC tCAH COLUMN ADDRESS tAWD tRWL tCWD W OE tCWL VIH - tWP VIL - tRWD tOEA VIH VIL - DQ0 ~ DQ7 VOH - OPEN VOL - tOLZ tCLZ tCAC tAA DQ8 ~ DQ15 VI/OH VI/OL - tRAC tOED tOEZ VALID DATA-OUT tDS tDH VALID DATA-IN Don′t care Undefined KM416C254D, KM416V254D CMOS DRAM HYPER PAGE MODE WORD READ CYCLE tRASP RAS tRP VIH VIL - tCSH tCRP UCAS tRCD tCP tHPC tCP tCAS tCP tCAS tCAS VIL - tCP tRCD VIL - VIH VIL - tRAD tRAH tASC ROW ADDR tCP tCAS VIH - tASR A tHPC tCAS VIH - tCRP LCAS tRHCP tHPC tCAS tCAH tASC COLUMN ADDRESS tCAH tREZ tCP tCAS tASC COLUMN ADDRESS tCAH COLUMN ADDR tCAS tASC tCAH COLUMN ADDRESS tRAL tRCS W VIH VIL - tAA tAA tCPA tOCH tOEA VIH - tCHO tOEP tOEA VIL - tCAC DQ0 ~ DQ7 VOH - tCPA tCAC tAA tCAC tCPA tCAC OE tRRH tRCH tOEP tDOH tRAC VALID DATA-OUT VOL - tOEZ tOEZ tOEZ VALID VALID VALID VALID DATA-OUT DATA-OUT DATA-OUT DATA-OUT VALID VALID VALID VALID DATA-OUT DATA-OUT DATA-OUT DATA-OUT tOLZ tCLZ tCAC DQ8 ~ DQ15 VOH - tRAC tOEP tDOH VALID DATA-OUT VOL - tOEZ tOEZ tOLZ tCLZ Don′t care Undefined KM416C254D, KM416V254D CMOS DRAM HYPER PAGE MODE LOWER BYTE READ CYCLE tRP tRASP RAS VIH VIL - ¡ó tRPC tCRP UCAS VIH - tCSH VIL - tRHCP tHPC tCP tRCD LCAS tCP tCAS VIH - tCAS tHPC tREZ tCP tCAS tCAS tCAH tASC tCAH VIL - tASR A tHPC VIH VIL - tRAD tRAH tASC ROW ADDR tCAH COLUMN ADDRESS tASC tCAH tASC COLUMN ADDRESS COLUMN ADDR COLUMN ADDRESS tRAL tRCS W VIH VIL - tAA tCPA tAA OE tRRH tRCH tAA tCPA tCAC tOCH tOEA VIH - tCAC tRAC VOL - tOEP tDOH VALID DATA-OUT VOL - DQ8 ~ DQ15 VOH - tCHO tOEP tOEA VIL - DQ0 ~ DQ7 VOH - tCPA tCAC tAA tCAC tOEZ tOEZ tOEZ VALID VALID VALID VALID DATA-OUT DATA-OUT DATA-OUT DATA-OUT tOLZ tCLZ OPEN Don′t care Undefined KM416C254D, KM416V254D CMOS DRAM HYPER PAGE MODE UPPER BYTE READ CYCLE tRASP RAS tRP VIH VIL - ¡ó tCSH tCRP UCAS tRHCP tHPC tRCD tCP tCAS VIH - tHPC tHPC tCP tCAS tCP tRPC tCAS tCAS VIL - tCRP LCAS VIL - tASR A tRPC VIH - VIH VIL - tRAD tRAH tASC ROW ADDR. tCAH tASC tCAH tASC COLUMN ADDRESS COLUMN ADDRESS tCAH COLUMN ADDR. tASC tCAH tREZ COLUMN ADDRESS tRAL tRCS W VIH VIL - tAA tCPA tOCH tOEA VIH - tCHO tOEP tOEA VIL - DQ0 ~ DQ7 VOH - OPEN VOL - tCAC DQ8 ~ DQ15 VOH - tCPA tCAC tAA tCAC tAA tCPA tCAC OE tRRH tRCH tRAC tOEP tDOH VALID DATA-OUT VOL - tOEZ tOEZ tOEZ VALID VALID VALID VALID DATA-OUT DATA-OUT DATA-OUT DATA-OUT tOLZ tCLZ Don′t care Undefined KM416C254D, KM416V254D CMOS DRAM HYPER PAGE MODE WORD WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRASP RAS tRHCP VIL - ¡ó tHPC tCRP UCAS tHPC tCP tRCD VIH - tRSH tCP tCAS tCRP tCAS VIL - tCAS ¡ó tHPC tCRP LCAS tRP VIH - tHPC tCP tRCD VIH - tRSH tCP tCAS tCAS VIL - tCAS ¡ó tRAD tRAL tCSH tASR A VIH VIL - tRAH tASC tCAH OE tCAH tASC tCAH ¡ó ROW ADDR COLUMN ADDRESS COLUMN ADDRESS tWCS W tASC tWCH tWCS tWP VIH - ¡ó tWCH tWP COLUMN ADDRESS tWCS ¡ó tWCH tWP VIL - ¡ó VIH VIL - DQ0 ~ DQ7 VIH - ¡ó tDS VIL - tDS tDH tDS tDH ¡ó VALID DATA-IN VIL - DQ8 ~ DQ15 VIH - tDH tDS tDH VALID DATA-IN tDS ¡ó tDH VALID DATA-IN tDS tDH ¡ó VALID DATA-IN VALID DATA-IN ¡ó VALID DATA-IN Don′t care Undefined KM416C254D, KM416V254D CMOS DRAM HYPER PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRASP RAS tRP VIH - tRHCP VIL - ¡ó tRPC tCRP UCAS VIH VIL - tHPC tCRP LCAS tRCD tHPC tCP VIH - tRSH tCP tCAS tCAS VIL - tCAS ¡ó tRAD tRAL tCSH tASR A VIH VIL - tRAH tCAH tASC OE VIH - tASC tCAH tCAH ¡ó ROW ADDR COLUMN ADDRESS tWCS W tASC tWCH COLUMN ADDRESS tWCS tWP ¡ó tWCH tWP COLUMN ADDRESS tWCS ¡ó tWCH tWP VIL - ¡ó VIH VIL - DQ0 ~ DQ7 VIH VIL - ¡ó tDS tDH tDS tDH tDS tDH ¡ó VALID DATA-IN VALID DATA-IN ¡ó VALID DATA-IN DQ8 ~ DQ15 VIH VIL - Don′t care Undefined KM416C254D, KM416V254D CMOS DRAM HYPER PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRASP RAS tRHCP VIL - ¡ó tHPC tCRP UCAS tRP VIH - tRCD tHPC tCP VIH - tRSH tCP tCAS tCAS VIL - tCAS ¡ó tRPC tCRP LCAS VIH VIL - tRAD tRAL tCSH tASR A VIH VIL - tRAH tASC tCAH OE VIH - tCAH tASC tCAH ¡ó ROW ADDR COLUMN ADDRESS tWCS W tASC tWCH COLUMN ADDRESS tWCS tWP ¡ó tWCH tWP COLUMN ADDRESS tWCS ¡ó tWCH tWP VIL - ¡ó VIH VIL - ¡ó DQ0 ~ DQ7 VIH - ¡ó VIL - DQ8 ~ DQ15 VIH VIL - ¡ó tDS tDH tDS tDH tDS tDH ¡ó VALID DATA-IN VALID DATA-IN ¡ó VALID DATA-IN Don′t care Undefined KM416C254D, KM416V254D CMOS DRAM HYPER PAGE MODE WORD READ - MODIFY - WRITE CYCLE tRP tRASP RAS VIH - tCSH tCRP UCAS tRSH tRCD tCRP tCP VIH - tCAS tCAS VIL - tCRP LCAS tHPRWC VIL - tRCD tCRP tCP VIH - tCAS tCAS VIL - tRAD tRAH tASR A VIH VIL - tRAL tCAH tASC tASC ROW ADDR COL. ADDR COL. ADDR tRCS W tCAH tCWL VIH - tWP VIL - tWP tCWD tCWD tAWD tRWD OE tRWL tCWL tRCS VIH - tAWD tCPWD tOEA tOEA VIL - tOED tOED tCAC tAA DQ0 ~ DQ7 VI/OH VI/OL - tDH tCAC tAA tDS tOEZ tDH tRAC tCLZ tCLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT tOED tCAC tAA DQ8 ~ DQ15 VI/OH VI/OL - tDS tOEZ tDH tOEZ tOED tCAC tAA tDS VALID DATA-IN tDH tOEZ tDS tRAC tCLZ tCLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN Don′t care Undefined KM416C254D, KM416V254D CMOS DRAM HYPER PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE tRP tRASP RAS VIH - tCSH tHPRWC VIL - tRPC tCRP UCAS VIH VIL - tCRP LCAS tRSH tCP tRCD VIH - tCAS tCAS VIL - tRAD tRAH tASR A VIH VIL - ROW ADDR tCAH tASC tCAH tASC COL. ADDR tRWL tCWL tRCS tCWL VIH - tWP VIL - tWP tCWD tCWD tAWD tCPWD tAWD tRWD OE tRAL COL. ADDR tRCS W tCRP VIH - tOEA tOEA VIL - tOED tCAC tAA DQ0 ~ DQ7 VI/OH VI/OL - tOEZ tRAC VI/OL - tDH tAA tDH tDS tDS tCLZ tOEZ tCLZ tOLZ DQ8 ~ DQ15 VI/OH - tOED tCAC VALID DATA-OUT VALID DATA-IN tOLZ VALID DATA-OUT VALID DATA-IN OPEN Don′t care Undefined KM416C254D, KM416V254D CMOS DRAM HYPER PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE tRP tRASP RAS VIH - tCSH tCRP UCAS tHPRWC VIL - tRSH tCP tRCD VIH - tCAS tCRP tCAS VIL - tRPC tCRP LCAS VIH VIL - tRAD tRAH tASR A VIH VIL - ROW ADDR tCAH tASC COL. ADDR tRWL tCWL tRCS tCWL VIH - tWP VIL - tWP tCWD tCWD tAWD tAWD tRWD OE tRAL COL. ADDR tRCS W tCAH tASC VIH - tCPWD tOEA tOEA VIL - DQ0 ~ DQ7 VI/OH - OPEN VI/OL - tOLZ tOLZ tOED tAA DQ8 ~ DQ15 VI/OH VI/OL - tRAC tOED tCAC tCAC tOEZ tDS tCLZ tDH tAA tDH tDS tOEZ tCLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN Don′t care Undefined KM416C254D, KM416V254D CMOS DRAM HYPER PAGE READ AND WRITE MIXED CYCLE tRP tRASP RAS VIH - READ(tCAC ) READ(tCPA ) tHPC VIH VIL - tCP tCP tCAS tRCD tCAS tHPC tHPC VIH - tCP VIL - tASR A VIH VIL - tRAH tASC ROW ADDR tCAH COLUMN ADDRESS tCAH tASC tCP tASC COLUMN ADDRESS tCAH COL. ADDR tHPC tCAS tCAS tCAS tCAS tRAD tCAS tCAS tCP LCAS tRHCP tHPC tHPC tCP UCAS READ(tAA ) WRITE VIL - tASC tCAH COL. ADDR tRAL tRCS W tRCH tRCS tRCH tWCH tRCH tWCS VIH VIL - tWPE tCLZ tCPA OE tWED VIH VIL - DQ0 ~ DQ7 VI/OH - tOEA tCAC tAA VI/OL - tWEZ tDH tDS tAA tREZ tRAC VALID DATA-OUT VI/OL - DQ8 ~ DQ15 VI/OH - tWEZ tOEA tCAC tAA tWEZ VALID DATA-OUT tWEZ VALID DATA-IN tDH tDS VALID DATA-OUT tAA tREZ tRAC VALID DATA-OUT VALID DATA-OUT VALID DATA-IN VALID DATA-OUT Don′t care Undefined KM416C254D, KM416V254D CMOS DRAM RAS - ONLY REFRESH CYCLE NOTE : W, OE , DIN = Don′t care DOUT = OPEN tRC VIH - RAS tRP tRAS VIL - tRPC tCRP VIH - UCAS VIL - tCRP VIH - LCAS VIL - tASR VIH - A VIL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE, A = Don′t care tRC tRP VIH - RAS VIL - tRP tRAS tRPC tRPC tCP UCAS tCSR VIH - tCHR VIL - tCP LCAS tCSR VIH - tCHR VIL - DQ0 ~ DQ7 VOH VOL DQ8 ~ DQ15 VOH VOL - tCEZ OPEN OPEN Don′t care Undefined KM416C254D, KM416V254D CMOS DRAM HIDDEN REFRESH CYCLE ( READ ) tRC RAS tRAS VIH - tRSH tCHR tRCD tRSH tCHR VIL - VIH VIL - tRAD tASR A tRCD VIH - tCRP LCAS VIH VIL - tRAH tASC tCAH ROW ADDRESS COLUMN ADDRESS tWRH tRCS W tRP tRAS VIL - tCRP UCAS tRC tRP VIH VIL - tRAL tAA OE VIH - tOEA VIL - tCEZ tREZ tCAC tCLZ DQ0 ~ DQ7 VOH VOL - DQ8 ~ DQ15 VOH VOL - tRAC tWEZ tOLZ tOEZ OPEN DATA-OUT OPEN DATA-IN DATA-OUT Don′t care Undefined KM416C254D, KM416V254D CMOS DRAM HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN tRC RAS tRAS VIH - tRSH tCHR tRCD tRSH tCHR VIL - VIH VIL - tRAD tASR A tRCD VIH - tCRP LCAS tRP tRAS VIL - tCRP UCAS tRC tRP VIH VIL - tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tWRH tWRP tWCS W OE VIH - tWCH tWP VIL - VIH VIL - tDS DQ0 ~ DQ7 VIH - DATA-IN VIL - tDS DQ8 ~ DQ15 VIH VIL - tDH tDH DATA-IN Don′t care Undefined KM416C254D, KM416V254D CMOS DRAM CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE VIH - RAS tRP tRAS VIL VIH - UCAS tCSR tCPT tRSH tCAS tCPT tRSH tCAS tCHR VIL VIH - LCAS tCSR tCHR VIL - tRAL tASC VIH - A COLUMN ADDRESS VIL - READ CYCLE tWRP tWRH tRRH tAA tRCS tRCH tCAC VIH - W VIL - OE VIH VIL - tOEA tCLZ VOH - DQ0 ~ DQ15 tCAH DATA-OUT VOL - WRITE CYCLE W tREZ tOEZ tCEZ tWRP tRWL tWRH VIH - tWEZ tCWL tWCH tWCS VIL - tWP OE VIH VIL - tDS DQ0 ~ DQ15 tDH VIH DATA-IN VIL - READ-MODIFY-WRITE tWRP W tWRH tAWD tRCS tCWL tCWD VIH - tRWL tWP tCAC VIL - tAA tOEA OE VIH - tOED VIL - tCLZ DQ0 ~ DQ15 tOEZ tDH tDS VI/OH VI/OL VALID DATA-OUT VALID DATA-IN Don′t care Undefined KM416C254D, KM416V254D CMOS DRAM CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE , A = Don′t care tRP tRASS tRPS VIH - RAS VIL - tRPC tCP UCAS VIH - tCSR tCHS tCSR tCHS VIL - tCP LCAS tRPC VIH VIL - DQ0 ~ DQ7 VOH VOL DQ8 ~ DQ15 VOH VOL - tCEZ OPEN OPEN Don′t care Undefined KM416C254D, KM416V254D CMOS DRAM PACKAGE DIMENSION 40 SOJ 400mil Units : Inches (millimeters) 0.360 (9.15) 0.380 (9.65) 0.400 (10.16) 0.435 (11.06) 0.445 (11.30) #40 0.006 (0.15) 0.012 (0.30) #1 0.148 (3.76) MAX 0.027 (0.69) MIN 1.041 (26.44) MAX 1.020 (25.92) 1.030 (26.16) 0.0375 (0.95) 0.050 (1.27) 0.026 (0.66) 0.032 (0.81) 0.015 (0.38) 0.021 (0.53) 44(40) TSOP(II) 400mil 0.400 (10.16) 0.455 (11.56) 0.471 (11.96) Units : Inches (millimeters) 0.004 (0.10) 0.010 (0.25) 0.741 (18.81) MAX 0.721 (18.31) 0.729 (18.51) 0.032 (0.805) 0.0315 (0.80) 0.047 (1.20) MAX 0.002 (0.05) MIN 0.010 (0.25) 0.018 (0.45) 0.010 (0.25) TYP 0.018 (0.45) 0.030 (0.75) 0~8 O