SAMSUNG KM44L32031BT

128Mb DDR SDRAM
Target
DDR SDRAM Specification
Version 0.61
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REV. 0.61 August 9. '99
128Mb DDR SDRAM
Target
Revision History
Version 0 (May, 1998)
- First version for internal review
Version 0.1(June, 1998)
- Added x4 organization
Version 0.2(Sep,1998)
1. Added "Issue prcharge command for all banks of the device" as the fourth step of power-up squence.
2. In power down mode timing diagram, NOP condition is added to precharge power down exit.
Version 0.3(Dec,1998)
- Added QFC Function.
- Added DC current value
- Reduce I/O capacitance values
Version 0.4(Feb,1999)
-Added DDR SDRAM history for reference(refer to the following page)
-Added low power version DC spec
Version 0.5(Apr,1999)
-Revised following first showing for JEDEC standard
-Added DC target current based on new DC test condition
Version 0.6(July 1,1999)
1.Modified binning policy
From
To
-Z (133Mhz)
-Z (133Mhz/266Mbps@CL=2)
-8 (125Mhz)
-Y (133Mhz/266Mbps@CL=2.5)
-0 (100Mhz)
-0 (100Mhz/200Mbps@CL=2)
2.Modified the following AC spec values
From.
-Z
-0
-Z
-Y
-0
tAC
+/- 0.75ns
+/- 1ns
+/- 0.75ns
+/- 0.75ns
+/- 0.8ns
tDQSCK
+/- 0.75ns
+/- 1ns
+/- 0.75ns
+/- 0.75ns
+/- 0.8ns
tDQSQ
+/- 0.5ns
+/- 0.75ns
+/- 0.5ns
+/- 0.5ns
+/- 0.6ns
tDS/tDH
0.5 ns
0.75 ns
0.5 ns
0.5 ns
0.6 ns
tCDLR*1
2.5tCK-tDQSS
2.5tCK-tDQSS
1tCK
1tCK
1tCK
tPRE
*1
tRPST*1
tHZQ
*1
To.
*1
1tCK +/- 0.75ns
1tCK +/- 1ns
0.9/1.1 tCK
0.9/1.1 tCK
0.9/1.1 tCK
tCK/2 +/- 0.75ns
tCK/2 +/- 1ns
0.4/0.6 tCK
0.4/0.6 tCK
0.4/0.6 tCK
tCK/2 +/- 0.75ns
tCK/2 +/- 1ns
+/- 0.75ns
+/- 0.75ns
+/-0.8ns
: Changed description method for the same functionality. This means no difference from the previous version.
3.Changed the following AC parameter symbol
From.
To.
tDQCK
tAC
Output data access time from CK/CK
Version 0.61(August 9,1999)
- Changed the some values of "write with auto precharge" table for different bank in page 30.
Asserted
command
For Different Bank
3
4
Old
New
Old
New
Read
Legal
Illegal
Legal
Illegal
Read + AP*1
Legal
Illegal
Legal
Illegal
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128Mb DDR SDRAM
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Revision History
-This revision history is for 64Mb and only for reference in other density.
Version 0.5 (JUN, 1997)
- First version for external release
- Center aligned DQ on reads and writes, 3.3V Vdd/Vddq, LVTTL for command and SSTL for DQ, DQS, CK and DM.
Version 0.6 (SEP. 1997)
- Changed to Edge alignedDQ on reads
- Add detailed discription for each functionality
Version 0.7 (JAN. 1998)
- Power supply: 3.3V +10%,-5% power supply for device operation (Vdd)
2.5V Power supply for I/O interface (Vddq)
- Interface: Add SSTL_2 for CK/DM (class I), DQ/DQS(class II) for KM416H431T.
* Put two part numbers, KM416H430T and KM416H431T.
- Clock input: Change to differential clock from single ended clock.
* Use CK, CK instead of CLK.
- Package: Change to 66pin TSOP-II, instead of 54pin TSOP-II
- tDQSS: Change to 0.75 ~ 1.25 tCK form 3ns ~ 1 tCK.
Add tSDQS(DQS-in setup time)
- In page 13, "DM can be ~" is modified to "DM must be ~".
- Tighten AC specs Change CK/CK hign/low level width from 0.4(min)/0.6(max)tCK to 0.45(min)/0.55(max)tCK.
-> Better input clock duty ratio from differential clock.
Version 0.8 (FEB. 1998)
- Correct pin rotation on pin 48 and 49 from 48-Vref, 49-Vss to 48-Vss, 49-Vref.
Version 0.9 (MAR. 1998)
- Change power-up sequence
. Add EMRS for DLL enable/disable
. Change DLL reset pin from A9 to A8 on MRS.
- Change speed range
. Add 133Mhz (266Mbps/pin), remove -12 (83Mhz)
- Change output load circuit
- Change input capacitance
- Add a comment on read interrupting write timing: Read command interrupting write can not be
issued at the next clock edge of write command.
- Modify the simplified state diagram on page 24.
Version 0.91 (May, 1998)
- Changed part number from KM416H430T/KM416H431T to KM416H4030T/KM416H4031T
- Added the 66pin package dimension on page 30.
- Changed Output Load Circuit 2 in page 29
- Removed CL=1.5
- Corrected typos
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Contents
Revision History
2
DDR SDRAM Ordering Information
1. Key Features
1.1 Features
1.2 Operating Frequencies
1.3 Device Information by organization
2. Package Pinout & Dimension
2.1 Package Pintout
2.2 Input/Output Function Description
2.3 66 Pin TSOP(II)/MS-024FC Package Physical Dimension
8
9
9
9
9
10
10
11
12
3. Functional Description
3.1 Simplified State Diagram
3.2 Basic Functionality
13
13
14
14
15
15
17
18
18
19
19
19
20
20
21
22
22
23
24
3.2.1 Power-Up Sequence
3.2.2 Mode Register Definition
3.2.2.1 Mode Register Set(MRS)
3.2.2.2 Extended Mode Register Set(EMRS)
3.2.3 Precharge
3.2.4 No Operation(NOP) & Device Deselect
3.2.5 Row Active
3.2.6 Read Bank
3.2.7 Write Bank
3.3 Essential Functionality for DDR SDRAM
3.3.1 Burst Read Operation
3.3.2 Burst Write Operation
3.3.3 Read Interrupted by a Read
3.3.4 Read Interrupted by a Write & Burst Stop
3.3.5 Read Interrupted by a Precharge
3.3.6 Write Interrupted by a Write
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3.3.7 Write Interrupted by a Read & DM
25
3.3.8 Write Interrupted by a Precharge & DM
26
3.3.9 Burst Stop
27
3.3.10 DM masking
28
3.3.11 Read With Auto Precharge
29
3.3.12 Write With Auto Precharge
30
3.3.13 Auto Refresh & Self Refresh
31
3.3.14 Power Down
32
4. Command Truth Table
33
5. Functional Truth Table
34
6. Absolute Maximum Rating
39
7. DC Operating Conditions & Specifications
39
7.1 DC Operating Conditions
39
7.2 DC Specifications
40
8. AC Operating Conditions & Timming Specification
41
8.1 AC Operating Conditions
41
8.2 AC Timming Parameters & Specification
42
9. AC Operating Test Conditions
44
10. Input/Output Capacitance
44
11. IBIS: I/V Characteristics for Input and Output Buffers
45
11.1 Normal strength driver
45
11.2 Half strength driver( will be included in the future)
47
12. QFC function
48
QFC definition
48
QFC timming on Read Operation
48
QFC timming on Write operation with tDQSSmax
49
QFC timming on Write operation with tDQSSmin
49
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List of tables
Table 1 : Operating frequency and DLL jitter
Table 2. : Column address configurtion
Table 3 : Input/Output function description
Table 4 : Burst address ordering for burst length
Table 5 : Bank selection for precharge by bank address bits
Table 6 : Operating description when new command asserted while
read with auto precharge is issued
Table 7 : Operating description when new command asserted while
write with auto precharge is issued
Table 8 : Command truth table
Table 9-1 : Functional truth table
Table 9-2 : Functional truth table (contiued)
Table 9-3 : Functional truth table (contiued)
Table 9-4 : Functional truth table (contiued)
Table 9-5 : Functional truth table (cotinued)
Table 10 : Absolute maximum raings
Table 11 : DC operating condtion
Table 12 : DC specification
Table 13 : AC operating condition
Table 14 : AC timing parameters and specifications
Table 15 : AC operating test conditions
Table 16 : Input/Output capacitance
Table 17 : Pull down and pull up current values
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REV. 0.61 August 9. '99
128Mb DDR SDRAM
Target
List of figures
Figure 1 : 128Mb Package Pinout
Figure 2 : Package dimension
Figure 3 :State digram
Figure 4 : Power up and initialization sequence
Figure 5 : Mode register set
Figure 6 : Mode register set sequence
Figure 7 : Extend mode register set
Figure 8 : Bank activation command cycle timing
Figure 9 : Burst read operation timing
Figure 10 : Burst write operation timing
Figure 11 : Read interrupted by a read timing
Figure 12 : Read interrupted by a write and burst stop timing
Figure 13 : Read interrupted by a precharge timing
Figure 14 : Write interrupted by a write timing
Figure 15 : Write interrupted by a read and DM timing
Figure 16 : Write interrupted by a precharge and DM timing
Figure 17 : Burst stop timing
Figure 18 : DM masking timing
Figure 19 : Read with auto precharge timing
Figure 20 : Write with auto precharge timing
Figure 21 : Auto refresh timing
Figure 22 : Self refresh timing
Figure 23 : Power down entry and exit timing
Figure 24 : Output Load Circuit (SSTL_2)
Figure 25 : I / V characteristics for input/output buffers:
pull-up(above) and pull-down(below)
Figure 26 : QFC timing on read operation
Figure 27 : QFC timing on write operation with tDQSSmax
Figure 28 : QFC timing on write operation with tDQSSmin
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12
13
14
15
16
17
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22
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128Mb DDR SDRAM
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DDR SDRAM ORDERING INFORMATION
KM 4 XX L XX X X X X X - X X
1. SAMSUNG Memory
12. Speed
2. Device
11. Power
10. Package Type
3. Organization
9. Revision
4. Product & Voltage(VDD)
8. Interface & Voltage(VDDQ)
5. Depth
7. Number of Bank
6. Refresh
1. SAMSUNG Memory
2. Device
•4
7. Number of Bank
DRAM
3. Organization
• 4
x4
• 8
x8
• 16
x16
• 32
x32
•3
4 Banks
•4
8 Banks
8. Interface & Voltage(VDDQ)
4. Product & Voltage(VDD)
•0
Mixed Interface(LVTTL & SSTL_3 & 3.3V V DDQ)
•1
SSTL_2(2.5V VDDQ)
9. Revision
•H
DDR SDRAM(3.3V V DD)
• Blank
1st Gen.
•L
DDR SDRAM(2.5V V DD)
•A
2nd Gen.
•B
3rd Gen.
•C
4th Gen.
5. Depth
•
4
4M
•
8
8M
• 16
16M
• 32
32M
•T
66pin TSOP-II
• 64
64M
•B
BGA
• 12
128M
•C
u - BGA(CSP)
• 25
256M
• 51
512M
• 1G
1G
• 2G
2G
• 4G
4G
6. Refresh
10. Package Type
11. Power
•G
Auto & Self Refresh
•F
Auto & Self Refresh with Low Power
12. Speed
• Z
7.5ns, 133MHz@CL2 (266Mbps/pin)
•0
64m/4K(15.6us)
• Y
7.5ns, [email protected](266Mbps/pin)
•1
32m/2K(15.6us)
• 0
10ns, 100MHz @CL2(200Mbps/pin)
•2
128m/8K(15.6us)
•3
64m/8K(7.8us)
•4
128m/16K(7.8us)
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1. Key Features
1.1 Features
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM/DM for write masking only
• Auto & Self refresh
• 15.6us refresh interval
• Maximum burst refresh cycle : 8
• 66pin TSOP II package
1.2 Operating Frequencies
Maximum Operation
Frequency
PC266A(-Z)
PC266B(-Y)
PC200(-0)
Speed
133MHz@CL2
[email protected]
100MHz@CL2
DLL jitter
±0.75ns
±0.75ns
±0.8ns
*CL : Cas Latency
Table 1. Operating frequency and DLL jitter
1.3 Device information by Organization
Density
128Mb
Part No.
KM44L32031BT-G(F)Z/Y/0
KM48L16031BT-G(F)Z/Y/0
KM416L8031BT-G(F)Z/Y/0
Operating Freq.
Interface
Package
133/133/100MHz
SSTL_2
66pin
TSOP II
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1. Package Pinout & Dimension
2.1 Package Pinout
8Mb x 16
16Mb x 8
32Mb x 4
VDD
VDD
VDD
1
66
VSS
VSS
VSS
DQ 0
DQ0
NC
2
65
NC
DQ7
DQ15
VDDQ
VDDQ
VDDQ
3
64
VSSQ
VSSQ
VSSQ
DQ 1
NC
NC
4
63
NC
NC
DQ14
DQ 2
DQ1
DQ0
5
62
DQ3
DQ6
DQ13
VSSQ
VSSQ
VSSQ
6
61
VDDQ
VDDQ
VDDQ
DQ 3
NC
NC
7
60
NC
NC
DQ12
DQ 4
DQ2
NC
8
59
NC
DQ5
DQ11
VDDQ
VDDQ
VDDQ
9
58
VSSQ
VSSQ
VSSQ
DQ 5
NC
NC
10
57
NC
NC
DQ10
DQ 6
DQ3
DQ1
11
56
DQ2
DQ4
DQ9
VSSQ
VSSQ
VSSQ
12
55
VDDQ
VDDQ
VDDQ
DQ 7
NC
NC
13
54
NC
NC
DQ8
NC
NC
NC
14
53
NC
NC
NC
VDDQ
VDDQ
VDDQ
15
52
VSSQ
VSSQ
VSSQ
LDQS
NC
NC
16
51
DQS
DQS
UDQS
NC
NC
NC
17
50
NC
NC
NC
VDD
VDD
VDD
18
49
VREF
VREF
VREF
QFC/NC QFC/NC
19
48
VSS
VSS
VSS
47
DM
DM
UDM
46
CK
CK
CK
QFC/NC
66 PIN TSOP(II)
(400mil x 875mil)
(0.65 mm PIN PITCH)
Bank Address
BA0-BA1
Row Address
A0-A11
Auto Precharge
A10
LDM
NC
NC
20
WE
WE
WE
21
CAS
CAS
CAS
22
45
CK
CK
CK
RAS
RAS
RAS
23
44
CKE
CKE
CKE
43
NC
NC
NC
42
NC
NC
NC
41
A11
A11
A11
CS
CS
CS
24
NC
NC
NC
25
BA0
BA0
BA0
26
MS-024FC
BA1
BA1
BA1
27
40
A9
A9
A9
AP/A 10
AP/A10
AP/A10
28
39
A8
A8
A8
A0
A0
A0
29
38
A7
A7
A7
A1
A1
A1
30
37
A6
A6
A6
A2
A2
A2
31
36
A5
A5
A5
A3
A3
A3
32
35
A4
A4
A4
VDD
VDD
VDD
33
34
VSS
VSS
VSS
FIgure 1. 128Mb package Pinout
Organization
Column Address
32Mx4
A0-A9, A11
16Mx8
A0-A9
8Mx16
A0-A8
DM is internally loaded to match DQ and DQS identically.
Table 2. Column address configuration
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2.2 Input/Output Function Description
SYMBOL
TYPE
DESCRIPTION
CK, CK
Input
Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the positive edge of CK/negative edge of CK. Output (read) data is referenced to both
edges of CK. Internal clock signals are derived from CK/CK.
CKE
Input
Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN
(row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs,
which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled
during power-down and self refresh modes, providing low standby power. CKE will recognize
an LVCMOS LOW level prior to VREF being stable on power-up.
CS
Input
Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command
decoder. All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple banks CS is considered part of the command code.
RAS, CAS, WE
Input
Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.
LDM,(U)DM
Input
Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH along with that input data during a WRITE access. DM is sampled on both
edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons to the data on
DQ8-DQ15.
BA0, BA1
Input
Bank Addres Inputs : BA0 and BA1 define to which bank ACTIVE, READ, WRITE or PRECHARGE command is being applied.
A [n : 0]
Input
Address Inputs : Provide the row address for ACTIVE commands, the column address and
AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If
only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also
provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which
mode register is loaded during the MODE REGISTER SET command (MRS or EMRS).
DQ
I/O
Data Input/Output : Data bus
LDQS,(U)DQS
I/O
Data Strobe : Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on
DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15.
QFC
Output
FET Control : Optional. Output during every Read and Write access. Can be used to control
isolation switches on modules.
NC
-
No Connect : No internal electrical connection is present.
VDDQ
Supply
DQ Power Supply : +2.5V ± 0.2V.
VSSQ
Supply
DQ Ground.
VDD
Supply
Power Supply : One of +3.3V ± 0.3V or +2.5V ± 0.2V (device specific).
VSS
Supply
Ground.
VREF
Input
SSTL_2 reference voltage.
Table 3. Input/Output Function Description
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2.3 66 Pin TSOP(II)/MS-024FC Package Physical Dimension
0.30±0.08
(10×)
NOTE
1. (
) IS REFERENCE
2. [
] IS ASS’Y OUT QUALITY
(10.76)
0.10 MAX
[
0.075 MAX ]
(R
0.2
5
0.65TYP
0.65±0.08
0.05 MIN
(0.71)
(R
0.
15
)
(0.50)
)
(4×
)
1.20MAX
(10×)
)
1.00±0.10
0.210±0.05
0.665±0.05
22.22±0.10
(R
0.1
5
0.125 +0.075
-0.035
(R
0.
25
)
(0.80)
#33
(1.50)
(10×)
0.45~0.75
(1.50)
(10×)
#1
11.76±0.20
(0.80)
#34
10.16±0.10
#66
(0.50)
Units : Millimeters
0.25TYP
0×~8×
Figure 2. Package dimension
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3. Functional Description
3.1 Simplified State Diagram
SELF
REFRESH
REFS
REFSX
MRS
MODE
REGISTER
SET
REFA
IDLE
AUTO
REFRESH
CKEL
CKEH
POWER
DOWN
ACT
POWER
DOWN
CKEL
CKEH
ROW
ACTIVE
BURST STOP
WRITE
READ
WRITEA
READA
READ
WRITEA
WRITE
WRITEA
READ
READA
READA
PRE
WRITEA
READA
PRE
POWER
APPLIED
POWER
ON
PRE
PRE
PRE
CHARGE
Automatic Sequence
Command Sequence
WRITEA : Write with autoprecharge
READA : Read with autoprecharge
Figure 3. State diagram
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3.2 Basic Functionality
3.2.1 Power-Up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE at a low state(all other inputs may be undefined.)
- Apply VDD before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as VTT & Vref.
2. Start clock and maintain stable condition for a minimum of 200us.
3. The minimum of 200us after stable power and clock(CK, CK), apply NOP & take CKE high.
4. Issue precharge commands for all banks of the device.
*1 5. Issue EMRS to enable DLL.(To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and "Low"
to all of the rest address pins, A1~A11 and BA1)
*1 6. Issue a mode register set command for "DLL reset". The additional 200 cycles of clock input is required to
lock the DLL.
(To issue DLL reset command, provide "High" to A8 and "Low" to BA0)
*2 7. Issue precharge commands for all banks of the device.
8. Issue 2 or more auto-refresh commands.
9. Issue a mode register set command with low to A8 to initialize device operation.
*1 Every "DLL enable" command resets DLL. Therefore sequence 6 can be skipped during power up.
Instead of it, the additional 200 cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6 & 7 is regardless of the order.
Power up & Initialization Sequence
3
4
5
6
7
8
9
10
precharge
ALL Banks
tRP
2 Clock min.
EMRS
2 Clock min.
MRS
DLL Reset
precharge
ALL Banks
12
13
1st Auto
Refresh
14
15
16
17
tRFC
tRFC
tRP
∼
Command
11
∼ ∼ ∼
2
2nd Auto
Refresh
min.200 Cycle
18
19
2 Clock min.
Mode
Register Set
Any
Command
∼
1
∼ ∼
∼ ∼
0
CK
CK
Figure 4. Power up and initialization sequence
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3.2.2 Mode Register Definition
3.2.2.1 Mode Register Set(MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs
CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make
DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined,
therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation. The mode
register is written by asserting low on CS, RAS, CAS, WE and BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The states of address pins A0 ~ A11 in
the same cycle as CS, RAS, CAS, WE and BA0 going low are written in the mode register. Two clock cycles
are requested to complete the write operation in the mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in
the idle state. The mode register is divided into various fields depending on functionality. The burst length uses
A0 ~ A2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used
for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer to the table for
specific codes for various burst lengths, addressing modes and CAS latencies.
BA1
BA0
RFU
0
A11
A10
A9
RFU
A8
A8
A7
DLL
TM
DLL Reset
A6
A5
A4
CAS Latency
A3
A2
BT
A1
A0
Burst Length
A7
mode
A3
Burst Type
0
No
0
Normal
0
Sequential
1
Yes
1
Test
1
Interleave
Address Bus
Mode Register
Burst Length
CAS Latency
BA0
An ~ A0
0
(Existing)MRS Cycle
1
Extended Funtions(EMRS)
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
A2
A1
A0
Reserved
0
0
Reserved
0
0
0
2
0
1
Reserved
0
0
Reserved
1
0
1
1
1
0
1
1
1
A6
A5
A4
Latency
0
0
0
0
0
1
0
1
0
1
1
Latency
Sequential
Interleave
0
Reserve
Reserve
1
2
2
1
0
4
4
0
1
1
8
8
1
0
0
Reserve
Reserve
Reserved
1
0
1
Reserve
Reserve
2.5
1
1
0
Reserve
Reserve
Reserved
1
1
1
Reserve
Reserve
Figure 5. Mode Register Set
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Burst Address Ordering for Burst Length
Burst
Length
Starting
Address(A2, A1, A0)
2
4
8
Sequential Mode
Interleave Mode
xx0
0, 1
0, 1
xx1
1, 0
1, 0
x00
0, 1, 2, 3
0, 1, 2, 3
x01
1, 2, 3, 0
1, 0, 3, 2
x10
2, 3, 0, 1
2, 3, 0, 1
x11
3, 0, 1, 2
3, 2, 1, 0
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
011
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
111
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
Table 4. Burst address ordering for burst length
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and
upon returing to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon
exiting Self Refresh Mode, the DLL is enabled automatically). Any time the DLL is enabled, 200 clock cycles
must occur before a READ command can be issued.
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II. Some vendors might also support
a weak driver strength option, intended for lighter load and/or point-to-point environments. I-V curves for the
normal drive strength and weak drive strength will be included in a future revision of this document.
Mode Register Set
0
1
2
3
4
5
6
7
8
CK
CK
*1
Mode
Register Set
Precharge
All Banks
Command
tCK
tRP*2
Any
Command
2 Clock min.
*1 : MRS can be issued only at all bank precharge state.
*2 : Minimum tRP is required to issue MRS command.
Figure 6. Mode Register Set sequence
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3.2.2.2 Extended Mode Register Set(EMRS)
The extended mode register stores the data for enabling or disabling DLL, QFC and selecting output driver
size. The default value of the extended mode register is not defined, therefore the extened mode register must
be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low
on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already
high prior to writing into the extended mode register). The state of address pins A0 ~ A11 and BA1 in the
same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. Two clock cycles
are required to complete the write operation in the extended mode register. The mode register contents can
be changed using the same command and clock cycle requirements during operation as long as all banks are
in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address
pins except A0 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.
BA1
BA0
RFU
1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
QFC D.I.C DLL
RFU : Must be set "0"
Address Bus
Extended Mode Register
Output Driver Impedence Control
A0
DLL Enable
0
Normal
0
Enable
1
Weak
1
Disable
An ~ A0
0
(Existing)MRS Cycle
1
Extended Funtions(EMRS)
QFC control
0
1
Disable(Default)
Enable
Figure 7. Extend Mode Register set
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3.2.3 Precharge
The precharge command is used to precharge or close a bank that has been activated. The precharge command is issued when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The precharge
command can be used to precharge each bank respectively or all banks simultaneously. The bank select
addresses(BA0, BA1) are used to define which bank is precharged when the command is initiated. For write
cycle, tWR(min.) must be satisfied until the precharge command can be issued. After tRP from the precharge,
an active command to the same bank can be initiated.
Bank Selection for Precharge by Bank address bits
A10/AP
BA1
BA0
Precharge
0
0
0
Bank A Only
0
0
1
Bank B Only
0
1
0
Bank C Only
0
1
1
Bank D Only
1
X
X
All Banks
Table 5. Bank selection for precharge by Bank address bits
3.2.4 No Operation(NOP) & Device Deselect
The device should be deselected by deactivating the CS signal. In this mode DDR SDRAM should ignore
all the control inputs. The DDR SDRAMs are put in NOP mode when CS is active and by deactivating RAS,
CAS and WE. For both Deselect and NOP the device should finish the current operation when this command is issued.
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3.2.5 Row Active
The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising
edge of the clock(CK). The DDR SDRAM has four independent banks, so two Bank Select addresses(BA0,
BA1) are required. The Bank Activation command must be applied before any Read or Write operation is executed. The delay from the Bank Activation command to the first read or write command must meet or exceed
the minimum of RAS to CAS delay time(tRCD min). Once a bank has been activated, it must be precharged
before another Bank Activation command can be applied to the same bank. The minimum time interval
between interleaved Bank Activation commands(Bank A to Bank B and vice versa) is the Bank to Bank delay
time(tRRD min).
Bank Activation Command Cycle (CAS Latency = 2)
0
1
Tn
2
Tn+1
Tn+2
CK
CK
Address
Bank A
Row Addr.
Bank A
Col. Addr.
Bank B
Row Addr.
RAS-CAS delay(tRCD )
Command
Bank A
Activate
NOP
Bank A
Row. Addr.
RAS-RAS delay time( tRRD )
Write A
with Auto
Precharge
Bank B
Activate
NOP
Bank A
Activate
: Don′t care
ROW Cycle Time(t RC)
Figure 8. Bank activation command cycle timing
3.2.6 Read Bank
This command is used after the row activate command to initiate the burst read of data. The read command
is initiated by activating RAS, CS, CAS, and deasserting WE at the same clock sampling(rising) edge as
described in the command truth table. The length of the burst and the CAS latency time will be determined by
the values programmed during the MRS command.
3.2.7 Write Bank
This command is used after the row activate command to initiate the burst write of data. The write command is initiated by activating RAS, CS, CAS, and WE at the same clock sampling(rising) edge as described in
the command truth table. The length of the burst will be determined by the values programmed during the
MRS command.
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3.3 Essential Functionality for DDR SDRAM
The essential functionality that is required for the DDR SDRAM device is described in this chapter
3.3.1 Burst Read Operation
Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read
command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the
clock(CK) after tRCD from the bank activation. The address inputs (A0~A9) determine the starting address for
the Burst. The Mode Register sets type of burst(Sequential or interleave) and burst length(2, 4, 8). The first
output data is available after the CAS Latency from the READ command, and the consecutive data are presented on the falling and rising edge of Data Strobe(DQS) adopted by DDR SDRAM until the burst length is
completed.
< Burst Length=4, CAS Latency= 2, 2.5 >
0
1
2
3
4
5
6
7
8
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK
CK
Command
READ A
DQS
NOP
tRPRE
tRPST
CAS Latency=2
DQ ′s
Dout 0 Dout 1 Dout 2 Dout 3
DQS
CAS Latency=2.5
DQ ′s
Dout 0 Dout 1 Dout 2 Dout 3
Figure 9. Burst read operation timing
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3.3.2 Burst Write Operation
The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising
edge of the clock(CK). The address inputs determine the starting column address. There is no write latency
relative to DQS required for burst write cycle. The first data of a burst write cycle must be applied on the DQ
pins tDS(Data-in setup time) prior to data strobe edge enabled after tDQSS from the rising edge of the
clock(CK) that the write command is issued. The remaining data inputs must be supplied on each subsequent
falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any
additional data supplied to the DQ pins will be ignored.
< Burst Length=4 >
0
1
2
3
4
5
6
7
8
NOP
NOP
NOP
NOP
NOP
CK
CK
Command
DQS
NOP
WRITEA
NOP
WRITEB
tDQSSmax
*1
tWPRES*1
DQ ′s
Din 0 Din 1 Din 2 Din 3 Din 0 Din 1 Din 2 Din 3
Figure 10. Burst write operation timing
1. The soecific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown
(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus.
If a previous write was in progress, DQS could be High at this time, depending on tDQSS.
(Refer to AC parameter table in page 42)
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3.3.3 Read Interrupted by a Read
A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When
the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst
length. The data from the first Read command continues to appear on the outputs until the CAS latency from
the interrupting Read command is satisfied. At this point the data from the interrupting Read command
appears. Read to Read interval is minimum 1 Clock.
< Burst Length=4, CAS Latency=2 >
0
1
2
3
4
5
6
7
8
NOP
NOP
NOP
NOP
NOP
NOP
CK
CK
Command
READ A
READ B
NOP
DQS
CAS Latency=2
DQ ′s
Dout A0 Dout A 1 Dout B0 Dout B1 Dout B 2 Dout B 3
Figure 11. Read interrupted by a read timing
3.3.4 Read Interrupted by a Write & Burst Stop
To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data contention on the I/O bus by placing the DQ’s(Output drivers) in a high impedance state. To insure the DQ’s are tristated one cycle before the beginning the write operation, Burst stop command must be applied at least 2
clock cycles for CL=2 and at least 3 clock cycles for CL=2.5 before the Write command.
< Burst Length=4, CAS Latency=2 >
0
1
2
3
4
5
6
7
8
CK
CK
Command
READ
Burst Stop
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
DQS
CAS Latency=2
DQ ′s
Dout 0 Dout 1
Din 0
Din 1
Din 2
Din 3
Figure 12. Read interrupted by a write and burst stop timing.
The following functionality establishes how a Write command may interrupt a Read burst.
1. For Write commands interrupting a Read burst, a Burst Terminate command is required to stop the read
burst and tristate the DQ bus prior to valid input write data. Once the Burst Terminate command has been
issued, the minimum delay to a Write command = RU(CL) [CL is the CAS Latency and RU means round up
to the nearest integer].
2. It is illegal for a Write command to interrupt a Read with autoprecharge command.
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3.3.5 Read Interrupted by a Precharge
A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required
for the read to precharge intervals. A precharge command to output disable latency is equivalent to the CAS
latency.
< Burst Length=8, CAS Latency=2 >
0
1
2
3
4
5
6
7
NOP
NOP
NOP
NOP
8
CK
CK
1tCK
Command
READ
Precharge
NOP
NOP
NOP
DQS
CAS Latency=2
DQ ′s
Dout 0 Dout 1 Dout 2 Dout 3 Dout 4 Dout 5 Dout 6 Dout 7
Interrupted by precharge
Figure 13. Read interrupted by a precharge timing
When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same
bank before the Read burst is complete. The following functionality determines when a Precharge command
may be given during a Read burst and when a new Bank Activate command may be issued to the same bank.
1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command
may be given on the rising clock edge which is CL clock cycles before the end of the Read burst where CL
is the CAS Latency. A new Bank Activate command may be issued to the same bank after tRP (RAS
Precharge time).
2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on
the rising clock edge which is CL clock cycles before the last data from the interrupted Read burst where
CL is the CAS Latency. Once the last data word has been output, the output buffers are tristated. A new
Bank Activate command may be issued to the same bank after tRP.
3. For a Read with autoprecharge command, a new Bank Activate command may be issued to the same
bank after tRP where tRP begins on the rising clock edge which is CL clock cycles before the end of the
Read burst where CL is the CAS Latency. During Read with autoprecharge, the initiation of the internal
precharge occurs at the same time as the earliest possible external Precharge command would initiate a
precharge operation without interrupting the Read burst as described in 1 above.
4. For all cases above, tRP is an analog delay that needs to be converted into clock cycles. The number of
clock cycles between a Precharge command and a new Bank Activate command to the same bank equals
tRP/tCK (where tCK is the clock cycle time) with the result rounded up to the nearest integer number of
clock cycles. (Note that rounding to X.5 is not possible since the Precharge and Bank Activate commands
can only be given on a rising clock edge).
In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge
time] has been satisfied. This includes Read with autoprecharge commands where tRAS(min) must still be
satisfied such that a Read with autoprecharge command has the same timing as a Read command followed by
the earliest possible Precharge command which does not interrupt the burst.
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3.3.6 Write Interrupted by a Write
A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the interval that separates the commands must be at least one clock cycle. When the previous burst
is interrupted, the remaining addresses are overridden by the new address and data will be written into the
device until the programmed burst length is satisfied.
< Burst Length=4 >
CK
CK
0
1
2
3
4
5
6
7
8
NOP
NOP
NOP
NOP
NOP
NOP
1tCK
Command
NOP
WRITE A
WRITE b
DQS
DQ ′s
Din A0
Din A1
Din B0
Din B1
Din B2
Din B3
Figure 14. Write interrupted by a write timing
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3.3.7 Write Interrupted by a Read & DM
A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance
state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention.
When the read command is registered, any residual data from the burst write cycle must be masked by DM.
The delay from the last data to read command (tCDLR) is required to avoid the data contention DRAM inside.
Data that are presented on the DQ pins before the read command is initiated will actually be written to the
memory. Read command interrupting write can not be issued at the next clock edge of that of write command.
< Burst Length=8, CAS Latency=2 >
0
1
2
3
4
5
6
7
8
NOP
NOP
CK
CK
Command
NOP
WRITE
NOP
NOP
NOP
READ
NOP
tCDLR
tDQSSmax
DQS
tWPRES
CAS Latency=2
DQ ′s
Din 0
Din 1
Din 2
Din 3
tDQSSmin
Din 4
Din 5
Din 6
Din 6
Din 7
Din 7
Dout 0 Dout 1 Dout 2 Do
tCDLR
DQS
CAS Latency=2
tWPRES
DQ ′s
Din 0
Din 1
Din 2
Din 3
Din 4
Din 5
Dout 0 Dout 1 Dout 2 Do
DM
Figure 15. Write interrupted by a read and DM timing
The following function established how a Read command may interrupt a Write burst and which input data is
not written into the memory.
1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock
cycles. The case where the Write to Read delay is 1 clock cycle is disallowed
2. For Read commands interrupting a Write burst, the DM pin must be used to mask the input data words
whcich immediately precede the interrupting Read operation and the input data word which immediately
follows the interrupting Read operation
3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip
(i.e., the memory controller) in time to allow the buses to turn around before the DDR SDRAM drives them
during a read operation.
4. If input Write data is masked by the Read command, the DQS input is ignored by the DDR SDRAM
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3.3.8 Write Interrupted by a Precharge & DM
A burst write operation can be interrupted before completion of the burst by a precharge of the same bank.
Random column access is allowed. A write recovery time(tWR) is required from the last data to precharge
command. When precharge command is asserted, any residual data from the burst write cycle must be
masked by DM.
< Burst Length=8 >
0
CK
CK
Command
NOP
1
2
WRITE A
NOP
3
4
NOP
5
NOP
NOP
6
Precharge
7
WRITEB
8
NOP
tDQSSmax
DQS
tWR
DQ ′s
Dina0
Dina1
Dina2
Dina3
Dina 4
Dina 5
Dina6
Dina1
Dina 2
Dina3
Dina4
Dina5
Dina6
Dina7
Dina7
Dinb0
tDQSSmin
DQS
DQ ′s
Dina0
Dinb0
Dinb1
DM
Figure 16. Write interrupted by a precharge and DM timing
Precharge timing for Write operations in DRAMs requires enough time to allow “write recovery” which is the
time required by a DRAM core to properly store a full “0” or “1” level before a Precharge operation. For DDR
SDRAM, a timing parameter, tWR, is used to indicate the required amount of time between the last valid write
operation and a Precharge command to the same bank.
The precharge timing for writes is a complex definition since the write data is sampled by the data strobe and
the address is sampled by the input clock. Inside the SDRAM, the data path is eventually synchronized with
the address path by switching clock domains from the data strobe clock domain to the input clock domain.
This makes the definition of when a precharge operation can be initiated after a write very complex since the
write recovery parameter must reference only the clock domain that is used to time the internal write operation,
i.e., the input clock domain.
tWR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid data and
ends on the rising clock edge that strobes in the precharge command.
1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the
minimum time for write recovery is defined by tWR.
2. When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask
input data during the time between the last valid write data and the rising clock edge on which the
Precharge command is given. During this time, the DQS input is still required to strobe in the state of DM.
The minimum time for write recovery is defined by tWR.
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3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same
bank after tWR+tRP where tWR+tRP starts on the falling DQS edge that strobed in the last valid data and
ends on the rising clock edge that strobes in the Bank Activate command. During write with
autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible
external Precharge command without interrupting the Write burst as described in 1 above.
4. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to
Precharge time] has been satisfied. This includes Write with autoprecharge commands where tRAS(min)
must still be satisfied such that a Write with autoprecharge command has the same timing as a Write
command followed by the earliest possible Precharge command which does not interrupt the burst.
3.3.9 Burst Stop
The burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of
the clock(CK). The burst stop command has the fewest restrictions making it the easiest method to use when
terminating a burst read operation before it has been completed. When the burst stop command is issued during a burst read cycle, the pair of data and DQS(Data Strobe) go to a high impedance state after a delay which
is equal to the CAS latency set in the mode register. The burst stop command, however, is not supported during a write burst operation.
< Burst Length=4, CAS Latency= 2, 2.5 >
0
1
2
3
4
5
6
7
8
NOP
NOP
NOP
NOP
NOP
CK
CK
Command
READ A
Burst Stop
NOP
NOP
DQS
CAS Latency=2
DQ ′s
Dout 0 Dout 1
The burst ends after a delay equal to the CAS latency.
DQS
CAS Latency=2.5
DQ ′s
Dout 0 Dout 1
Figure 17. Burst stop timing
The Burst Stop command is a mandatory feature for DDR SDRAMs. The following functionality is required:
1. The BST command may only be issued on the rising edge of the input clock, CK.
2. BST is only a valid command during Read bursts.
3. BST during a Write burst is undefined and shall not be used.
4. BST applies to all burst lengths.
5. BST is an undefined command during Read with autoprecharge and shall not be used.
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6. When terminating a burst Read command, the BST command must be issued LBST (“BST Latency”) clock
cycles before the clock edge at which the output buffers are tristated, where LBST equals the CAS latency
for read operations. This is shown in previous page Figure with examples for CAS latency (CL) of 1.5, 2,
2.5, 3 and 3.5 (only selected CAS latencies are required by the DDR SDRAM standards, the others are
optional).
7. When the burst terminates, the DQ and DQS pins are tristated.
The BST command is not byte controllable and applies to all bits in the DQ data word and the(all) DQS pin(s).
3.3.10 DM masking
The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle, not read
cycle. When the data mask is activated (DM high) during write operation, DDR SDRAM does not accept the
corresponding data.(DM to data-mask latency is zero).
DM must be issued at the rising or falling edge of data strobe.
< Burst Length=8 >
CK
CK
Command
0
1
WRITE
NOP
2
3
4
5
6
7
8
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSS
DQS
DQ ′s
Din 0 Din 1 Din 2
Din 3 Din 4 Din 5 Din 6
Din7
DM
masked by DM=H
Figure 18. DM masking timing
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3.3.11 Read With Auto Precharge
If a read with auto-precharge command is initiated, the DDR SDRAM automatically enters the precharge
operation BL/2 clock later from a read with auto-precharge command when tRAS(min) is satisfied. If not, the
start point of precharge operation will be delayed until tRAS(min) is satisfied. Once the precharge operation
has started the bank cannot be reactivated and the new command can not be asserted until the precharge
time(tRP) has been satisfied.
< Burst Length=4, CAS Latency= 2, 2.5>
0
1
2
3
4
5
6
7
8
NOP
NOP
NOP
NOP
NOP
NOP
CK
CK
BANK A
ACTIVE
Command
READ A
Auto Precharge
NOP
tRAS(min.)
DQS
CAS Latency=2
DQ ′s
Dout 0 Dout 1 Dout 2 Dout 3
* Bank can be reactivated at the
completion of precharge
tRP
DQS
CAS Latency=2.5
DQ ′s
Dout 0 Dout 1 Dout 2 Dout 3
Begin Auto-Precharge
Figure 19. Read with auto precharge timing
When the Read with Auto precharge command is issued, new command can be asserted at 3,4 and 5
respectively as follows,
Asserted
command
For same Bank
For Different Bank
3
4
5
3
4
5
READ
READ +
No AP*1
READ+
No AP
Illegal
Legal
Legal
Legal
READ+AP
READ +
AP
READ +
AP
Illegal
Legal
Legal
Legal
Active
Illegal
Illegal
Illegal
Legal
Legal
Legal
Precharge
Legal
Legal
Illegal
Legal
Legal
Legal
*1
: AP = Auto Precharge
Table 6. Operating description when new command asserted
while read with auto precharge is issued
- 29 of 63 -
REV. 0.61 August 9. '99
128Mb DDR SDRAM
Target
3.3.12 Write with Auto Precharge
If A10 is high when write command is issued , the write with auto-precharge function is performed. Any new
command to the same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping tWR(min).
< Burst Length=4 >
0
1
2
3
4
5
6
7
8
CK
CK
BANK A
ACTIVE
Command
NOP
WRITE A
Auto Precharge
NOP
NOP
NOP
Din 0
Din 1 Din 2 Din 3
NOP
NOP
NOP
DQS
DQ ′s
* Bank can be reactivated at
completion of tRP
tWR
tRP
Internal precharge start
Figure 20. Write with auto precharge timing
Burst length = 4
Asserted
command
For same Bank
For Different Bank
3
4
5
6
7
8
3
4
5
6
7
WRITE
WRITE+
No AP*1
WRITE+
No AP
WRITE+
No AP
Illegal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
WRITE+
AP
WRITE+
AP
WRITE+
AP
WRITE+
AP
Illegal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
READ
Illegal
READ+NO
AP+DM *2
READ+NO
AP+DM
READ+
NO AP
READ+
NO AP
Illegal
Illegal
Illegal
Legal
Legal
Legal
READ+AP
Illegal
READ +
AP+DM
READ +
AP+DM
READ +
AP
READ +
AP
Illegal
Illegal
Illegal
Legal
Legal
Legal
Active
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
Precharge
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
*1
: AP = Auto Precharge
*2
: DM : Refer to " 3.3.7 Write Interrupted by a Read & DM " in page 25.
Table 7. Operating description when new command asserted
while write with auto precharge is issued
- 30 of 63 -
REV. 0.61 August 9. '99
128Mb DDR SDRAM
Target
3.3.13 Auto Refresh & Self Refresh
Auto Refresh
An auto refresh command is issued by having CS, RAS and CAS held low with CKE and WE high at the rising edge of the clock(CK). All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. No control of the external address pins is required once this cycle has started because of the
internal address counter. When the refresh cycle has completed, all banks will be in the idle state. A delay
between the auto refresh command and the next activate command or subsequent auto refresh command
must be greater than or equal to the tRFC(min).
∼
Auto
Refresh
PRE
CMD
∼
∼
Command
∼
CK
CK
CKE = High
tRP
tRFC
Figure 21. Auto refresh timing
Self Refresh
∼
∼
Read
∼
CKE
∼
Active
∼
∼
∼
Self
Refresh
∼
Command
∼
∼ ∼
∼
CK
CK
∼
A self refresh command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising
edge of the clock(CK). Once the self refresh command is initiated, CKE must be held low to keep the device in
self refresh mode. During the self refresh operation, all inputs except CKE are ignored. The clock is internally
disabled during self refresh operation to reduce power consumption. The self refresh is exited by supplying
stable clock input before returning CKE high, asserting deselect or NOP command and then asserting CKE
high for longer than tXSR for locking of DLL.
tXSA
tXSR
Figure 22. Self refresh timing
- 31 of 63 -
REV. 0.61 August 9. '99
128Mb DDR SDRAM
Target
3.3.14 Power down
The power down mode is entered when CKE is low and exited when CKE is high. Once the power down
mode is initiated, all of the receiver circuits except clock, CKE and DLL circuit tree are gated off to reduce
power consumption. The all banks should be in idle state prior to entering the precharge power down mode
and CKE should be set high at least 1tck+tIS prior to row active command . During power down mode, refresh
operations cannot be performed, therefore the device cannot remain in power down mode longer than the
refresh period(tREF) of the device.
Precharge
power
down
Entry
∼
∼
Active
Active
power
down
Entry
Active
power
down
Exit
Read
∼
∼
CKE
∼
∼
Precharge
∼
Command
∼
∼
CK
CK
Figure 23. Power down entry and exit timing
- 32 of 63 -
REV. 0.61 August 9. '99
128Mb DDR SDRAM
Target
4. Command Truth Table
COMMAND
CKEn
CS
RAS
CAS
WE
DM
X
L
L
L
L
X
OP CODE
1, 2
X
L
L
L
L
X
OP CODE
1, 2
L
L
L
H
X
X
L
H
H
H
H
X
X
X
X
X
Register
Extended MRS
H
Register
Mode Register Set
H
Auto Refresh
Refresh
Entry
Self
Refresh
L
L
H
Bank Active & Row Addr.
H
X
L
L
H
H
X
V
Read &
Column Address
H
X
L
H
L
H
X
V
Write &
Column Address
Exit
H
H
BA0,1
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Burst Stop
Precharge
Bank Selection
X
L
H
L
L
X
H
X
L
H
H
L
X
H
All Banks
Active Power Down
H
X
Entry
H
L
Exit
L
H
Entry
H
L
Exit
L
H
Precharge Power Down Mode
DM
No operation (NOP) : Not defined
L
L
H
L
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
H
H
X
X
X
X
X
X
L
H
H
H
Note
3
3
3
3
Row Address
L
H
L
H
Column
Address
(A0 ~A9)
4
Column
Address
(A0 ~A9)
4
X
V
L
X
H
4
4, 6
7
X
5
X
X
X
X
X
V
H
Table 8. Command truth table
X
V
A10/AP
A11,
A9 ~ A0
CKEn-1
X
X
X
8
9
9
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
1. OP Code : Operand Code. A 0 ~ A11 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2.EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA 0 ~ BA 1 : Bank select addresses.
If both BA 0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA 0 is "High" and BA 1 is "Low" at read, write, row active and precharge, bank B is selected.
If both BA 0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA 0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA 0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
- 33 of 63 -
REV. 0.61 August 9. '99
128Mb DDR SDRAM
Target
5. Functional Truth Table
Current State
CS
PRECHARGE
STANDBY
L
H
H
L
X
Burst Stop
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ/WRITE
ILLEGAL*2
L
L
H
H
BA, RA
Active
Bank Active, Latch RA
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL*4
L
L
L
H
X
Refresh
AUTO-Refresh*5
L
L
L
L
Op-Code, Mode-Add
MRS
Mode Register Set*5
L
H
H
L
X
Burst Stop
NOP
L
H
L
H
BA, CA, A10
READ/READA
Begin Read, Latch CA,
Determine Auto-Precharge
L
H
L
L
BA, CA, A10
WRITE/WRITEA
Begin Write, Latch CA,
Determine Auto-Precharge
L
L
H
H
BA, RA
Active
Bank Active/ILLEGAL*2
L
L
H
L
BA, A10
PRE/PREA
Precharge/Precharge All
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
L
H
H
L
X
Burst Stop
Terminate Burst
L
H
L
H
BA, CA, A10
READ/READA
Terminate Burst, Latch CA,
Begin New Read, Determine
Auto-Precharge*3
L
H
L
L
BA, CA, A10
WRITE/WRITEA ILLEGAL
L
L
H
H
BA, RA
Active
Bank Active/ILLEGAL*2
L
L
H
L
BA, A10
PRE/PREA
Terminate Burst, Precharge
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add MRS
ACTIVE
STANDBY
READ
RAS CAS
WE
Address
Command
Action
ILLEGAL
Table 9-1. Functional truth table
- 34 of 63 -
REV. 0.61 August 9. '99
128Mb DDR SDRAM
Current State
CS
WRITE
L
H
H
L
X
Burst Stop
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
Terminate Burst With DM=High,
Latch CA, Begin Read, Determine Auto-Precharge*3
L
H
L
L
BA, CA, A10
Terminate Burst, Latch CA,
WRITE/WRITEA Begin new Write, Determine
Auto-Precharge*3
L
L
H
H
BA, RA
Active
Bank Active/ILLEGAL*2
L
L
H
L
BA, A10
PRE/PREA
Terminate Burst With DM=High,
Precharge
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
L
H
H
L
X
Burst Stop
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
*6
L
H
L
L
BA, CA, A10
WRITE/WRITEA ILLEGAL
L
L
H
H
BA, RA
Active
*6
L
L
H
L
BA, A10
PRE/PREA
*6
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
L
H
H
L
X
Burst Stop
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
*7
L
H
L
L
BA, CA, A10
WRITE/WRITEA *7
L
L
H
H
BA, RA
Active
*7
L
L
H
L
BA, A10
PRE/PREA
*7
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add MRS
READ with
AUTO
PRECHARGE*6
(READA)
WRITE with
AUTO
RECHARGE*7
(WRITEA)
RAS CAS
Target
WE
Address
Command
Action
ILLEGAL
Table 9-2. Functional truth table
- 35 of 63 -
REV. 0.61 August 9. '99
128Mb DDR SDRAM
Current State
CS
PRECHARGING
(DURING tRP)
L
H
H
L
X
Burst Stop
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ/WRITE
ILLEGAL*2
L
L
H
H
BA, RA
Active
ILLEGAL*2
L
L
H
L
BA, A10
PRE/PREA
NOP*4(Idle after tRP)
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
L
H
H
L
X
Burst Stop
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ/WRITE
ILLEGAL*2
L
L
H
H
BA, RA
Active
ILLEGAL*2
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL*2
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
L
H
H
L
X
Burst Stop
ILLEGAL*2
L
H
L
H
BA, CA, A10
READ
ILLEGAL*2
L
H
L
L
BA, CA, A10
WRITE
WRITE
L
L
H
H
BA, RA
Active
ILLEGAL*2
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL*2
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
ROW
ACTIVATING
(FROM ROW
ACTIVE TO
tRCD)
WRITE
RECOVERING
(DURING tWR
OR tCDLR)
RAS CAS
Target
WE
Address
Command
Action
Table 9-3. Functional truth table
- 36 of 63 -
REV. 0.61 August 9. '99
128Mb DDR SDRAM
Current State
CS
REFRESHING
L
H
H
L
X
Burst Stop
ILLEGAL
L
H
L
X
BA, CA, A10
READ/WRITE
ILLEGAL
L
L
H
H
BA, RA
Active
ILLEGAL
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
L
H
H
L
X
Burst Stop
ILLEGAL
L
H
L
X
BA, CA, A10
READ/WRITE
ILLEGAL
L
L
H
H
BA, RA
Active
ILLEGAL
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
MODE
REGISTER
SETTING
RAS CAS
Target
WE
Address
Command
Action
Table 9-4. Functional truth table
- 37 of 63 -
REV. 0.61 August 9. '99
128Mb DDR SDRAM
Target
CKE
n-1
CKE
n
CS
RAS
CAS
WE
L
H
H
X
X
X
X
Exit Self-Refresh
L
H
L
H
H
H
X
Exit Self-Refresh
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOPeration(Maintain Self-Refresh)
POWER
DOWN
L
H
X
X
X
X
X
Exit Power Down(Idle after tPDEX)
L
L
X
X
X
X
X
NOPeration(Maintain Power Down)
ALL BANKS
H
H
X
X
X
X
X
Refer to Function True Table
IDLE*9
H
L
L
L
L
H
X
Enter Self-Refresh
H
L
H
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
Enter Power Down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
L
X
X
X
X
X
X
Refer to Current State=Power Down
H
H
X
X
X
X
X
Refer to Function Truth Table
Current State
SELFREFRESHING*8
ANY STATE
Add
Action
other than
listed above
Table 9-5. Functional truth table
ABBREVIATIONS :
H=High Level, L=Low level, X=Don′t Care
Note :
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state ; function may be legal in the bank indicated by BA, depending on the state of that bank.
3. Must satisfy bus contention, bus turn around and write recovery requirements.
4. NOP to bank precharging or in idle sate. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
6. Refer to "3.3.11 Read with Auto Precharge" in page 29 for detailed information.
7. Refer to "3.3.12 Write with Auto Precharge" in page 30 for detailed information.
8. CKE Low to High transition will re-enable CK, CK and other inputs asynchronously. A minimum setup time must be satisfied
before issuing any command other than EXIT.
9. Power-Down and Self-Refresh can be entered only from All Bank Idle state.
ILLEGAL = Device operation and/or data integrity are not guaranteed.
- 38 of 63 -
REV. 0.61 August 9. '99
128Mb DDR SDRAM
Target
6. Absolute Maximum Rating
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD supply relative to VSS
VDD, VDDQ
-1.0 ~ 3.6
V
Voltage on VDDQ supply relative to VSS
VDDQ
-0.5 ~ 3.6
V
Storage temperature
TSTG
-55 ~ +150
°C
Power dissipation
PD
1.0
W
Short circuit current
IOS
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
Table 10. Absolute maximum ratings
7. DC Operating Conditions & Specifications
7.1 DC Operating Conditions
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Symbol
Min
Max
Unit
Supply voltage(for device with a nominal VDD of 3.3V)
VDD
3.0
3.6
V
Supply voltage(for device with a nominal VDD of 2.5V)
VDD
2.3
2.7
I/O Supply voltage
VDDQ
2.3
2.7
V
I/O Reference voltage
VREF
1.15
1.35
V
1
2
I/O Termination voltage(system)
VTT
VREF-0.04
VREF +0.04
V
Input logic high voltage
VIH (DC)
VREF+0.18
VDDQ+0.3
V
Input logic low voltage
VIL(DC)
-0.3
VREF-0.18
V
Input Voltage Level, CK and CK inputs
VIN (DC)
-0.3
VDDQ+0.3
V
Input Differential Voltage, CK and CK inputs
VID (DC)
0.36
VDDQ+0.6
V
II
-5
5
uA
5
Input leakage current
Output leakage current
IOZ
-5
Output High Current (VOUT = 1.95V)
IOH
-15.2
mA
Output Low Current (VOUT = 0.35V)
IOL
15.2
mA
Note
3
uA
Notes 1. V REF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-topeak noise on V REF may not exceed 2% of the DC value
2.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to
VREF , and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
Table 11. DC operating condition
- 39 of 63 -
REV. 0.61 August 9. '99
PC 200/266 DDR SDRAM
128Mb DDR SDRAM
7.1 DC Specifications
128Mb(Common)
Parameter
Symbol
Test Condition
Version
-Z
-Y
-0
Unit
Precharge Power-down
Standby Current
IDD2P
CKE≤VIL(max), tCK=tCK(min), All banks idle
25
mA
Idle Standby Current
IDD2N
CKE≥VIH(min), CS≥VIH(min), tCK=tCK(min)
45
mA
Active Power-down
Standby Current
IDD3P
All banks idle, CKE≤VIL(max), tCK=tCK(min)
40
mA
Active Standby Current
IDD3N
One bank; Active-Precharge, tRC=tRAS(max),
tCK=tCK(min)
60
mA
Auto Refresh Current
IDD5
tRC=tRFC(min)
Self Refresh Current
IDD6
CKE≤0.2V
200
165
2.5
mA
Note
2
mA
32Mx4
Parameter
Symbol
Test Condition
Version
-Z
-Y
-0
T.B.D
T.B.D
T.B.D
Unit
mA
Note
Operating Current
(One Bank Active)
IDD0
tRC=tRC(min) tCK=tCK(min)
Active-Precharge
Operating Current
(One Bank Active)
IDD1
Burst=2 tRC=tRC(min), CL=2.5
IOUT=0mA, Active-Read-Precharge
125
125
105
Operating Current(Read)
IDD4R
Burst=2, CL=2.5, tCK=tCK(min), IOUT=0mA
150
150
125
mA
1
Operating Current(Write)
IDD4W
Burst=2, CL=2.5, tCK=tCK(min)
115
115
95
mA
1
Unit
Note
1
mA
16Mx8
Parameter
Symbol
Test Condition
Version
-Z
-Y
-0
T.B.D
T.B.D
T.B.D
mA
Operating Current
(One Bank Active)
IDD0
tRC=tRC(min) tCK=tCK(min)
Active-Precharge
Operating Current
(One Bank Active)
IDD1
Burst=2 tRC=tRC(min), CL=2.5
IOUT=0mA, Active-Read-Precharge
135
135
115
mA
Operating Current(Read)
IDD4R
Burst=2, CL=2.5, tCK=tCK(min), IOUT=0mA
170
170
145
mA
1
Operating Current(Write)
IDD4W
Burst=2, CL=2.5, tCK=tCK(min)
130
130
110
mA
1
Unit
Note
1
8Mx16
Parameter
Symbol
Test Condition
Version
-Z
-Y
-0
T.B.D
T.B.D
T.B.D
Operating Current
(One Bank Active)
IDD0
tRC=tRC(min) tCK=tCK(min)
Active-Precharge
mA
Operating Current
(One Bank Active)
IDD1
Burst=2 tRC=tRC(min), CL=2.5
IOUT=0mA, Active-Read-Precharge
145
140
125
mA
Operating Current(Read)
IDD4R
Burst=2, CL=2.5, tCK=tCK(min), IOUT=0mA
200
200
175
mA
1
Operating Current(Write)
IDD4W
Burst=2, CL=2.5, tCK=tCK(min)
150
150
130
mA
1
1
Note 1.Measured with outputs open.
2. Refresh period is 64ms.
Table 12. DC specifications
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128Mb DDR SDRAM
Target
8. AC Operating Conditions & Timming Specification
8.1 AC Operating Conditions
Parameter/Condition
Symbol
Max
Min
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
VIL(AC)
VREF + 0.35
Input Differential Voltage, CK and CK inputs
VID(AC)
0.7
Input Crossing Point Voltage, CK and CK inputs
VIX(AC)
0.5*VDDQ-0.2
Unit
Note
V
VREF - 0.35
V
VDDQ+0.6
V
1
0.5*VDDQ+0.2
V
2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
Table 13. AC operating conditions
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128Mb DDR SDRAM
Target
8.2 AC Timming Parameters & Specifications
Parameter
Symbol
- Z(PC266@CL=2)
Min
Max
- Y(PC266@CL=2.5) - 0(PC200@CL=2)
Min
Max
Min
Max
Unit
Row cycle time
tRC
65
65
70
Refresh row cycle time
tRFC
75
75
80
Row active time
tRAS
45
RAS to CAS delay
tRCD
20
20
20
ns
Row precharge time
tRP
20
20
20
ns
Row active to Row active delay
tRRD
15
15
15
ns
Write recovery time
tWR
2
2
2
tCK
Last data in to Read command
tCDLR
1
1
1
tCK
Last data in to Write command
tCDLW
0
0
0
tCK
Col. address to Col. address delay
tCCD
1
1
1
tCK
Clock cycle time
tCK
CL=2.0
CL=2.5
12K
48
12K
48
ns
ns
12K
ns
7.5
15
10
15
10
15
ns
7
15
7.5
15
8
15
ns
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock high level width
tCH
Clock low level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
DQS-out access time from CK/CK
tDQSCK
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
ns
Output data access time from CK/CK
tAC
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
ns
Data strobe edge to ouput data edge
tDQSQ
-0.5
+0.5
-0.5
+0.5
-0.6
+0.6
ns
Read Preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read Postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Data out high impedence time from CK/CK tHZQ
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
ns
CK to valid DQS-in
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS-in setup time
tWPRES
0
0
0
ns
DQS-in hold time
tWPREH
0.25
0.25
0.25
tCK
DQS-in high level width
tDQSH
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS-in low level width
tDQSL
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS-in cycle time
tDSC
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Address and Control Input setup time
tIS
1.1
1.1
1.2
ns
Address and Control Input hold time
tIH
1.1
1.1
1.2
ns
Mode register set cycle time
tMRD
15
15
16
ns
DQ & DM setup time to DQS
tDS
0.5
0.5
0.6
ns
DQ & DM hold time to DQS
tDH
0.5
0.5
0.6
ns
DQ & DM input pulse width
tDIPW
1.75
1.75
2
ns
Power down exit time
tPDEX
10
10
10
ns
Exit self refresh to write command
tXSW
95
116
ns
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Note
2
3
REV. 0.61 August 9. '99
128Mb DDR SDRAM
Parameter
Target
Symbol
PC266A
Min
Max
PC266B
Min
Max
PC200
Min
Max
Unit
Note
Exit self refresh to bank active command
tXSA
75
75
80
ns
Exit self refresh to read command
tXSR
200
200
200
Cycle
15.6
15.6
15.6
us
1
1
Refresh interval time
64Mb, 128Mb
256Mb
tREF
7.8
7.8
7.8
us
Output DQS valid window
tDV
0.35
0.35
0.35
tCK
DQS write postamble time
tWPST
0.25
0.25
0.25
tCK
Auto precharge write recovery + Precharge time
tDAL
35
35
35
ns
4
.
1. Maximum burst refresh of 8
2. tHZQ transitions occurs in the same access time windows as valid data transitions. These parameters are not referenced
to a specific voltage level, but specify when the device output is no longer driving.
3. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
4. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
Table 14. AC timing parameters and specifications
- 43 of 63 -
REV. 0.61 August 9. '99
128Mb DDR SDRAM
Target
9. AC Operating Test Conditions
(VDD=2.5/3.3V, VDDQ=2.5V, TA= 0 to 70°C)
Parameter
Value
Unit
Input reference voltage for Clock
0.5 * VDDQ
V
Input signal maximum peak swing
1.5
V
Input signal minimum slew rate
1.0
V/ns
VREF+0.35/VREF-0.35
V
VREF
V
Vtt
V
Input Levels(VIH/VIL)
Input timing measurement reference level
Output timing measurement reference level
Output load condition
Note
See Load Circuit
Table 15. AC operating test conditions
Vtt=0.5*VDDQ
RT=50Ω
Output
Z0=50Ω
CLOAD =30pF
VREF
=0.5*VDDQ
Figure 24. Output Load Circuit (SSTL_2)
10. Input/Output Capacitance
(VDD=2.5, VDDQ=2.5V, TA= 25°C , f=1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance
(A0 ~ A 11, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)
CIN1
2.5
3.5
pF
Input capacitance( CK, CK )
CIN2
2.5
3.5
pF
Data & DQS input/output capacitance(DQ0~DQ15)
COUT
4.0
5.5
pF
Input capacitance(DM)
CIN3
4.0
5.5
pF
Table 16. Input/output capacitance
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128Mb DDR SDRAM
Target
11. IBIS: I/V Characteristics for Input and Output Buffers
11.1 Normal strength driver
1. The nominal pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I
curve of Figure a.
2. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage
will lie within the outer bounding lines the of the V-I curve of below Figure.
Maximum
Iout(mA)
Nominal High
Nominal Low
Minimum
Vout(V)
3. The nominal pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I
curve of below Figure.
4. The Full variation in driver pullup current from minimum to maximum process, temperature and voltage
will lie within the outer bounding lines of the V-I curve of below Figrue
Minumum
Iout(mA)
Nominal Low
Nominal High
Maximum
Vout(V)
5. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7,
for device drain to source voltage from 0 to VDDQ/2
6. The Full variation in the ratio of the nominal pullup to pulldown current should be unity ±10%, for device
drain to source voltages from 0 to VDDQ/2
Figure 25. I/V characteristics for input/output buffers:Pull up(above) and pull down(below)
- 45 of 63 -
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128Mb DDR SDRAM
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Pulldown Current (mA)
pullup Current (mA)
Voltage
(V)
Normal
Low
Normal
High
Minimum
Maximum
Normal
Low
Normal
High
Minimum
Maximum
0.1
5.7
6.4
4.3
8.3
-5.8
-7.2
-4.3
-8.6
0.2
11.5
12.7
8.7
16.5
-11.5
-13.7
-8.7
-17.0
0.3
17.1
19.0
13.0
24.4
-17.1
-20.0
-13.0
-25.3
0.4
22.7
25.1
17.4
32.0
-22.6
-26.1
-17.4
-33.6
0.5
28.1
31.1
21.7
39.4
-28.1
-32.2
-21.7
-41.7
0.6
32.6
36.9
26.1
46.6
-32.4
-38.2
-26.1
-49.6
0.7
37.2
41.7
30.4
53.6
-35.9
-44.2
-30.4
-57.5
0.8
41.2
47.0
34.7
59.6
-38.8
-50.1
-34.0
-65.2
0.9
44.8
52.1
37.4
65.9
-41.3
-56.0
-36.0
-72.9
1.0
48.4
56.9
40.2
72.0
-43.4
-61.8
-36.5
-80.4
1.1
51.0
61.5
42.3
77.8
-45.1
-67.5
-36.8
-87.7
1.2
53.0
65.9
43.6
83.3
-46.4
-73.2
-37.0
-94.9
1.3
54.6
70.0
44.4
88.5
-47.2
-78.9
-37.2
-102.0
1.4
55.9
74.0
44.7
93.5
-47.6
-84.6
-37.4
-109.0
1.5
56.7
77.6
45.0
97.9
-47.8
-90.1
-37.6
-116.0
1.6
57.1
81.0
45.3
102.3
-48.1
-95.6
-37.8
-123.0
1.7
57.5
84.1
45.7
105.8
-48.2
-101.0
-37.9
-129.0
1.8
58.0
87.0
46.1
109.3
-48.4
-106.0
-38.0
-136.0
1.9
58.5
89.9
46.3
112.8
-48.6
-112.0
-38.1
-142.0
2.0
59.0
91.7
46.6
116.3
-48.7
-117.0
-38.2
-148.0
2.1
59.3
93.5
46.8
119.3
-48.9
-122.0
-38.3
-154.0
2.2
59.7
95.2
47.0
122.2
-49.1
-127.0
-38.4
-160.0
2.3
60.2
96.1
47.1
124.9
-49.2
-132.0
-38.5
-166.0
2.4
60.5
97.0
47.2
127.4
-49.3
-137.0
-38.6
-171.0
2.5
60.9
97.9
47.4
129.5
-49.5
-142.0
-38.7
-177.0
Table 17. Pull down and pull up current values
Temperature (Tjunction)
Typical
Minimum
Maximum
Vdd/Vddq
Normal
Minimum
Maximum
50°C
0°C
0°C
2.5V
2.3V
2.7V
The adove characteristics are specied under best, worst and normal process variation/conditions
- 46 of 63 -
REV. 0.61 August 9. '99
128Mb DDR SDRAM
Target
11.2 Half Strength Driver
THe half strength driver IBIS will be included in the
future.
- 47 of 63 -
REV. 0.61 August 9. '99
128Mb DDR SDRAM
Target
12. QFC function
QFC definition
when drive low on reads coincident with the start of DQS, this DRAM output signal says that one cycle later
there will be the first valid DQS output and returned to HI-Z after this finishing a burst operation. It is also
driven low shortly after a write command is received and returned to HI-Z shortly after the last data strobe
transition is received. Whenever the device is in standby, the signal is HI-Z. DQS is intended to enable an
external data switch. QFC can be enabled or disabled through EMRS control.
QFC timming on Read operation
QFC on reads is enabled coincident with the start of DQS preamble, and disabled coincident with the end of
DQS postamble
CL = 2, BL = 2
0
1
2
3
4
5
6
7
8
CK
CK
Command
Read
DQS
DQ’S
QFC
Dout 0 Dout 1
Hi-Z
tQCS
tQCH
Figure 26. QFC timing on read operation
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128Mb DDR SDRAM
Target
QFC timming on Write operation with tDQSSmax
QFC on writes is enabled as soon as possible after the clock edge of write command and disabled as soon
as possible after the last DQS-in low going edge.
0
1
2
3
4
5
6
7
8
BL = 2
CK
CK
Command
Write
DQS@tDQSSmax
DQ’S@tDQSSmax
Dout 0 Dout 1
Hi-Z
QFC
tQCSW
tQCHW
Figure 27. : QFC timing on write operation with tDQSSmax
QFC Timming on Write operation with tDQSSmin
QFC on writes is enabled as soon as possible after the clock edge of write command and disabled
as soon as possible after the last DQS-in low going edge.
CK
CK
0
1
2
3
4
5
6
7
8
BL = 2
Command
Write
DQS@tDQSSmin
DQ’S@tDQSSmin
QFC
Dout 0 Dout 1
Hi-Z
tQCSW
tQCHW
Figure 28. : QFC timing on write operation with tDQSSmax
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REV. 0.61 August 9. '99