MOSEL V58C265804S

MOSEL VITELIC
V58C265804S
HIGH PERFORMANCE
2.5 VOLT 8M X 8 DDR SDRAM
4 BANKS X 2Mbit X 8
PRELIMINARY
6
7
8
System Frequency (fCK)
166 MHz
143 MHz
125 MHz
Clock Cycle Time (tCK3)
6 ns
7 ns
8 ns
6.5 ns
7.5 ns
9 ns
7ns
8ns
10ns
Clock Cycle Time (tCK2.5)
Clock Cycle Time (tCK2)
Features
Description
■ 4 banks x 2Mbit x 8 organization
■ High speed data transfer rates with system
frequency up to 166 MHz
■ Data Mask for Write Control (DM)
■ Four Banks controlled by BA0 & BA1
■ Programmable CAS Latency: 2, 2.5, 3
■ Programmable Wrap Sequence: Sequential
or Interleave
■ Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
■ Automatic and Controlled Precharge Command
■ Suspend Mode and Power Down Mode
■ Auto Refresh and Self Refresh
■ Refresh Interval: 4096 cycles/64 ms
■ Available in 66-pin 400 mil TSOP-II
■ SSTL-2 Compatible I/Os
■ Double Data Rate (DDR)
■ Bidirectional Data Strobe (DQs) for input and
output data, active on both edges
■ On-Chip DLL aligns DQ and DQs transitions with
CLK transitions
■ Differential clock inputs CLK and CLK
■ Power Supply 2.5V ± 0.2V
The V58C265804S is a four bank DDR DRAM organized as 4 banks x 2Mbit x 8. The V58C265804S
achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits
and then synchronizes the output data to a system
clock
All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O transactions are possible on both
edges of DQS.
Operating the four memory banks in an interleaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and
speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
JEDEC 66 TSOP II
–6
-7
-8
Std.
L
Temperature
Mark
0°C to 70 °C
•
•
•
•
•
•
Blank
Package Outline
V58C265804S Rev. 1.3 January 2000
CLK Cycle Time (ns)
1
Power
V58C265804S
MOSEL VITELIC
66 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
Pin Names
CLK, CLK
Differential Clock Input
CKE
Clock Enable
CS
Chip Select
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
DQS
Data Strobe (Bidirectional)
VDD
1
66
VSS
DQ0
VDDQ
2
3
4
5
65
64
63
62
DQ7
VSSQ
NC
DQ6
6
7
8
9
10
61
60
59
58
57
VDDQ
NC
DQ5
VSSQ
NC
A0–A11
Address Inputs
BA0, BA1
Bank Select
11
56
DQ4
DQ0–DQ7
Data Input/Output
12
55
VDDQ
54
53
52
51
50
49
48
47
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
DM
Data Mask
VDD
Power (+2.5V)
VSS
Ground
VDDQ
Power for I/O’s (+2.5V)
NC
NC
13
14
15
16
17
18
19
20
VSSQ
Ground for I/O’s
NC
Not connected
WE
CAS
RAS
21
22
23
46
45
44
CLK
CLK
CKE
VREF
Reference Voltage for Inputs
CS
NC
24
25
26
27
28
29
43
42
NC
NC
41
40
39
38
A11
A9
A8
A7
30
31
32
33
37
36
35
34
A6
A5
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
64M
DDR SDRAM
V58C265804S Rev. 1.3 January 2000
A4
VSS
2
V58C265804S
MOSEL VITELIC
Capacitance*
Absolute Maximum Ratings*
Operating temperature range .................. 0 to 70 °C
Storage temperature range ................-55 to 150 °C
Input/output voltage.................. -0.3 to (VCC+0.3) V
Power supply voltage .......................... -0.3 to 4.6 V
Power dissipation ...........................................1.6 W
Data out current (short circuit).......................50 mA
TA = 0 to 70°C, VCC = 2.5V ± 0.2V, f = 1 Mhz
Max. Unit
Symbol Parameter
CI1
Input Capacitance (A0 to A11)
5
pF
CI2
Input Capacitance
RAS, CAS, WE, CS, CKE
5
pF
CIO
Output Capacitance (DQ)
6.5
pF
CCLK
Input Capacitance (CCLK, CLK)
4
pF
*Note: Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
*Note: Capacitance is sampled and not 100% tested.
Block Diagram
Row Addresses
Column Addresses
A0 - A8, AP, BA0, BA1
Row address
buffer
Column address
buffer
Refresh Counter
Row decoder
Row decoder
Memory array
Memory array
Memory array
Memory array
Bank 0
4096 x 512
x 8 bit
Bank 1
4096 x 512
x 8 bit
Input buffer
Column decoder
Sense amplifier & I(O) bus
Row decoder
Column decoder
Sense amplifier & I(O) bus
Row decoder
Column decoder
Sense amplifier & I(O) bus
Column decoder
Sense amplifier & I(O) bus
Column address
counter
A0 - A11, BA0, BA1
Bank 2
4096 x 512
x 8 bit
Output buffer
Bank 3
4096 x 512
x 8 bit
Control logic & timing generator
DQS
Strobe
Gen.
Data Strobe
V58C265804S Rev. 1.3 January 2000
3
DM
WE
CAS
CS
RAS
CKE
DLL
CLK
CLK, CLK
CLK
DQ0-DQ7
V58C265804S
MOSEL VITELIC
Signal Pin Description
Pin
Type
Signal
Polarity
Function
CLK
CLK
Input
Pulse
Positive
Edge
The system clock input. All inputs except DQs and DMs are sampled on the rising edge
of CLK.
CKE
Input
Level
Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
initiates either the Power Down mode, Suspend mode, or the Self Refresh mode.
CS
Input
Pulse
Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
RAS, CAS
WE
Input
Pulse
Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
DQS
Input/
Output
Pulse
Active High Active on both edges for data input and output.
Center aligned to input data
Edge aligned to output data
A0 - A11
Input
Level
—
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)
when sampled at the rising clock edge.CAn depends from the SDRAM organization:
8M x 8 SDRAM CAn = CA8 (Page Length = 512 bits)
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will be precharged
simultaneously regardless of state of BA0 and BA1.
BA0,
BA1
Input
Level
—
Selects which bank is to be active.
DQx
Input/
Output
Level
—
Data Input/Output pins operate in the same manner as on conventional DRAMs.
DM
Input
Pulse
Active High In Write mode, DM has a latency of zero and operates as a word mask by allowing input
data to be written if it is low but blocks the write operation if is high.
VDD, VSS Supply
Power and ground for the input buffers and the core logic.
VDDQ
VSSQ
Supply
—
—
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
VREF
Input
Level
—
SSTL Reference Voltage for Inputs
V58C265804S Rev. 1.3 January 2000
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MOSEL VITELIC
Functional Description
■ Power-Up Sequence
The following sequence is required for POWER UP.
1. Apply power and attempt to maintain CKE at a low stately other inputs may be undefined.)
- Apply VDD before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as VTT & Vref.
2. Start clock and maintain stable condition for a minimum of 200us.
3. The minimum of 200us after stable power and clock (CLK, CLK), apply NOP & take CKE high.
4. Precharge all banks.
5. Issue EMRS to enable DLL.(To issue “DLL Enable” command, provide “Low” to A0, “High” to BA0
and “Low” to all of the rest address pins, A1~A11 and BA1)
6. Issue a mode register set command for “DLL reset”. The additional 200 cycles of clock input is
required to lock the DLL. (To issue DLL reset command, provide “High” to A8 and “Low” to BA0)
7. Issue precharge commands for all banks of the device.
8. Issue 2 or more auto-refresh commands.
9. Issue a mode register set command to initialize device operation.
Note1 Every “DLL enable” command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it,
the additional 200 cycles of clock input is required to lock the DLL after enabling DLL.
Power up Sequence & Auto Refresh(CBR)
0
CK, CK
1
2
4
5
6
7
8
9
10
••
••
11
12
13
14
••
tRFC
tRP
2 Clock min.
2 Clock min.
Command
3
precharge
ALL Banks
EMRS
MRS
DLL Reset
4
5
6
200 µS Power up
to 1st command
precharge
ALL Banks
1st Auto
Refresh
16
17
18
19
••
tRFC
••
••
15
2nd Auto
Refresh
••
••
2 Clock min.
Mode
Register Set
Any
Command
min. 200 Cycle
7
8
8
Extended Mode Register Set (EMRS)
The extended mode register stores the data for enabling or disabling DLL. The default value of the extended mode register is not defined, therefore the extended mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and
high on BA0 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into
the extended mode register). The state of address pins A0 ~ A11 and BA1 in the same cycle as CS, RAS,
CAS and WE low is written in the extended mode register. Two clock cycles are required to complete the
write operation in the extended mode register. The mode register contents can be changed using the same
command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used
for DLL enable or disable. “High” on BA0 is used for EMRS. All the other address pins except A0 and BA0
must be set to low for proper EMRS operation. A1 is used at EMRS to indicate I/O strength A1 = 0 full strength,
A1 = 1 half strength. Refer to the table for specific codes.
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MOSEL VITELIC
Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs
CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to
make DDR SDRAM useful for a variety of different applications. The default value of the mode register is not
defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation.
The mode register is written by asserting low on CS, RAS, CAS, WE and BA0 (The DDR SDRAM should be
in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins
A0 ~ A11 in the same cycle as CS, RAS, CAS, WE and BA0 low is written in the mode register. Two clock
cycles are required to meet tMRD spec. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode
uses A3, CAS latency (read latency from column address) uses A4 ~ A6. A7 is a Mosel Vitelic specific test
mode during production test. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer
to the table for specific codes for various burst length, addressing modes and CAS latencies.
1. MRS can be issued only at all banks precharge state.
2. Minimum tRP is required to issue MRS command.
BA1
BA 0
0
MRS
0
MRS
A 11
A 10
A9
A8
A7
A6
A5
A4
A3
RFU : Must be set "0"
RFU
DLL
TM
CAS Latency
BT
A1
A0
I/O
DLL
Burst Length
Address Bus
Extended Mode Register
Mode Register
A8
DLL Reset
A7
mode
A3
Burst Type
A1
0
No
0
Normal
0
Sequential
0
Full
0
Enable
1
Yes
1
Test
1
Interleave
1
Half
1
Disable
An ~ A 0
A6 A5
A4
Latency
A2
A1
A0
Reserve
0
0
0
2
0
1
1
3
1
0
0
Latency
Sequential
Interleave
0
Reserve
Reserve
0
1
2
2
0
1
0
4
4
Reserve
0
1
1
8
8
0
(Existing)MRS Cycle
0
0
0
Reserve
1
Extended Funtions(EMRS)
0
0
1
0
1
0
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
I/O Strength
Burst Length
CAS Latency
BA 0
A2
1
0
1
Reserve
1
0
0
Reserve
Reserve
1
1
0
2.5
1
0
1
Reserve
Reserve
1
1
1
Reserve
1
1
0
Reserve
Reserve
1
1
1
Reserve
Reserve
Mode Register Set
0
1
2
3
4
5
CK, CK
*1
Mode
Register Set
Precharge
All Banks
Command
tCK
V58C265804S Rev. 1.3 January 2000
tRP *2
Any
Command
tMRD
6
6
7
8
A0
DLL Enable
V58C265804S
MOSEL VITELIC
Mode Register Set Timing
T0
T1
T2
T3
T4
T5
T7
T8
T9
tMRD
tRP
tCK
T6
CK, CK
Pre- All
Command
MRS/EMRS
ANY
Mode Register set (MRS) or Extended Mode Register Set (EMRS) can be issued only when all banks are in the idle state.
If a MRS command is issued to reset the DLL, then an additional 200 clocks must occur prior to issuing any new command
to allow time for the DLL to lock onto the clock.
Burst Mode Operation
Burst Mode Operation is used to provide a constant flow of data to memory locations (Write cycle), or from
memory locations (Read cycle). Two parameters define how the burst mode will operate: burst sequence and
burst length. These parameters are programmable and are determined by address bits A0—A3 during the
Mode Register Set command. Burst type defines the sequence in which the burst data will be delivered or
stored to the SDRAM. Two types of burst sequence are supported: sequential and interleave. The burst
length controls the number of bits that will be output after a Read command, or the number of bits to be input
after a Write command. The burst length can be programmed to values of 2, 4, or 8. See the Burst Length
and Sequence table below for programming information.
Burst Length and Sequence
Burst Length
Starting Length (A2, A1, A0)
Sequential Mode
Interleave Mode
xx0
0, 1
0, 1
xx1
1, 0
1, 0
x00
0, 1, 2, 3
0, 1, 2, 3
x01
1, 2, 3, 0
1, 0, 3, 2
x10
2, 3, 0, 1
2, 3, 0, 1
x11
3, 0, 1, 2
3, 2, 1, 0
000
0,1, 2, 3, 4, 5, 6, 7
0,1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
011
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 0, 1, 2, 3, 4, 5, 6
6, 7, 4, 5, 2, 3, 0, 1
111
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
2
4
8
V58C265804S Rev. 1.3 January 2000
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MOSEL VITELIC
Bank Activate Command
The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising
edge of the clock. The DDR SDRAM has four independent banks, so two Bank Select addresses (BA0 and
BA1) are supported. The Bank Activate command must be applied before any Read or Write operation can
be executed. The delay from the Bank Activate command to the first Read or Write command must meet or
exceed the minimum RAS to CAS delay time (tRCD min). Once a bank has been activated, it must be precharged before another Bank Activate command can be applied to the same bank. The minimum time interval
between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay
time (tRRD min).
Bank Activation Timing
(CAS Latency = 2; Burst Length = Any)
T0
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
Tn+4
Tn+5
tRC
tRP(min)
tRAS(min)
tRRD(min)
tRCD(min)
CK, CK
BA/Address
Bank/Row
Bank/Col
Bank
Bank/Row
Bank/Row
Command
Activate/A
Read/A
Pre/A
Activate/A
Activate/B
Begin Precharge Bank A
Read Operation
With the DLL enabled, all devices operating at the same frequency within a system are ensured to have
the same timing relationship between DQ and DQS relative to the CK input regardless of device density, process variation, or technology generation.
The data strobe signal (DQS) is driven off chip simultaneously with the output data (DQ) during each read
cycle. The same internal clock phase is used to drive both the output data and data strobe signal off chip to
minimize skew between data strobe and output data. This internal clock phase is nominally aligned to the
input differential clock (CK, CK) by the on-chip DLL. Therefore, when the DLL is enabled and the clock frequency is within the specified range for proper DLL operation, the data strobe (DQS), output data (DQ), and
the system clock (CK) are all nominally aligned.
Since the data strobe and output data are tightly coupled in the system, the data strobe signal may be delayed and used to latch the output data into the receiving device. The tolerance for skew between DQS and
DQ (tDQSQ) is tighter than that possible for CK to DQ (tAC) or DQS to CK (tDQSCK).
V58C265804S Rev. 1.3 January 2000
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V58C265804S
MOSEL VITELIC
Output Data (DQ) and Data Strobe (DQS) Timing Relative to the Clock (CK)
During Read Cycles
(CAS Latency = 2.5; Burst Length = 4)
T0
T1
T2
T3
T4
CK, CK
Command
READ
NOP
NOP
NOP
NOP
tDQSCK(max)
tDQSCK(min)
tDQSCK
DQS
tAC(max)
tAC(min)
tAC
D0
DQ
D1
D2
D3
The minimum time during which the output data (DQ) is valid is critical for the receiving device (i.e., a memory controller device). This also applies to the data strobe during the read cycle since it is tightly coupled to
the output data. The minimum data output valid time (tDV) and minimum data strobe valid time (tDQSV) are derived from the minimum clock high/low time minus a margin for variation in data access and hold time due to
DLL jitter and power supply noise.
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V58C265804S
MOSEL VITELIC
Output Data and Data Strobe Valid Window for DDR Read Cycles
(CAS Latency = 2; Burst Length = 2)
T0
T1
T2
T3
T4
CK, CK
Command
READ
NOP
NOP
NOP
DQS
tDQSV(min)
D0
DQ
D1
tDV(min)
Read Preamble and Postamble Operation
Prior to a burst of read data and given that the controller is not currently in burst read mode, the data strobe
signal (DQS), must transition from Hi-Z to a valid logic low. The is referred to as the data strobe “read preamble” (tRPRE). This transition from Hi-Z to logic low nominally happens one clock cycle prior to the first edge of
valid data.
Once the burst of read data is concluded and given that no subsequent burst read operations are initiated,
the data strobe signal (DQS) transitions from a logic low level back to Hi-Z. This is referred to as the data
strobe “read postamble” (tRPST). This transition happens nominally one-half clock period after the last edge of
valid data.
Consecutive or “gapless” burst read operations are possible from the same DDR SDRAM device with no
requirement for a data strobe “read” preamble or postamble in between the groups of burst data. The data
strobe read preamble is required before the DDR device drives the first output data off chip. Similarly, the
data strobe postamble is initiated when the device stops driving DQ data at the termination of read burst cycles.
V58C265804S Rev. 1.3 January 2000
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MOSEL VITELIC
Data Strobe Preamble and Postamble Timings for DDR Read Cycles
(CAS Latency = 2; Burst Length = 2)
T0
T1
T2
T3
T4
CK, CK
READ
Command
NOP
NOP
NOP
tRPRE(max)
tRPRE(min)
tRPST(min)
DQS
tRPST(max)
tDQSQ(min)
D0
DQ
D1
tDQSQ(max)
Consecutive Burst Read Operation and Effects on the Data Strobe Preamble and Postamble
Burst Read Operation (CAS Latency = 2; Burst Length = 4)
CK, CK
Command
ReadA
NOP
ReadB
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS
D0A D1A D2A D3A D0B D1B D2B D3B
DQ
Burst Read Operation (CAS Latency = 2; Burst Length = 4)
CK, CK
Command
ReadA
NOP
NOP
ReadB
NOP
NOP
NOP
DQS
DQ
V58C265804S Rev. 1.3 January 2000
D0A D1A D2A D3A
11
D0B D1B D2B D3B
V58C265804S
MOSEL VITELIC
Auto Precharge Operation
The Auto Precharge operation can be issued by having column address A10 high when a Read or Write
command is issued. If A10 is low when a Read or Write command is issued, then normal Read or Write burst
operation is executed and the bank remains active at the completion of the burst sequence. When the Auto
Precharge command is activated, the active bank automatically begins to precharge at the earliest possible
moment during the Read or Write cycle once tRAS(min) is satisfied.
Read with Auto Precharge
If a Read with Auto Precharge command is initiated, the DDR SDRAM will enter the precharge operation
N-clock cycles measured from the last data of the burst read cycle where N is equal to the CAS latency programmed into the device. If a Read with autoprecharge command is issued before tRAS(min) is satisfied, the
precharge operation will be delayed until that time when tRAS(min) is met. Once the autoprecharge operation has begun, the bank cannot be reactivated until the minimum precharge time (tRP) has been satisfied.
Read with Autoprecharge Timing
(CAS Latency = 2; Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
tRAS(min)
T7
T8
T9
tRP(min)
CK, CK
Command
BA
NOP
R w/AP
NOP
NOP
NOP
NOP
BA
NOP
DQS
D0
DQ
D1
D2
D3
Begin Autoprecharge
Earliest Bank A reactivate
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MOSEL VITELIC
Read with Autoprecharge Timing as a Function of CAS Latency
(CAS Latency = 2, 2.5, 3; Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
tRAS(min)
T7
T8
T9
NOP
NOP
tRP(min)
CK, CK
Command
BA
NOP
NOP
RAP
NOP
NOP
NOP
BA
DQS
D0
DQ
D1
D2
D3
1
CAS Latency=2
DQS
D0
DQ
D1
D2
D3
CAS Latency=2.5
DQS
D0
DQ
D1
D2
CAS Latency=3
Begin Autoprecharge
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D3
V58C265804S
MOSEL VITELIC
Precharge Timing During Read Operation
For the earliest possible Precharge command without interrupting a Read burst, the Precharge command
may be issued on the rising clock edge which is CAS latency (CL) clock cycles before the end of the Read
burst. A new Bank Activate (BA) command may be issued to the same bank after the RAS precharge time
(tRP). A Precharge command can not be issued until tRAS(min) is satisfied.
Read with Precharge Timing as a Function of CAS Latency
(CAS Latency = 2, 2.5, 3; Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
tRAS(min)
T7
T8
T9
NOP
NOP
tRP(min)
CK, CK
Command
BA
NOP
NOP
Read
NOP
PreA
NOP
BA
DQS
D0
DQ
D1
D2
D3
CAS Latency=2
DQS
D0
DQ
D1
D2
D3
CAS Latency=2.5
DQS
D0
DQ
D1
D2
CAS Latency=3
V58C265804S Rev. 1.3 January 2000
14
D3
V58C265804S
MOSEL VITELIC
Burst Stop Command
The Burst Stop command is valid only during burst read cycles and is initiated by having RAS and CAS
high with CS and WE low at the rising edge of the clock. When the Burst Stop command is issued during a
burst Read cycle, both the output data (DQ) and data strobe (DQS) go to a high impedance state after a delay
(LBST) equal to the CAS latency programmed into the device. If the Burst Stop command is issued during a
burst Write cycle, the command will be treated as a NOP command.
Read Terminated by Burst Stop Command Timing
(CAS Latency = 2, 2.5, 3; Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
CK, CK
Command
Read
BST
NOP
NOP
NOP
LBST
DQS
CAS Latency = 2
D0
DQ
D1
LBST
DQS
CAS Latency = 2.5
D0
DQ
D1
LBST
DQS
CAS Latency = 3
D0
DQ
V58C265804S Rev. 1.3 January 2000
15
D1
NOP
V58C265804S
MOSEL VITELIC
Read Interrupted by a Precharge
A Burst Read operation can be interrupted by a precharge of the same bank. The Precharge command to
Output Disable latency is equivalent to the CAS latency.
Read Interrupted by a Precharge Timing
(CAS Latency = 2, 2.5, 3; Burst Length = 8)
T0
T1
T2
T3
T4
T5
T6
tRAS(min)
T7
T8
T9
NOP
NOP
tRP(min)
CK, CK
Command
BA
NOP
NOP
Read
NOP
PreA
NOP
BA
DQS
D0
DQ
D1
D2
D3
CAS Latency=2
DQS
D0
DQ
D1
D2
D3
CAS Latency=2.5
DQS
D0
DQ
D1
D2
D3
CAS Latency=3
Burst Write Operation
The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising
edge of the clock. The address inputs determine the starting column address. The memory controller is required to provide an input data strobe (DQS) to the DDR SDRAM to strobe or latch the input data (DQ) and
data mask (DM) into the device. During Write cycles, the data strobe applied to the DDR SDRAM is required
to be nominally centered within the data (DQ) and data mask (DM) valid windows. The data strobe must be
driven high nominally one clock after the write command has been registered. Timing parameters tDQSS(min)
and tDQSS(max) define the allowable window when the data strobe must be driven high.
Input data for the first Burst Write cycle must be applied one clock cycle after the Write command is
registered into the device (WL=1). The input data valid window is nominally centered around the midpoint of
the data strobe signal. The data window is defined by DQ to DQS setup time (tQDQSS) and DQ to DQS hold
time (tQDQSH). All data inputs must be supplied on each rising and falling edge of the data strobe until the burst
length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored.
Write Preamble and Postamble Operation
Prior to a burst of write data and given that the controller is not currently in burst write mode, the data strobe
signal (DQS), must transition from Hi-Z to a valid logic low. This is referred to as the data strobe “write preamble”.
This transition from Hi-Z to logic low nominally happens on the falling edge of the clock after the write command has been registered by the device. The preamble is explicitly defined by a setup time (tWPRES(min)) and
hold time (tWPREH(min)) referenced to the first falling edge of CK after the write command.
V58C265804S Rev. 1.3 January 2000
16
V58C265804S
MOSEL VITELIC
Burst Write Timing
(CAS Latency = Any; Burst Length = 4)
T0
T1
T2
T3
T4
CK, CK
WRITE
Command
NOP
NOP
NOP
tWPREH
tWPST
tWPRES
tQDQSS
tDQSS
DQS(nom)
tQDQSH
tQDQSS
D0
DQ(nom)
D1
tQDQSH
D2
D3
tWPREH(min)
tWPRES(min)
DQS(min)
tDQSS(min)
D0
DQ(min)
D1
D2
D3
D0
D1
D2
tWPRES(max)
tWPREH(max)
DQS(max)
tDQSS(max)
DQ(max)
D3
Once the burst of write data is concluded and given that no subsequent burst write operations are initiated,
the data strobe signal (DQS) transitions from a logic low level back to Hi-Z. This is referred to as the data
strobe “write postamble”. This transition happens nominally one-half clock period after the last data of the
burst cycle is latched into the device.
V58C265804S Rev. 1.3 January 2000
17
V58C265804S
MOSEL VITELIC
Write Interrupted by a Precharge
A Burst Write can be interrupted before completion of the burst by a Precharge command, with the only
restriction being that the interval that separates the commands be at least one clock cycle. When the previous
burst is interrupted, the remaining addresses are overridden by the new address and data will be written into
the device until the programmed burst length is satisfied.
Write Interrupted by a Precharge Timing
(CAS Latency = 2; Burst Length = 8)
T0
T1
T2
T3
T4
T5
T6
PreA
NOP
tWR
NOP
T7
T8
T9
NOP
NOP
T10
T11
T12
CK, CK
WriteA
Command
NOP
NOP
NOP
NOP
NOP
DQS
D0 D1 D2 D3 D4 D5
DQ
DM
Data is masked
by DM input
Data is masked
by Precharge Command
DQS input ignored
Write with Auto Precharge
If A10 is high when a Write command is issued, the Write with auto Precharge function is performed. Any
new command to the same bank should not be issued until the internal precharge is completed. The internal
precharge begins after keeping tWR (min.).
Write with Auto Precharge Timing
(CAS Latency = Any; Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
T7
tRAS(min)
T8
T9
tRP(min)
CK, CK
Command
BA
NOP
NOP
WAP
NOP
NOP
NOP
NOP
NOP
tWR(min)
DQS
DQ
D0
D1
D2
D3
Begin Autoprecharge
V58C265804S Rev. 1.3 January 2000
18
BA
V58C265804S
MOSEL VITELIC
Precharge Timing During Write Operation
Precharge timing for Write operations in DRAMs requires enough time to satisfy the write recovery requirement. This is the time required by a DRAM sense amp to fully store the voltage level. For DDR SDRAMs, a
timing parameter (tWR) is used to indicate the required amount of time between the last valid write operation
and a Precharge command to the same bank.
The “write recovery” operation begins on the rising clock edge after the last DQS edge that is used to strobe
in the last valid write data. “Write recovery” is complete on the next rising clock edge that is used to strobe in
the Precharge command.
For the earliest possible Precharge command following a Write burst without interrupting the burst, the
minimum time for “write recovery” is 1.25 clock cycles. Maximum “write recovery” time is 1.75 clock cycles.
Write with Precharge Timing
(CAS Latency = Any; Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
T7
tRAS(min)
T8
T9
tRP(min)
CK, CK
Command
BA
NOP
NOP
Write
NOP
NOP
NOP
PreA
tWR(min)
DQS
D0
DQ
D1
D2
D3
tWR(max)
DQS
DQ
V58C265804S Rev. 1.3 January 2000
D0
D1
19
D2
D3
NOP
BA
V58C265804S
MOSEL VITELIC
Data Mask Function
The DDR SDRAM has a Data Mask function that is used in conjunction with the Write cycle, but not the
Read cycle. When the Data Mask is activated (DM high) during a Write operation, the Write is blocked (Mask
to Data Latency = 0).
When issued, the Data Mask must be referenced to both the rising and falling edges of Data Strobe.
Data Mask Timing
(CAS Latency = Any; Burst Length = 8)
T0
T1
T2
Write
NOP
T3
T4
T5
T6
T7
T8
T9
CK, CK
Command
NOP
NOP
NOP
NOP
tDMDQSS
NOP
NOP
tDMDQSS
DQS
tDMDQSH
D0
DQ
D1
D2
D3
D4
tDMDQSH
D5
D6
D7
DM
Burst Interruption
Read Interrupted by a Read
A Burst Read can be interrupted before completion of the burst by issuing a new Read command to any
bank. When the previous burst is interrupted, the remaining addresses are overridden with a full burst length
starting with the new address. The data from the first Read command continues to appear on the outputs until
the CAS latency from the interrupting Read command is satisfied. At this point, the data from the interrupting
Read command appears on the bus. Read commands can be issued on each rising edge of the system clock.
It is illegal to interrupt a Read with autoprecharge command with a Read command.
Read Interrupted by a Read Command Timing
(CAS Latency = 2; Burst Length = 4)
T0
T1
T2
ReadA
ReadB
T3
T4
T5
T6
T7
T8
CK, CK
Command
NOP
NOP
NOP
NOP
DQS
DQ
V58C265804S Rev. 1.3 January 2000
DA0 DA1 DB0 DB1 DB2 DB3
20
NOP
NOP
T9
V58C265804S
MOSEL VITELIC
Read Interrupted by a Write
To interrupt a Burst Read with a Write command, a Burst Stop command must be asserted to stop the burst
read operation and 3-state the DQ bus. Additionally, control of the DQS bus must be turned around to allow
the memory controller to drive the data strobe signal (DQS) into the DDR SDRAM for the write cycles. Once
the Burst Stop command has been issued, a Write command can not be issued until a minimum delay or
latency (LBST) has been satisfied. This latency is measured from the Burst Stop command and is equivalent
to the CAS latency programmed into the mode register. In instances where CAS latency is measured in half
clock cycles, the minimum delay (LBST) is rounded up to the next full clock cycle (i.e., if CL=2 then LBST=2, if
CL=2.5 then LBST=3). It is illegal to interrupt a Read with autoprecharge command with a Write command.
Read Interrupted by Burst Stop Command Followed by a Write Command Timing
(CAS Latency = 2; Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
Write
NOP
NOP
NOP
NOP
T9
CK, CK
Read
Command
BST
DQS
D0
DQ
D1
D0
D1
D2
D3
LBST
Write Interrupted by a Write
A Burst Write can be interrupted before completion by a new Write command to any bank. When the previous burst is interrupted, the remaining addresses are overridden with a full burst length starting with the new
address. The data from the first Write command continues to be input into the device until the Write Latency
of the interrupting Write command is satisfied (WL=1) At this point, the data from the interrupting Write command is input into the device. Write commands can be issued on each rising edge of the system clock. It is
illegal to interrupt a Write with autoprecharge command with a Write command.
Write Interrupted by a Write Command Timing
(CAS Latency = Any; Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
WriteA
WriteB
NOP
NOP
NOP
NOP
NOP
NOP
CK, CK
Command
DQS
DQ
DA0 DA1 DB0 DB1 DB2 DB3
DM
DM0 DM1 DM0 DM1 DM2 DM3
Write Latency
V58C265804S Rev. 1.3 January 2000
21
T9
V58C265804S
MOSEL VITELIC
Write Interrupted by a Read
A Burst Write can be interrupted by a Read command to any bank. If a burst write operation is interrupted
prior to the end of the burst operation, then the last two pieces of input data prior to the Read command must
be masked off with the data mask (DM) input pin to prevent invalid data from being written into the memory
array. Any data that is present on the DQ pins coincident with or following the Read command will be masked
off by the Read command and will not be written to the array. The memory controller must give up control of
both the DQ bus and the DQS bus at least one clock cycle before the read data appears on the outputs in
order to avoid contention. In order to avoid data contention within the device, a delay is required (tCDLR) from
the last valid data input before a Read command can be issued to the device. It is illegal to interrupt a Write
with autoprecharge command with a Read command.
Write Interrupted by a Read Command Timing
(CAS Latency = 2; Burst Length = 8)
T0
T1
T2
T3
T4
T5
T6
Read
NOP
NOP
T7
T8
T9
NOP
NOP
T10
T11
T12
CK, CK
Write
Command
NOP
NOP
tCDLR
NOP
NOP
NOP
DQS
D0 D1 D2 D3 D4 D5
DQ
D0 D 1 D 2 D3 D4 D 5 D 6 D7
DM
Data is masked
by DM input
Data is masked
by Read command
DQS input ignored
Auto Refresh
The Auto Refresh command is issued by having CS, RAS, and CAS held low with CKE and WE high at the
rising edge of the clock. All banks must be precharged and idle for a tRP(min) before the Auto Refresh command is applied. No control of the address pins is required once this cycle has started because of the internal
address counter. When the Auto Refresh cycle has completed, all banks will be in the idle state. A delay between the Auto Refresh command and the next Activate command or subsequent Auto Refresh command
must be greater than or equal to the tRFC(min). Commands may not be issued to the device once an Auto
Refresh cycle has begun. CS input must remain high during the refresh period or NOP commands must be
registered on each rising edge of the CK input until the refresh period is satisfied.
Auto Refresh Timing
T0
T1
T2
tRP
T3
T4
T5
T6
T7
tRFC
T8
T9
T10
T11
CK, CK
Pre All
Command
CKE
NOP
Auto Ref
High
V58C265804S Rev. 1.3 January 2000
22
ANY
V58C265804S
MOSEL VITELIC
Self Refresh
A self refresh command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising
edge of the clock (CK). Once the self refresh command is initiated, CKE must be held low to keep the device
in self refresh mode. During the self refresh operation, all inputs except CKE are ignored. The clock is internally disabled during self refresh operation to reduce power consumption. The self refresh is exited by supplying stable clock input before returning CKE high, asserting deselect or NOP command and then asserting
CKE high for longer than tSREX for locking of DLL. The auto refresh is required before self refresh entry and
after self refresh exit.
••
CK, CK
Command
••
Self
Refresh
••
Stable Clock
Auto
Refresh
••
NOP
••
••
CKE
••
tSREX
Power Down Mode
The power down mode is entered when CKE is low and exited when CKE is high. Once the power down
mode is initiated, all of the receiver circuits except clock, CKE and DLL circuit are gated off to reduce power
consumption. The both banks should be in idle state prior to entering the precharge power down mode and
CKE should be set high at least 1tck+tIS prior to row active command. During power down mode, refresh
operations cannot be performed, therefore the device cannot remain in power down mode longer than the
refresh period (tREF) of the device.
CK, CK
Command
••
Precharge
Precharge
power
down
Entry
••
precharge
power
down
Exit
••
••
Active
NOP
CKE
••
••
Active
power down
Entry
V58C265804S Rev. 1.3 January 2000
23
Active
power down
Exit
Read
V58C265804S
MOSEL VITELIC
SSTL_2 Input AC/DC Logic Levels
Symbol
Parameter
Min
Max
Units
Notes
1
VIH (DC)
DC Input Logic High
VREF+0.18
VDDQ+0.3
V
VIH (AC)
AC Input Logic High
VREF+0.35
—
V
VIL (DC)
DC Input Logic Low
–0.30
VREF–0.18
V
VIL (AC)
AC Input Logic Low
—
VREF–0.35
V
Note: 1. The relationship of the VDDQ of the driving device and the VREF of the receiving device is what determines noise margins.
However, in the case of VIH (max) (input overdrive), it is the VDDQ of the receiving device that is referenced. In the case where
a device is implemented such that supports SSTL_2 inputs but has no SSTL_2 outputs (e.g., a translator), and therefore no
VDDQ supply voltage connection, inputs must tolerate input overdrive to 3.0V (High corner VDDQ+300mV.)
SSTL_2 AC Test Conditions
Symbol
Parameter
VREF
Input Reference Voltage
VSWING (max)
SLEW
Value
Units
Notes
0.5*VDDQ
V
1
Input Signal Maximum Peak to Peak Swing
1.5
V
1, 2
Input Signal Minimum Slew Rate
1.0
V/ns
3
Notes: 1. Input waveform timing is referenced to the input signal crossing the VREF level applied to the device.
2. Compliant devices must still meet the VIH (AC) and VIL (AC) specifications under actual use conditions.
3. The 1 V/ns input signal minimum slew rate is to be maintained in the VIL max (AC) to VIL min (AC) range of the input
signal swing.
SSTL_2 Output Buffers
■
■
■
■
The input voltage provided to the receiver depends on three parameters:
VDDQ and current drive capabilities of the output buffer
Termination voltage
Termination resistance
VDDQ ≤ VDD
Class II SSTL_2 Output Buffer (Driver)
VTT = 0.5 *VDDQ
VDDQ
RT=50Ω
Output
Buffer
Receiver
VREF
VOUT
VIN
VSSQ
V58C265804S Rev. 1.3 January 2000
24
CLOAD = 30pF
V58C265804S
MOSEL VITELIC
DC CHARACTERISTICS
Recommended operating conditions Unless Otherwise Noted, TA=0 to 70°C
Parameter
Symbol
Test Condition
CAS
Latency
Version
–6
–7
–8
Unit
130
120
110
mA
Operating Current
(One Bank Active)
ICC1
Burst Length=2 tRC=tRC(min) IOL=0mA
Precharge Standby Current
in Power-Down Mode
ICC2P
CKE=VIL(max), tCC=10ns
20
mA
Precharge Standby Current
in Non Power-Down Mode
ICC2N
CKE=VIH(min), CS–VIH(min), tCC=10ns
Input signals are changed once during 20ns
45
mA
Active Standby Current
in Power-Down Mode
ICC3P
CKE=VIL(max), tCC=10ns
30
mA
Active Standby Current in Non- ICC3N
Power-Down Mode
CKE=VIH(min), CS–VIH(min), tCC=10ns
Input signals are changed once during 20ns
60
mA
Operating Current (Burst Mode) ICC4
IOL=0mA
Page Burst
All Banks activated
tCCD=2CKs
Refresh Current
ICC5
tRC=tRFC (min)
Self Refresh Current
ICC6
CKE=0.2V
V58C265804S Rev. 1.3 January 2000
25
2
140
130
120
mA
200
mA
2
mA
V58C265804S
MOSEL VITELIC
AC Characteristics (TA=0 to +70°C, VCC=2.5 ± 0.2V)
–8
Symbol
Parameter
–7
–6
Min.
Max.
Min.
Max.
Min.
Max.
Unit
CL = 2.0
10
15
8
15
7
15
ns
CL = 2.5
9
15
7.5
15
6.5
15
ns
CL = 3.0
8
15
7
15
6
15
ns
0.45
0.55
0.45
0.55
0.45
0.55
%
0.45
0.55
0.45
0.55
0.45
0.55
%
Clock Cycle
tCK
tCH
Clock Cycle
Clock Duty Cycle
tCL
Command Cycle
tRAS
Row Active Time (ACT->PRE)
56
-
49
-
42
-
ns
tRP
Row Precharge (PRE->ACT)
24
-
21
-
18
-
ns
tRC
Row Cycle (ACT->ACT)
80
-
70
-
60
-
ns
tRCD
RAS->CAS Delay (ACT->WR/RD)
24
-
21
-
18
-
ns
tRRD
RAS->RAS Delay (ACTa->ACTb)
16
-
14
-
12
-
ns
tRFC
Auto-Refresh (REF->REF/ACT)
88
-
77
-
66
-
ns
tREF
Refresh Cycle
-
64
-
64
-
64
ms
200
-
200
-
200
-
cycles
1
-
1
-
1
-
tRC
tSREX(DLL)
Self-Refresh Exit Delay
tSREX
tIS
CMD, ADDR->CLK Setup
0.15
-
0.15
-
0.15
-
tCK
tIH
CMD, ADDR->CLK Hold
0.15
-
0.15
-
0.15
-
tCK
tCCD
CAS->CAS Delay (Cola->Colb)
1
1
1
tCK
tMRD
Mode Register Set Delay
2
2
2
tCK
tPDENT
Power Down Entry Delay
1
1
1
tCK
Power Down Exit Delay
1
1
1
tCK
1
1
1
tCK
tPDEX(DLL)
tPDEX
Read Cycle
tAC
CLK->DQ Skew
-0.1
0.1
-0.1
0.1
-0.1
0.1
tCK
tDQSCK
CLK->DQS Skew
-0.1
0.1
-0.1
0.1
-0.1
0.1
tCK
tDQSQ
DQS->DQ Skew
-0.075
0.075
-0.075
0.075
-0.075
0.075
tCK
DQ/DQS Valid Window
0.3
-
0.3
-
0.3
-
tCK
tRPRE
Read DQS Preamble
0.9
1.1
0.9
1.1
0.9
1.1
tCK
tRPST
Read DQS Postamble
0.4
0.6
0.4
0.6
0.4
0.6
tCK
tDV
V58C265804S Rev. 1.3 January 2000
26
V58C265804S
MOSEL VITELIC
AC Characteristics (Continued) (TA=0 to +70°C, VCC=2.5 ± 0.2V)
–8
Symbol
Parameter
–7
–6
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Write Cycle
tWPRES
Write Preamble DQS Setup
0
0.5
0
0.5
0
0.5
tCK
tWPREH
Write Preamble DQS Hold
0.25
1.25
0.25
1.25
0.25
1.25
tCK
tDQSS
Write Preamble CLK->DQS (first)
0.75
1.25
0.75
1.25
0.75
1.25
tCK
tDSH
Write DQS High Width
0.4
0.6
0.4
0.6
0.4
0.6
tCK
tDSL
Write DQS Low Width
0.4
0.6
0.4
0.6
0.4
0.6
tCK
tWPST
Write Postamble DQS (last) -> Hi-Z
0.4
0.6
0.4
0.6
0.4
0.6
tCK
tDQSR
Write (last DIN) -> READ Command
1.25
1.75
1.25
1.75
1.25
1.75
tCK
tWR
Write (last DIN) -> PRE Command
1.25
1.75
1.25
1.75
1.25
1.75
tCK
tDS
DQ/DM -> DQS Setup (Data Setup)
0.075
-
0.075
-
0.075
-
tCK
tDH
DQ/DM -> DQS Hold (Data Hold)
0.075
-
0.075
-
0.075
-
tCK
tQDQSS
Date Input to Data Strobe Setup Time
0.075
-
0.075
-
0.075
-
tCK
tQDQSH
Date Input to Data Strobe Hold Time
0.075
-
0.075
-
0.075
-
tCK
tDMDSQS
Date Mask to Data Strobe Setup Time
0.075
-
0.075
-
0.075
-
tCK
tDMDQSH
Date Mask to Data Strobe Hold Time
0.075
-
0.075
-
0.075
-
tCK
V58C265804S Rev. 1.3 January 2000
27
V58C265804S
MOSEL VITELIC
Complete List of Operation Commands
DDR SDRAM Function Truth Table
CURRENT
STATE1
CS
RAS
CAS
WE
BS
Addr
ACTION
Idle
H
L
L
L
L
L
L
L
X
H
H
H
L
L
L
L
X
H
H
L
H
H
L
L
X
H
L
X
H
L
H
L
X
X
BS
BS
BS
BS
X
Op-
X
X
X
X
RA
AP
X
Code
NOP or Power Down
NOP
ILLEGAL2
ILLEGAL2
Row (&Bank) Active; Latch Row Address
NOP4
Auto-Refresh or Self-Refresh5
Mode reg. Access5
Row Active
H
L
L
L
L
L
L
X
H
H
H
L
L
L
X
H
L
L
H
H
L
X
X
H
L
H
L
X
X
X
BS
BS
BS
BS
X
X
X
CA,AP
CA,AP
X
AP
X
NOP
NOP
Begin Read; Latch CA; DetermineAP
Begin Write; Latch CA; DetermineAP
ILLEGAL2
Precharge
ILLEGAL
Read
H
L
L
L
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
L
L
H
H
L
X
H
L
H
L
H
L
X
X
X
BS
BS
BS
BS
BS
X
X
X
X
CA,AP
CA,AP
X
AP
X
NOP (Continue Burst to End;>Row Active)
NOP (Continue Burst to End;>Row Active)
ILLEGAL
Term Burst, New Read, DetermineAP3
Term Burst, Start Write, DetermineAP3
ILLEGAL to Same Bank, other Bank 0K if tRRD is Satisfied
Term Burst, Precharge
ILLEGAL
Write
H
L
L
L
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
L
L
H
H
L
X
H
L
H
L
H
L
X
X
X
BS
BS
BS
BS
BS
X
X
X
X
CA,AP
CA,AP
X
AP
X
NOP (Continue Burst to End;>Row Active)
NOP (Continue Burst to End;>Row Active)
ILLEGAL
Term Burst, Start Read, DetermineAP3
Term Burst, New Write, DetermineAP3
ILLEGAL2
Term Burst, Precharge3
ILLEGAL
Read
with
Auto
Precharge
H
L
L
L
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
L
L
H
H
L
X
H
L
H
L
H
L
X
X
X
BS
BS
X
BS
BS
X
X
X
X
X
X
X
AP
X
NOP (Continue Burst to End;> Precharge)
NOP (Continue Burst to End;> Precharge)
ILLEGAL2
ILLEGAL2
ILLEGAL
ILLEGAL2
ILLEGAL2
ILLEGAL
V58C265804S Rev. 1.3 January 2000
28
V58C265804S
MOSEL VITELIC
DDR SDRAM Function Truth Table (continued)
CURRENT
STATE1
CS
RAS
CAS
WE
BS
Addr
Write
with
Auto
Precharge
H
L
L
L
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
L
L
H
H
L
X
H
L
H
L
H
L
X
X
X
BS
BS
X
BS
BS
X
X
X
X
X
X
X
AP
X
NOP (Continue Burst to End;> Precharge)
NOP (Continue Burst to End;> Precharge)
ILLEGAL2
ILLEGAL2
ILLEGAL
ILLEGAL2
ILLEGAL2
ILLEGAL
Precharging
H
L
L
L
L
L
L
X
H
H
H
L
L
L
X
H
H
L
H
H
L
X
H
L
X
H
L
X
X
X
BS
BS
BS
BS
X
X
X
X
X
X
AP
X
NOP;> Idle after tRP
NOP;> Idle after tRP
ILLEGAL2
ILLEGAL2
(0K Provided tRP Satisfied) ACT
NOP4
ILLEGAL
Row
Activating
H
L
L
L
L
L
L
X
H
H
H
L
L
L
X
H
H
L
H
H
L
X
H
L
X
H
L
X
X
X
BS
BS
BS
BS
X
X
X
X
X
X
AP
X
NOP;> Row Active after tRCD
NOP;> Row Active after tRCD
ILLEGAL2
(0K if tRCD satisfied) Read/Write
(0K to other Bank if tRRD Satisfied) ACT
Precharge
ILLEGAL
Write
Recovering
H
L
L
L
L
L
L
X
H
H
H
L
L
L
X
H
H
L
H
H
L
X
H
L
X
H
L
X
X
X
BS
BS
BS
BS
X
X
X
X
X
X
AP
X
NOP
NOP
ILLEGAL2
ILLEGAL2
ILLEGAL2
ILLEGAL2
ILLEGAL
Refreshing
H
L
L
L
L
X
H
H
L
L
X
H
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NOP;> Idle after tRC
NOP;> Idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
Mode
Register
H
L
L
L
L
X
H
H
H
L
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
NOP
NOP
ILLEGAL
ILLEGAL
ILLEGAL
Accessing
V58C265804S Rev. 1.3 January 2000
29
ACTION
V58C265804S
MOSEL VITELIC
Clock Enable (CKE) Truth Table
CKE
n-1
CKE
n
CS
RAS
CAS
WE
Addr
Self-Refresh6
H
L
L
L
L
L
L
X
H
H
H
H
H
L
X
H
L
L
L
L
X
X
X
H
H
H
L
X
X
X
H
H
L
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
INVALID
EXIT Self-Refresh, Idle after tRC
EXIT Self-Refresh, Idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Self-Refresh)
Power-Down
H
L
L
L
L
L
L
X
H
H
H
H
H
L
X
H
L
L
L
L
X
X
X
H
H
H
L
X
X
X
H
H
L
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
INVALID
EXIT Power-Down, > Idle.
EXIT Power-Down, > Idle.
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Low-Power Mode)
All. Banks
Idle7
H
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
X
H
L
L
L
L
L
L
X
X
X
H
H
H
L
L
L
X
X
X
H
H
L
H
L
L
X
X
X
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
Refer to the function truth table
Enter Power- Down
Enter Power- Down
ILLEGAL
ILLEGAL
ILLEGAL
Enter Self-Refresh
ILLEGAL
NOP
Any State
other than
listed above
H
H
L
L
H
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Refer to the function truth table
Begin Clock Suspend next cycle8
Exit Clock Suspend next cycle8.
Maintain Clock Suspend.
STATE(n)
ACTION
Abbreviations:
RA = Row Address
CA = Column Address
BS = Bank Select Address
AP = Auto Precharge
Notes for SDRAM function truth table:
1.
2.
3.
4.
5.
6.
Current State is state of the bank determined by BS. All entries assume that CKE was active (HIGH) during the preceding clock cycle.
Illegal to bank in specified state; Function may be legal in the bank indicated by BS, depending on the state of that bank.
Must satisfy bus contention, bus turn around, and/or write recovery requirements.
NOP to bank precharging or in Idle state. The precharge bank(s) indicated by BS and AP.
Illegal if any bank is not Idle.
CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any
command other than EXIT.
7. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
8. Must be legal command as defined in the SDRAM function truth table.
V58C265804S Rev. 1.3 January 2000
30
V58C265804S Rev. 1.3 January 2000
31
Command
DM
DQ
ACT B
t RCDA
Rb
Ra
A0-A9
ACT A
Rb
Ra
A10, AP
DQS
Rb
Ra
A11
T3
BAb
t RRD
T2
BAa
High
T1
BA0, BA1
WE
CAS
RAS
CS
CKE
CLK
CLK
T0
RD A
Ca
BAa
T4
t RCDB
T5
Multibank Interleaving Read (CAS Latency = 2; Burst Length = 4)
T7
T8
T9
RD B
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
Cb
BAb
T6
T10
MOSEL VITELIC
V58C265804S
Multibank Interleaving Read
V58C265804S Rev. 1.3 January 2000
32
Command
DM
DQ
DQS
A0-A9
A10, AP
A11
BA0, BA1
WE
CAS
RAS
CS
CKE
CLK
CLK
High
T0
RD A
Ca
BAa
tCCD
T1
RD B
Cb
BAb
T2
Qa0 Qa1
T3
Qb0
T4
Qb1
Read Interrupted by a Read (CAS Latency = 2; Burst Length = 8)
Qb2 Qb3
T5
Qb4
T6
Qb5 Qb6
T7
Qb7
T8
MOSEL VITELIC
V58C265804S
Read Interrupted by a Read
V58C265804S Rev. 1.3 January 2000
33
Command
DM
DQ
DQS
ADDR (A0~A9, A11)
A10, AP
A11
BA
BA0, BA1
WE
CAS
RAS
CS
CKE
CLK
CLK
High
T0
Rb
Ra
ACT B
Rb
Ra
ACT A
Rb
Ra
T3
BAb
t RCD
t RRD
T2
BAa
T1
Da0
t RCDB
WR A
Ca
BAa
T4
Cb
BAb
T6
WR B
Da1 Da2 Da3
T5
Db0
Db1
T7
Db2
Db3
T8
MOSEL VITELIC
V58C265804S
Multi Bank Interleaving Write (@ BL = 4)
V58C265804S Rev. 1.3 January 2000
34
Qa1
Qa2
T4
Qa3
T5
Auto Precharge Start
tRP
T6
Ba
T7
Command
DM
DQ
DQS
A0-A9
RAP
Ca
Qa4
Qa5
Qa6
BA
Qa7
Ra
Ra
Qa0
T3
A10, AP
Ba
T2
Ra
High
T1
A11
BA0, BA1
WE
CAS
RAS
CS
CKE
CK
CK
T0
MOSEL VITELIC
V58C265804S
Auto Precharge After Read Burst (@ BL = 8, CL = 2)
V58C265804S Rev. 1.3 January 2000
35
Command
DM
DQ
DQS
A0-A9
A10, AP
A11
BA0, BA1
WE
CAS
RAS
CS
CKE
CK
CK
High
T0
WR
Ca
BAa
T1
Da0
Da1 Da2
T2
Da3
T3
Da4
Auto Precharge After Write Burst (Burst Length = 8)
Da5
T4
Da6
Da7
T5
t WPST + t WR
T6
T7
T9
Ra
Ra
Ra
BAa
BA
Auto Precharge Start
tRP
T8
MOSEL VITELIC
V58C265804S
Auto Precharge After Write Burst (@ BL=8)
V58C265804S
MOSEL VITELIC
PRE
Qa2
V58C265804S Rev. 1.3 January 2000
36
Command
DM
DQ
DQS
A0–A9
A10, AP
A11
BA0, BA1
WE
CAS
RAS
CS
CKE
CK
CK
T0
High
RD
Ca
BAa
T1
T2
T3
Qa0
Qa1
BAa
T4
Qa3
T5
Qa4
Qa5
T6
T7
Read Interrupted by Precharge (@BL = 8, CL = 2)
V58C265804S Rev. 1.3 January 2000
37
Command
DM
DQ
DQS
A0-A9
A10, AP
A11
BA0, BA1
WE
CAS
RAS
CS
CKE
CK
CK
High
T0
WR
Ca
BAa
T1
Da0
Da1 Da2
T2
tCDLR
T4
Cb
BAb
T5
RD
Da3 Da4 Da5 Da6 Da7
T3
Write Interrupted by a Read (CAS Latency = 2; Burst Length = 8)
T6
T8
T9
T10
Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb6 Qb7
T7
MOSEL VITELIC
V58C265804S
Write Interrupted by a Read (@BL=8, CL=2)
V58C265804S Rev. 1.3 January 2000
38
Command
DM
DQ
DQS
A0-A9
A10, AP
A11
BA0, BA1
WE
CAS
RAS
CS
CKE
CLK
CLK
High
T0
WR
Ca
BAa
T1
Da0
Write Burst (Burst Length = 4)
Da1
T2
Da2
Da3
T3
tWR
T4
PRE
BAa
T5
T6
MOSEL VITELIC
V58C265804S
Write Burst
V58C265804S Rev. 1.3 January 2000
39
Command
DM
DQ
DQS
ADDR (A0-A9, A11)
A10, AP
A11
BA
(BA0, BA1)
WE
CAS
RAS
CS
CKE
CLK
CLK
High
T0
T1
RD
Ca
BAa
T2
BST
T3
LBST
Qa0 Qa1
T4
T5
T7
T8
T9
T10
WR
t DQSS
Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb6 Qb7
Cb
BAb
T6
MOSEL VITELIC
V58C265804S
Read Interrupted by a Write and Burst Stop
V58C265804S Rev. 1.3 January 2000
40
Command
DM
DQ
DQS
A0-A9
A10, AP
A11
BA0, BA1
WE
CAS
RAS
CS
CKE
CK
CK
T0
High
WR
Ca
BAa
T1
Da0
Da1
T2
Da2
Da3
T3
Da4
Da5
T4
Data Mask Function During Burst Write Cycles (CAS Latency = 2; Burst Length = 8)
Da6
Da7
T5
T6
MOSEL VITELIC
V58C265804S
Data Mask Function (@BL=8) Only for Write
V58C265804S Rev. 1.3 January 2000
41
DQS
DM
DQ
A10
A9, A11
A8
A7
A1-A6
A0
BA1
BA0
WE
CAS
RAS
CS
CKE
CLK
CLK
200 µs min
T1
T2
Precharge all
Hi-Z
Hi-Z
T3
---DLL enable
High level is required
T0
T5
---DLL reset
200 clock min
T4
Power Up Sequence and Auto Refresh (CBR)
T7
---Precharge all
T6
T8
T10
T11
T12
T13
Minimum of two refresh cycles is required
T9
tRC
T14
T15
T16
T18
T19
---Any command
---Mode register set
Two clock minimum
T17
MOSEL VITELIC
V58C265804S
Power up Sequence and Auto Refresh (CBR)
V58C265804S Rev. 1.3 January 2000
42
DQS
DM
DQ
A0-A8
A10
A9, A11
BA0, BA1
WE
CAS
RAS
CS
CKE
CLK
CLK
Hi-Z
Hi-Z
High
T0
T1
tCK
tRP
T3
T4
Two clock minimum
T5
T7
---Extended mode register set command
---Any command
T6
---Mode register set command
ADRSKEY
---Precharge command all banks
T2
Mode Register Set Extended Mode Register Set
MOSEL VITELIC
V58C265804S
Mode Register/Extended Mode Register Set
V58C265804S
MOSEL VITELIC
Package Diagram
66-Pin TSOP-II (400 mil)
(0.71)
0.65TYP
0.65 0.08
NOTE
1. (
) IS REFERENCE
V58C265804S Rev. 1.3 January 2000
(10.76)
(R
0.
25
)
)
0.10 MAX
0.30 0.08
43
[
0.075 MAX
]
(R
0. 2
5
(R
0.
15
)
)
( 4•
)
0.125 +0.075
-0.035
1.20MAX
1.00 0.10
(10•)
0.05 MIN
0.210 0.05
0.665 0.05
(10•)
22.22 0.10
(R
0.1
5
(0.50)
(0.80)
#33
(1.50)
(10•)
0.45~0.75
(1.50)
(10•)
#1
11.76 0.20
(0.80)
#34
10.16 0.10
#66
(0.50)
Units : Millimeters
0.25TYP
0 ~8
MOSEL VITELIC
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© Copyright 2000, MOSEL VITELIC Inc.
The information in this document is subject to change without
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