DRAM MODULE KMM372F213CK/CS ABSOLUTE MAXIMUM RATINGS * Item Voltage on any pin relative VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol Rating Unit VIN, VOUT VCC Tstg PD IOS -0.5 to +4.6 -0.5 to +4.6 -55 to +125 9 50 V V °C W mA * Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to V SS, TA = 0 to 70°C) Item Supply Voltage Ground Input High Voltage Input Low Voltage Symbol Min Typ Max Unit VCC VSS VIH VIL 3.0 0 2.0 3.3 0 - 3.6 0 VCC+0.3*1 0.8 V V V V -0.3*2 *1 : VCC+1.3V/15ns, Pulse width is measured at VCC. *2 : -1.3V/15ns, Pulse width is measured at VSS. DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) Symbol Speed ICC1 KMM372F213CK/CS Unit Min Max -5 -6 - 990 900 mA mA ICC2 Don′t care - 100 mA ICC3 -5 -6 - 990 900 mA mA ICC4 -5 -6 - 810 720 mA mA ICC5 Don′t care - 30 mA ICC6 -5 -6 - 990 900 mA mA II(L) IO(L) Don′t care -25 -5 25 5 uA uA VOH VOL Don′t care 2.4 - 0.4 V V ICC1* : Operating Current * (RAS, CAS, Address cycling @tRC=min) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3* : RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min) ICC4* : EDO Mode Current * (RAS=VIL, CAS cycling : tHPC=min) ICC5 : Standby Current (RAS=CAS=W=Vcc-0.2V) ICC6* : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min) II(L) : Input Leakage Current (Any input 0≤VIN≤Vcc+0.3V, all other pins not under test=0 V) IO(L) : Output Leakage Current(Data Out is disabled, 0V≤VOUT≤Vcc) VOH : Output High Voltage Level (IOH = -2mA) VOL : Output Low Voltage Level (IOL = 2mA) * NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one hyper page mode cycle, tHPC. DRAM MODULE KMM372F213CK/CS CAPACITANCE (TA = 25°C, Vcc=3.3V, f = 1MHz) Item Symbol Input capacitance[A0-A10, B0] Input capacitance[W0, W2, OE0, OE2] Input capacitance[RAS0, RAS2] Input capacitance[CAS0, CAS4] Input/Output capacitance[DQ0 - 71] CIN1 CIN2 CIN3 CIN4 CDQ1 Min Max Unit - 20 20 45 20 20 pF pF pF pF pF AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=3.3V±0.3V. See notes 1,2.) Test condition : Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V, Output loading CL=100pF Parameter -5 Symbol Min Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z OE to output in Low-Z Output buffer turn-off delay from CAS Transition time(rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold time referenced to CAS Read command hold time referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data set-up time Data hold time Refresh period(2K Ref.) Write command set-up time CAS to W delay time RAS to W delay time tRC tRWC tRAC tCAC tAA tCLZ tOLZ tCEZ tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL tDS tDH tREF tWCS tCWD tRWD -6 Max 84 Min Unit 104 131 ns 155 50 Note Max ns 60 ns 3,4,10 18 20 ns 3,4,5,14 30 35 ns 3,10,14 8 8 ns 3,14 8 8 ns 3,14 8 18 8 20 ns 6,11,12,14 2 50 2 50 ns 2 30 50 40 10K 18 60 ns 10K 20 36 43 ns ns 14 ns 14 8 10K 10 10K ns 13 18 32 18 40 ns 4,14 13 20 13 25 ns 10,14 10 10 ns 14 5 5 ns 14 8 8 ns 14 0 0 ns 8 10 ns 30 35 ns 0 0 ns 14 0 0 ns 8 -2 -2 ns 8,14 10 10 ns 10 10 ns 18 20 ns 8 10 ns -2 -2 ns 9,14 13 15 ns 9,14 32 32 14 ms 0 0 ns 7 36 40 ns 7 71 83 ns 7,14 DRAM MODULE KMM372F213CK/CS AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=3.3V±0.3V. See notes 1,2.) Test condition : Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V, Output loading CL=100pF Parameter Column address to W delay time CAS precharge time to W delay time CAS set-up time(CAS-before-RAS refresh) CAS hold time(CAS-before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Hyper page cycle time Hyper page read-modify-write cycle time CAS precharge time(Hyper page cycle) RAS pulse width (Hyper page cycle) RAS hold time from CAS precharge OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time W to RAS precharge time(C-B-R refresh) W to RAS hold time(C-B-R refresh) Output data hold time Output buffer turn off delay time from RAS Output buffer turn off delay time from W W to data delay OE to CAS hold time CAS hold time to OE OE precharge time W pulse width(Hyper page cycle) Symbol tAWD tCPWD tCSR tCHR tRPC tCPA tHPC tHPRWC tCP tRASP tRHCP tOEA tOED tOEZ tOEH tWRP tWRH tDOH tREZ tWEZ tWED tOCH tCHO tOEP tWPE -5 Min -6 Max Min Max Unit Note 7 48 55 ns 53 60 ns 5 5 ns 14 8 8 ns 14 3 3 33 40 ns 14 ns 3,14 20 25 ns 12 68 77 ns 12 8 50 10 200K 35 60 40 18 18 5 ns 200K 20 20 18 5 20 ns ns 14 ns 14 ns 14 ns 6,11,14 13 15 ns 15 15 ns 14 8 8 ns 14 10 10 3 13 3 18 ns 14 3 15 ns 6.11.12 3 20 ns 6.11.14 20 20 ns 14 5 5 ns 5 5 ns 5 5 ns 5 5 ns Present Detect Read Cycle PDE to Valid PD bit PDE to PD bit Inactive tPD tPDOFF 10 2 7 2 10 ns 7 ns DRAM MODULE KMM372F213CK/CS NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. If tCWD≥tCWD(min), tRWD≥tRWD(min) and tAWD≥tAWD (min), then the cycle is a read-write cycle and the data output will contain data read from the selected address. If neither of the above conditions are satisfied, the condition of the data out is indeterminated. 8. Either tRCH or tRRH must be satisfied for a read cycle. 3. Measured with a load equivalent to 1 TTL loads and 100pF. Voh=2.0V and Vol=0.8V. 9. These parameters are referenced to the CAS leading edge in early write cycles and to the W leading edge in read-write cycles. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 5. Assumes that tRCD≥tRCD(max). 11. tCEZ(max), tREZ(max), tWEZ(max) and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced to output voltage level. 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter. They are included in the data sheet as electrical characteristics only. If tWCS≥tWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 12. If RAS goes to high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes to high before RAS high going , the open circuit condition of the output is achieved by RAS high going. 13. tASC≥tCP min 14. The timing skew from the DRAM to the DIMM resulted from the addition of buffers. DRAM MODULE KMM372F213CK/CS READ CYCLE tRC tRAS RAS VIL - tCSH tCRP CAS tRP VIH - tRCD tCRP tRSH VIH - tCAS VIL - tRAD tASR A VIH VIL - tRAH tRAL tASC tCAH ROW ADDRESS COLUMN ADDRESS tRCH tRCS W tRRH VIH VIL - tWEZ tCEZ tAA OE VIH - tOEZ tOEA VIL - tOLZ DQ VOH VOL - tRAC OPEN tCAC tCLZ tREZ DATA-OUT Don′t care Undefined DRAM MODULE KMM372F213CK/CS WRITE CYCLE ( EARLY WRITE ) NOTE : D OUT = OPEN tRC tRAS RAS tRP VIH VIL - tCSH tCRP CAS tRSH VIH - VIH VIL - tCRP tCAS VIL - tRAD tASR A tRCD tRAH tASC ROW ADDRESS tRAL tCAH COLUMN ADDRESS tCWL tRWL tWCS W OE VIH VIL - VIH VIL - tDS DQ tWCH tWP VIH VIL - tDH DATA-IN Don′t care Undefined DRAM MODULE KMM372F213CK/CS WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : D OUT = OPEN tRC tRAS RAS VIL - tCSH tCRP CAS tRP VIH - tRCD tRSH tCAS VIH - tCRP VIL - tRAD tRAL tASR A VIH VIL - tRAH ROW ADDRESS tASC tCAH COLUMN ADDRESS tCWL tRWL W OE tWP VIH VIL - VIH VIL - tOED tDS DQ VIH VIL - tOEH tDH DATA-IN Don′t care Undefined DRAM MODULE KMM372F213CK/CS READ - MODIFY - WRITE CYCLE tRWC tRAS RAS VIL - tCRP CAS tRP VIH - tRCD tRSH VIH - tCAS VIL - tRAD tASR tRAH tASC tCAH tCSH A VIH VIL - ROW ADDR COLUMN ADDRESS tAWD tRWL tCWD W tCWL VIH - tWP VIL - tRWD OE tOEA VIH VIL - tOLZ tCLZ tCAC tAA DQ VI/OH VI/OL - tOED tOEZ tRAC VALID DATA-OUT tDS tDH VALID DATA-IN Don′t care Undefined DRAM MODULE KMM372F213CK/CS HYPER PAGE READ CYCLE tRP tRASP RAS VIH VIL - ¡ó tCSH tCRP CAS VIL - tHPC tCP tCAS VIL - tHPC tCP tCAS tCP tCAS tCAS tRAD tASR A tRCD VIH - VIH - tRHCP tHPC tRAH tASC ROW ADDR tCAH tASC COLUMN ADDRESS tCAH COLUMN ADDRESS tASC tCAH COLUMN ADDR tASC tCAH tREZ COLUMN ADDRESS tRRH tRCS W tRCH VIH - tCPA VIL - tCAC tAA tCPA tCAC tAA OE VIH - tCPA tOCH tOEA tCHO tOEP tOEA VIL - tOEP tCAC tDOH tRAC DQ tCAC tAA tCAC tAA VOH VOL - VALID DATA-OUT tOLZ tCLZ tOEZ tOEA tOEZ VALID DATA-OUT tOEZ VALID DATA-OUT VALID DATA-OUT Don′t care Undefined DRAM MODULE KMM372F213CK/CS HYPER PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : D OUT = OPEN tRP tRASP RAS VIH - tRHCP VIL - ¡ó tHPC tCRP CAS tRCD tHPC tCP VIH - tCAS VIL - tRSH tCP tCAS tCAS tRAD ¡ó tCSH tASR A VIH VIL - tRAH tASC tCAH VIH - COLUMN ADDRESS tWCH COLUMN ADDRESS tWCS tWP tCAH ¡ó COLUMN ADDRESS tWCS ¡ó tWCH tWP VIL - tCWL VIL - VIH VIL - tCWL tRWL ¡ó VIH - ¡ó tDS DQ tASC tWCH tWP tCWL OE tCAH ¡ó ROW ADDR. tWCS W tASC tDH tDS tDH tDS tDH ¡ó VALID DATA-IN VALID DATA-IN ¡ó VALID DATA-IN Don′t care Undefined DRAM MODULE KMM372F213CK/CS HYPER PAGE READ-MODIFY-WRITE CYCLE RAS tCSH tHPRWC tRCD tCAS VIL - VIH VIL - tCAS tRAD tRAH ROW ADDR tRAL tCAH tASC tCAH tASC COL. ADDR COL. ADDR tRCS W tCRP tCP VIH - tASR A tRSH VIL - tCRP CAS tRWL tCWL tCWL VIH - tWP VIL - tWP tCWD tCWD tAWD tRWD OE tRP tRASP VIH - VIH - tAWD tCPWD tOEA tOEA VIL - tOED tOED tCAC tAA tDH tOEZ tCAC tAA tDS tDH tOEZ tDS tRAC DQ VI/OH VI/OL - tCLZ tCLZ tOLZ VALID DATA-OUT VALID DATA-IN tOLZ VALID DATA-OUT VALID DATA-IN Don′t care Undefined DRAM MODULE KMM372F213CK/CS HYPER PAGE READ AND WRITE MIXED CYCLE tRP tRASP RAS VIH - READ(tCAC) READ(tCPA) tHPC tHPC tCP tCP CAS VIH VIL - VIH VIL - tCAS tRAD tASR A tRAH tASC ROW ADDR tCAH COLUMN ADDRESS tRCS W READ(tAA) WRITE VIL - tCAS tRCS tCAH tASC COL. ADDR COLUMN ADDRESS tRCH tCAS tCAS tCAH tASC tHPC tCP tRCH tASC tCAH COL. ADDR tWCH tRCH tWCS VIH VIL - tWPE tCLZ tWED tCPA OE VIH VIL - tOEA tCAC tAA DQ VI/OH VI/OL - tWEZ tDH tWEZ tDS VALID VALID DATA-IN tREZ tAA tRAC VALID DATA-OUT DATA-OUT VALID DATA-OUT Don′t care Undefined DRAM MODULE KMM372F213CK/CS RAS - ONLY REFRESH CYCLE* NOTE : W, OE, DIN = Don′t care DOUT = OPEN tRC RAS VIH - tRP tRAS VIL - tRPC tCRP CAS VIH VIL - tASR A tCRP VIH VIL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE , A = Don′t care tRC tRP RAS VIH VIL - tRPC tCP CAS tRAS VIH - tRPC tCSR tCHR VIL - tWRP W tRP tWRH VIH VIL - tCEZ DQ VOH VOL - OPEN Don′t care Undefined * In RAS-only refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off. DRAM MODULE KMM372F213CK/CS HIDDEN REFRESH CYCLE ( READ ) tRC RAS tRAS VIH - tRP tRAS VIL - tCRP CAS tRC tRP tRCD tRSH tCHR VIH VIL - tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tRCS W tRRH tWRH tWRP VIH VIL - tAA OE VIH - tOEA VIL - tCEZ tOLZ tCAC tCLZ tRAC DQ VOH VOL - OPEN tREZ tWEZ tOEZ DATA-OUT Don′t care Undefined DRAM MODULE KMM372F213CK/CS HIDDEN REFRESH CYCLE ( WRITE ) NOTE : D OUT = OPEN tRC RAS tRAS VIH - tRP tRAS VIL - tCRP CAS tRC tRP tRCD tRSH tCHR VIH VIL - tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tWRH tWRP tWCS W OE VIH VIL - VIH VIL - tDS DQ tWCH tWP VIH VIL - tDH DATA-IN Don′t care Undefined DRAM MODULE KMM372F213CK/CS CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE tRP RAS CAS VIH - tRAS VIL VIH - tCPT tCSR tRSH tCHR tCAS VIL - tRAL tASC A VIH - W OE COLUMN ADDRESS VIL - READ CYCLE tWRP tWRH tRRH tAA tRCS tRCH tCAC VIH VIL VIH VIL - tOEA tCLZ VOH - DQ tCAH tOEZ DATA-OUT VOL - WRITE CYCLE W tCEZ tREZ tWRP tRWL tWRH tCWL VIH - tWCS tWCH VIL - tWP OE VIH VIL - tDS DQ tDH VIH DATA-IN VIL - READ-MODIFY-WRITE tWRP W tWRH tAWD tRCS tCWL tCWD VIH - tRWL tWP tCAC VIL - tAA tOEA OE VIH - tOED VIL - tCLZ DQ tOEZ tDH tDS VI/OH VI/OL VALID DATA-OUT VALID DATA-IN NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules. Don′t care Undefined tWEZ DRAM MODULE KMM372F213CK/CS CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Don′t care tRP RAS VIL - tRPS tRPC tRPC tCP VIH - CAS tRASS VIH - tCHS tCSR VIL - tCEZ VOH - DQ OPEN VOL - VIH - W VIL - tWRP tWRH TEST MODE IN CYCLE NOTE : OE , A = Don′t care tRC tRP RAS tRP tRAS VIH VIL - tRPC tRPC tCP CAS tCSR VIH - tWTS W tCHR VIL - tWTH VIH VIL - tCEZ DQ VOH VOL - OPEN Don′t care Undefined DRAM MODULE KMM372F213CK/CS PACKAGE DIMENSIONS Units : Inches (millimeters) 5.250 (133.350) 0.054 (1.372) 5.014 (127.350) R 0.079 (R 2.000) 0.700 (17.780) 0.157±0.004 (4.000±0.100) 0.118 (3.000) B A .118DIA±.004 (3.000DIA±.100) 0.250 (6.350) 0.350 (8.890) .450 (11.430) C 0.100Min (2.540Min) 1.000 (25.40) 0.118 (3.000) 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) 4.550 (115.57) ( Front view ) 0.200 Min (5.08Min) 0.100Max (2.54Max) TSOP 0.200Max (5.08Max) SOJ 0.050±0.0039 (1.270±0.10) 0.100 Min 0.250 (6.350) 0.250 (6.350) Detail A 0.039±.002 (1.000±.050) 0.123±.005 (3.125±.125) 0.123±.005 (3.125±.125) 0.079±.004 (2.000±.100) (2.540 Min) ( Back view ) 0.079±.0040 (2.000±.100) Detail B Tolerances : ±.005(.13) unless otherwise specified The used device is 2Mx8 DRAM with EDO mode, SOJ or TSOP II. (Forward) DRAM Part No. : KMM372F213CK/CS - KM48V2104CK and KM48V2104CS. 0.01Max (0.25 Max) 0.050 (1.270) Detail C