KS7221D VERTICAL DRIVER FOR CCD GENERAL DESCRIPTION 20-SSOP-225 The KS7221D is a Vertical CCD Driver LSI which is fabricated by CMOS process for high voltage FEATURES ORDERING INFORMATION ⋅ Include voltage source circuit for CCD image sensor. ⋅ Input voltage : 5V / 3.3V Device Package Operating Temperature KS7221D 20-SSOP-225 -20°C ~ + 85°C ⋅ Package : 20 SSOP BLOCK DIAGRAM GND 1 20 VHH XSUB 2 19 VSUB XV2 3 18 VEE XV1 4 17 ΦV2 XSG1 5 16 ΦV1 XV3 6 15 VME XSG3 7 14 ΦV3 XV4 8 13 ΦV4 VCP 9 12 VHH DCIN 10 11 DCOUT + - KS7221D VERTICAL DRIVER FOR CCD PIN DESCRIPTION Pin Symbol I/O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 GND Xsub XV2 XV1 XSG1 XV3 XSG3 XV4 VCP DCIN DCOUT VHH ΦV4 ΦV3 VME ΦV1 ΦV2 VEE Vsub VHH I I I I I I I I I O O O O O O - Description ABSOLUTE MAXIMUM RATINGS Characteristics Supply Voltage Input Voltage Output Voltage OP-Amp output Current Operating Temperature Storage Temperature Remark Ground control Output Control (Vsub) Output Control (ΦV2) Output Control (ΦV1) Output Control (ΦV1) Output Control (ΦV3) Output Control (ΦV3) Output Control (ΦV4) Power of amp OP-Amp input (internal pull-down resistor) OP-Amp output Power (15V) High Voltage Output (2 level :VME, VEE) High Voltage Output ( 3 level : VME, VEE, VHH) Power (0V) High Voltage Output (3 level : VME, VEE, VHH) High Voltage Output (2 level : VME, VEE) Power (-8.5V) High Voltage Output ( 2 level : VEE, VHH) Power (15V) ( Ta = 25°C ) Symbol VEE VHH VME VI VCP ΦV1, ΦV2, ΦV3, ΦV4, ΦVsub IOUT T OPR T STG Value Unit 0 ~ -10 -0.3 ~ VEE +35 VEE -0.3 ~ 3.0 -0.3 ~ VHH +0.3 -0.3 ~ VEE+35 VEE -0.3 ~ VHH +0.3 ±5 -25 ~ +85 -45 ~ +120 V mA °C LOGIC FUNCTION TABLE INPUT XV1,3 L H L H - XSG1,3 L L H H - OUTPUT XV2,4 L H - XSUB L H ΦV1, 3 VHH Z VME VEE - ΦV2, 4 VME VEE - VSUB VHH VEE KS7221D VERTICAL DRIVER FOR CCD AC CHARACTERISTICS ( VHH = 15V, VME = GND, VEE = - 8.5V ; Ta = 25°C ) Description DELAY TIME RISING TIME OUTPUT NOISE VOLTAGE Symbol TPLM TPMH TPLH TPML TPHM TPHL TTLM TTMH TTLH TTML TTHM TTHL VCLH, VCLL VCMH, VCML Test Condition Min Typ Max Unit NO LOAD (*1) NO LOAD (*1) NO LOAD (*1) NO LOAD (*1) NO LOAD (*1) NO LOAD (*1) VEE → VME (*1) VME → VHH (*1) VEE → VHH (*1) VME → VEE (*1) VHH → VME (*1) VHH → VME (*1) 10 10 10 10 10 10 400 400 10 200 400 10 40 30 40 100 100 60 700 650 50 300 600 50 70 70 100 200 180 100 930 930 100 500 820 100 ns - - 0.5 V (*2) (*1) REFER TIMING DIAGRAM (*2) REFER NOISE DIAGRAM DC CHARACTERISTICS ( VHH = 15V, VME = GND, VEE = -8.5, VCP = 22V ; Ta = 25°C ) Description Symbol Op-Amp Gain VHH VEE VCP VIH VIL II IDCIN IHH IME IEE IOL IOM1 IOM2 IOH IOSL IOSH G Gain Variation ∆G Supply Voltage Input Voltage High level input voltage Low level input voltage Input Current Operation Current Output Current Operation Current IVCP Test Conditon When VCP is used (*3) (*3) VIN = 0~5V (*3) VDCIN = 1.0V (*1) (*1) (*1) ΦV1~4 = -8.0V ΦV1~4 = -0.5V ΦV1.3 = 0.5V ΦV1.3 = 14.5V VSUB = -8.0V VSUB = 14.5V IOUT = -200µA Ta=-20 ~ 75°C (*2), Iout=-200µAVDCIN = 1.0 ~ 4.5V VDCIN = 1.0 ~ 4.5V IOUT = 0µA ( * 1 ) : Refer the test cirect. Shutter speed : 1/100000 SEC ( * 2 ) : Refer the characteristics of OP - AMP ( * 3 ) : XV1 ~ 4, XSG1, XSG3, XSUB PIN Min Typ Max 14.5 -9.5 VHH 2.3 -1.0 80 -8.5 25 9 12 x 4.0 15 -8.5 22 0.0 100 2.0 4.5 -6.5 37 -15 13.5 -18 18 -10.5 x 4.2 15.5 -7.5 23.5 1.2 1.0 140 3.5 5.0 -10 -12 -7 x 4.7 Unit -3 - +3 % 0.08 - 1.0 mA V µA mA KS7221D VERTICAL DRIVER FOR CCD TIMING DIAGRAM 5V 50% 50% XV1 ~ 4 GND 5V 50% 50% TPHM TTHM XSG1,3 GND TPMH TTMH VHH TPLM Φ V1,3 10% VME 10% 90% 10% 10% TTLM TPLM TPHL 90% 90% Φ V2,4 VEE 10% 10% 5V XSUB 50% 50% GND TTHL TPLH VHH TTLH TPHL 90% 90% VSUB VEE 10% 10% NOISE DIAGRAM VCMH VCML VM VCLH VCLL VL TPML 90% VEE VME TTML 90% TTLM TTHL KS7221D VERTICAL DRIVER FOR CCD TEST CIRCUIT R1 R2 R1 : 27 Ω R2 : 5 Ω C1 : 1500pF C2 : 3300pF R1 C1 C2 C2 C1 C1 C2 C2 500pF R1 R1 C1 VEE(-8.5V) VDD2(15V) VDD1(15V) 0V 20 19 18 17 16 15 14 13 12 11 8 9 10 KS7221D 1 2 3 4 5 6 7 VCC(22V) Timing Generator OP- AMP Gain Characteristics lout = 0uA 25.0 ( V ) Ta = - 20 ~ 75 ¡£C °C OUTPUT VOLTAGE (2.5 / div) 5.0 ( v ) INPUT VOLTAGE (0.5 / div) KS7221D VERTICAL DRIVER FOR CCD APPLICATION CIRCUIT 0.1µF / 35V + + VHH ( 15V ) 0.1µF / 35V VEE ( - 8.5 ) 1 GND VHH 20 0.1µF + 1µF T I M I N G XSUB 2 2 XSUB VSUB 19 XV2 3 3 XV2 VEE 18 XV1 4 4 XV1 ΦV2 17 Φ V2 G E N E R A T O R XSG1 5 5 XSG1 ΦV1 16 Φ V1 XV3 6 6 XV3 VME 15 XSG3 7 7 XSG3 ΦV3 14 Φ V3 XV4 8 8 XV4 ΦV4 13 Φ V4 9 VCP VHH 12 10 DCIN DCOUT 11 K S 7 2 2 1 D VSUB VDD (5V) 47KΩ 0.1µF 0.1µF 100KΩ * In case of DCOUT ≤ VHH - 1.0V , VCP PIN connects with VHH. Warning : When voltage is biased, You must keep this flow. if you don`t this flow, Negative voltage is applied to CCD image sensor`s SUB. 15V (VHH) t1 20% 0V (VME) 20% - 8.5V (VME) t2 _ t2 >_ 10ms * t1 > 1MΩ C C D KS7221D VERTICAL DRIVER FOR CCD PACKAGE DIMENSION unit : mm 20-SSOP-225 #20 #11 5.72 #10 + 0.10 1.50 _ + 0.20 0.15 - 0.05 1.85MAX 6.50 _ + 0.20 0.65 0.22 _ + 0.10 0.05MIN 0.10 MAX (0.30) 050 _ + 0.20 #1 4.40 _ + 0.20 6.40 _ + 0.30 0~ 8