Ver1.0 1 A1 PROs Ai1003 A1 PROs Vertical Clock Driver for Camera System Description Pin Configuration -. Ai1003 is a vertical clock driver with 3 levels of output voltage processed in a standard CMOS GND 16 VP1(+15V) 1 15 VSUB XSUB 2 Feature -. 3 Levels of output voltage, 15V, 0V, -8.5V -. 3.3V / 5V input voltage XV2 3 14 VSS(-8.5V) XV1 4 13 Vφ2 XSG1 5 12 Vφ1 XV3 6 11 VP0(0V) XSG2 7 10 Vφ3 XV4 8 9 Vφ4 16 PIN TSSOP ( Top View ) Absolute Maximum Ratings Rating Parameter Symbol Unit Min Typ Max VSS -10 0 V VP1 -0.3 VSS+30 V VP0 VSS-0.3 3 V VI -0.3 VP1+0.3 V VΦ1, VΦ3, VSUB VSS-0.3 VP1+0.3 V VΦ2, VΦ4 VSS-0.3 VP1+0.3 V Operating Ambient Temperature Ta -25 85 ℃ Storage Temperature Ts -45 125 ℃ Supply Voltage Input Voltage Output Voltage NOTE : Stress above those listed under “Absolute Maximum Rating” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for the extended periods of time may affect device reliability. 1 Ai1003 VP1(+15V) VSUB VSS(-8.5V) Vφ2 Vφ1 VP0(0V) Vφ3 Vφ4 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 GND XSUB XV2 XV1 XSG1 XV3 XSG2 XV4 Block Diagram Logic Truth Table Input XV1, 2 L L H H XSG1, 2 L H L H Output Vφ1,3 VP1 VP0 *Z VSS XSUB XV2, 4 L H Vφ2,4 VSUB VP0 VSS VP1 VSS L H * Z is high impedance. Pin Description No. Symbol I/O 1 2 GND - GND XSUB Input signal pin - control VSUB 3 XV2 I I 4 5 XV1 XSG1 I I 6 7 8 XV3 XSG2 I I Input signal pin - control Vφ3 XV4 Vφ4 I O O Input signal pin - control Vφ4 Output signal pin - 2 level ( VP0, VSS) Output signal pin - 3 level ( VP1, VP0, VSS) Power supply (0V) 9 10 11 12 13 14 15 16 Vφ3 VP0 Vφ1 Vφ2 VSS VSUB VP1 Description Input signal pin - control Vφ2 Input signal pin - control Vφ1 Input signal pin - control Vφ1 Input signal pin - control Vφ3 O Output signal pin - 3 level ( VP1, VP0, VSS) Output signal pin - 2 level ( VP0, VSS) Power supply (-8.5V) Output signal pin - 2 level ( VP1, VSS) Power supply (+15V) O O - 2 Ai1003 DC Characteristics (TA=25℃, VDD = 5V, VSS = -8.5V, VP0 =GND, VP1 = 15V) Value Parameter Power Supply Symbol Unit Min Typ Max VP1 14.5 15 15.5 V VSS -9.5 -8.5 -7.5 V 2.4 6 mA IP1 Supply Current ISS -8 IP0 Input Voltage VIH -4.2 0.6 -1 0 IOL 24 30 IOM2 -18 9 IOH IOSL IOSH (*1) mA V II IOM1 Output Current 2.5 2.3 VIL Input Current mA Condition 1.2 V 1 μA VIN=0~5V (*2) mA VΦ1~4 = -8.0V mA VΦ1~4 = -0.5V mA VΦ1,3 = -0.5V mA VΦ1,3 = -0.5V mA VSUB = -8.0V mA VSUB = 14.5V -25 13.5 -15 12 -25 18 -10 (*1) : Refer to the measurement circuit. Shutter speed : 1/40μs (*2) : XV1~4, XSG1,2 , XSUB pins 3 -7 Ai1003 Measurement Circuit R1 R1 C1 R1 : 27Ω R2 : 5Ω C1 : 1500pF C2 : 3300pF R2 C1 C2 C2 C2 C2 C1 500pF R1 R1 C1 VP1(15V) VSS(− 8.5V) 0V 16 15 14 13 12 11 10 9 6 7 8 Ai1003 1 2 3 4 5 Timing Generator 4 Ai1003 AC Characteristics (TA=25℃, VDD = 5V, VSS = -8.5V, VP0 =GND, VP1 = 15V) Value Parameter Symbol Delay Time Transition Time Output Noise Voltage Unit Condition Min Typ Max TPLM 100 140 190 ns TPMH 100 140 190 ns TPLH 110 150 210 ns TPML 190 250 310 ns TPHM 190 250 310 ns TPHL 150 220 270 ns TTLM 170 250 330 ns VSS → VP0 (*1) TTMH 190 240 310 ns VP0 → VP1 (*1) TTLH 100 150 210 ns VSS → VP1 (*1) TTML 100 200 310 ns VP0 → VSS (*1) TTHM 60 110 170 ns VP1 → VP0 (*1) TTHL 90 140 210 ns VP1 → VSS (*1) 0.5 V (*2) No Load (*1) VCLH, VCLL VCMH, VCML (*1) : Refer to Timing Diagram (*2) : Refer to Noise Diagram Noise Diagram VCMH VCML VM VCLH VCLL VL 5 Ai1003 Timing Diagram 5V XV1 ~ 4 XSG1, 2 50% 50% GND 5V 50% 50% TPHM GND TTHM TPMH 90% TTLM TPLM VΦ1,3 TTML TTMH VP1 VP0 TPML 10% 10% 90% 90% 10% VSS 10% TTHL TPHL TTLM TPLM VP0 90% 90% VΦ2,4 10% VSS 10% 5V 50% XSUB 50% GND TTHL TPLH VP1 VSUB VSS TTLH TPHL 90% 90% 10% 10% 6 Ai1003 Application Circuit VP1 (15V) VSS (− 8.5V) GND VP1 16 VSUB 15 VSS 14 VΦ2 13 VΦ2 VΦ1 12 VΦ1 VP0 11 VΦ3 10 VΦ3 VΦ4 9 VΦ4 T I M I N G XSUB 2 2 XSUB XV2 3 3 XV2 G E N E R A T O R XV1 1N4148 1μF 1 4 4 XV1 XSG1 5 5 XSG1 XV3 6 6 XV3 XSG2 7 7 XSG2 XV4 8 8 XV4 A i 1 0 0 3 0.1μF VSUB 100KΩ C C D * Warning : When voltage is biased, You must keep this flow. If you don’t keep this flow, Negative voltage is applied to CCD image sensor’s SUB. 15V (VP1) t1 20% 0V (VP0 ) 20% − 8.5V (VSS ) t2 * t1 ≥ t2 ≥ 10ms 7 Ai1003 Package Dimension ( Ai1003 : 16 PIN TSSOP ) E E1 e D D b y 12° (4X) A2 A1 C A θ L NOTE: 1. PACKAGE BODY SIZES EXCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS 2. TOLERANCE ±0.1mm UNLESS OTHERWISE SPECIFIED 3. COPLANARITY : 0.1mm 4. CONTROLLOMG DIMENSION IS MILLIMETER. CONVERTED INCH DIMENSIONS ARE NOT NECESSARILY EXACT. 5. FOLLOWED FROM JEDEC MO-153 DIMENSIONS IN MILLIMETERS DIMENSIONS IN INCHES SYMBOLS MIN NOM MAX MIN NOM MAX A - - 1.20 - - 0.048 A1 0.05 - 0.15 0.002 - 0.006 A2 0.80 1.00 1.05 0.031 0.039 0.041 b 0.19 - 0.30 0.007 - 0.012 C 0.09 - 0.20 0.004 - 0.008 D 4.90 5.00 5.10 0.193 0.197 0.201 E 6.20 6.40 6.60 0.244 0.252 0.260 E1 4.30 4.40 4.50 0.169 0.173 0.177 e - 0.65 - - 0.026 - L 0.45 0.60 0.75 0.018 0.024 0.030 y - - 0.10 - - 0.004 θ 0° - 8° 0 - 8° 8