CXD1267AN CCD Vertical Clock Driver Description The CXD1267AN is a vertical clock driver for CCD image sensors. This IC is the successor of the CXD1250N with attractive features. Power consumption is reduced approximately 30% for the CXD1267AN version. 20 pin SSOP (Plastic) Features 1) Substrate voltage (Vsub) generator is built-in. • Variable Vsub in the range of 4.0V to 18.5V. • Reduction of peripheral parts saves space. 2) Only two power supplies (+15V and –8.5V) are needed. 3) 3.3V clock interface is acceptable. 4) 20-pin SSOP package is used. 5) Low power consumption 90mW (CXD1267N) 62mW (CXD1267AN) approximately 30% reduction Appllications CCD cameras Structure CMOS Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VL 0 to –10 • Supply voltage VH VL – 0.3 to 2VL + 35 • Supply voltage VM VL – 0.3 to 3.0 • Input voltage VI VL – 0.3 to VH + 0.3 • Output voltage (V2, V4) MVφ VL – 0.3 to VM + 0.3 • Output voltage (V1, V3) HVφ VL – 0.3 to VH + 0.3 • Output voltage (VSHT) HHVφ VL – 0.3 to VH + 0.3 • Operational amplifier output current IDCOUT ±5 • Operating temperature Topr –25 to +85 • Storage temperature Tstg –40 to +125 Recommended Operating Conditions • Supply voltage VH • Supply voltage VM • Supply voltage VL • Input voltage (except for pin 3) VI • Operational amplifier input voltage VIOP • Operating temperature Topr V V V V V V V mA °C °C 14.5 to 15.5 0 –6.0 to –9.0 V V V 0 to 6.0 V 1.0 to 4.5 –20 to +75 V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94X38-PK CXD1267AN Block Diagram and Pin Configuration (Top View) 1 CPP1 CPP3 20 VH Charge Pump 2 3 4 CPP2 DCIN DCOUT XSHT VSHT XV2 7 XV1 XSG1 XV3 17 VM 13 Vφ3 12 Vφ4 11 8 XSG2 9 10 18 VL 16 Vφ2 15 Vφ1 14 5 6 19 XV4 Pin Description Pin No. Symbol I/O Description 1 CPP3 O Charge pump 2 VH — Power supply (15V) 3 DCIN I Operational amplifier input 4 XSHT I Output control (VSHT) 5 XV2 I Output control (Vφ2) 6 XV1 I Output control (Vφ1) 7 XSG1 I Output control (Vφ1) 8 XV3 I Output control (Vφ3) 9 XSG2 I Output control (Vφ3) 10 XV4 I Output control (Vφ4) 11 Vφ4 O High-voltage output (2 levels: VM, VL) 12 Vφ3 O High-voltage output (3 levels: VH, VM, VL) 13 VM — GND 14 Vφ1 O High-voltage output (3 levels: VH, VM, VL) 15 Vφ2 O High-voltage output (2 levels: VM, VL) 16 VL — Power supply (–8.5V) 17 VSHT O High-voltage output (2 levels: VH, VL) 18 DCOUT O Operational amplifier output 19 CPP2 — Charge pump 20 CPP1 — Charge pump –2– CXD1267AN Truth Table Input Output XV1, 3 XSG1, 2 XV2, 4 XSHT Vφ1, 3 Vφ2, 4 VSHT L L X X VH X X H L X X Z X X L H X X VM X X H H X X VL X X X X L X X VM X X X H X X VL X X X X L X X VH X X X H X X VL Electrical Characteristics DC Characteristics Item X: Don't care Z: High impedance (Unless otherwise specified, Ta = 25°C, VH = 15V, VM = GND, VL = –8.5V) Symbol Condition Min. Typ. Max. Unit High level input voltage VIH 2.3 — — V Low level input voltage VIL — — 1.3 V High level output voltage VOH IO = –20µA 14.9 15.0 — V Middle level output voltage VOM1 IO = 20µA — 0.0 0.1 V Middle level output voltage VOM2 IO = –20µA –0.1 0.0 — V Low level output voltage VOL IO = 20µA — –8.5 –8.4 V Charge pump output voltage VCPP3 –1 ≤ ICPP3 ≤ 0mA IDCOUT = 0mA, Ta = –20 to 75°C VIOP = 4.5V 20 — — V Input current II –1.0 0.0 1.0 µA Operating supply current IH VI = VL to 5V ∗1 — 1.4 2.0 mA Operating supply current IL ∗1 –6.0 –5.0 — mA Output current IOL Vφ1 to 4 = –8.0V 25 — — mA Output current IOM1 Vφ1 to 4 = –0.5V — — –10 mA Output current IOM2 Vφ1, 3 = 0.5V 9 — — mA Output current IOH Vφ1, 3 = 14.5V — — –12 mA Output current IOSL VSHT = –8.0V 12 — — mA Output current IOSH VSHT = 14.5V — — –7 mA Operational amplifier gain G — × 4.40 — Gain error ∆G IDCOUT = –200/+100µA Ta = –20 to 75°C∗2 IDCOUT = –200/+100µA VIOP = 1.0 to 4.5V –3 — +3 ∗1 See Measurement Circuit. Shutter speed: 1/10000. ∗2 See Operational Amplifier Gain Characteristic. Note) Current directions: + indicates the direction flowing to IC; – indicates the direction flowing from IC –3– % CXD1267AN Switching Characteristics Item (VH = 15V, VM = GND, VL = –8.5V) Symbol Conditions Min. Typ. Max. Unit TPLM ∗1 30 50 75 ns Propagation delay time TPMH ∗1 30 50 75 ns Propagation delay time TPLH ∗1 30 50 75 ns Propagation delay time TPML ∗1 50 80 120 ns Propagation delay time TPHM ∗1 50 80 120 ns Propagation delay time TPHL ∗1 50 80 120 ns Rise time TTLM 360 600 900 ns Rise time TTMH 330 550 770 ns Rise time TTLH 30 50 75 ns Fall time TTML 180 300 500 ns Fall time TTHM 330 550 770 ns Fall time TTHL VH → VM∗1 VH → VL∗1 24 40 60 ns Charge pump boosting time TC ∗2 — — 10 ms Output noise voltage VCLH ∗3 — — 0.5 V Output noise voltage VCLL ∗3 — — 0.5 V Output noise voltage VCMH ∗3 — — 0.5 V Output noise voltage VCML ∗3 — — 0.5 V Propagation delay time VL → VM∗1 VM → VH∗1 VL → VH∗1 VM → VL∗1 ∗1 See Response of Voltage Pulse. ∗2 CP1 = 0.1µF, CP2 = 0.1µF, VCPP3 = 20V; boosting time after all power supplies rose. ∗3 See Noise on a Waveform. Note) Each item is evaluated by Measurement Circuit. Notes on Operation (See Application Circuit.) 1. Be sure to protect against static electricity because this IC is MOS structure. 2. A bypass capacitor is connected between each power supply (VH, VL) and GND. 3. To prevent latch-up, use a capacitor of 0.1µF (CP1, CP2) for charge pump. Insert a silicon diode (D2) between CPP3 and CPP1. 4. In order to protect CCD image sensor, pre-clamp is requested prior to clamp by DCOUT. –4– CXD1267AN Measurement Circuit C1 R1 R1 R1; 27Ω R2; 5Ω C1; 1500pF C2; 3300pF C2 C2 C1 C1 C2 C2 500pF R1 R1 C1 R2 –8.5V 0V 0.1µF 20 19 18 17 15 16 14 13 12 11 7 8 9 10 CXD1267AN 1 2 3 4 6 5 0.1µF 15V 4.5V Timing generator (CXD1156Q) Operational Amplifier Gain Characteristics [V] 25.0 Ta = –20 to +75°C IDCOUT = 0µA At VH = 15V, VL = –8.5V Output voltage At VH = 14.5V, VL = –6.0V 2.5/div 0 0.5/div Input voltage 5.0 [V] Note) Operating amplifier maximum output voltage is restricted as shown in the formula below depending on supply voltage setting of VH and VL. Maximum output voltage VDCOUT (max) ≈ VH + | VL | – 0.8V For instance, when VH = 14.5V and VL = –6.0V, output voltage is saturated at approximately 19.7V as shown above figure. –5– CXD1267AN Response of Voltage Pulse VI (5V) XV1 to 4 50% GND VI (5V) 50% XSG1, 2 TPHM TTHM GND TPMH VH TTMH 90% TTLM Vφ1, 3 TTML TPLM TPML 10% VM 90% 10% VL TTML TTLM TPML TPLM VM 90% Vφ2, 4 10% VL VI (5V) 50% XSHT TTHL GND TPLH TPHL VH 90% TTLH VSHT 10% VL Noise on a Waveform VCMH VCML VM VCLH VCLL VL –6– CXD1267AN Application Circuit 15V 5V CP1 0.1µF 47kΩ 0kΩ D2 D1 0.1µF 1 CPP3 CPP1 20 2 VH CPP2 19 3 DCIN CP2 0.1µF D3 0.1µF D4 DCOUT 18 0.1µF C1 XSUB 4 C2 SUB VSHT 17 XSHT 0.1µF 1µF/35V R1 100kΩ R2 1MΩ XV2 5 XV2 VL 16 XV1 6 XV1 Vφ2 15 Vφ2 XSG1 7 XSG1 Vφ1 14 Vφ1 XV3 8 XV3 XSG2 9 XSG2 XV4 –8.5V 0.1µF VM 13 10 XV4 Vφ3 12 Vφ3 Vφ4 11 Vφ4 CXD1267AN CCD ∗ A peripheral circuit can be simplified by CCD image sensor. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Note with power-on sequence To protect CCD image sensor, rise two power supplies as follows. 15V t1 20% 0V 20% t2 –8.5V t2 ≥ t1 –7– CXD1267AN Package Outline Unit: mm 20PIN SSOP (Plastic) + 0.1 0.15 – 0.05 ∗6.5 ± 0.1 20 11 0.1 ± 0.1 10 + 0.1 0.22 – 0.05 0.10 M 0° to 10° 1.45 MAX 0.575 MAX 1.15 ± 0.1 0.65 0.5 ± 0.2 1 6.4 ± 0.2 ∗4.4 ± 0.1 0.10 NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING SONY CODE SSOP-20P-L071 LEAD TREATMENT EIAJ CODE SSOP020-P-0044-AN LEAD MATERIAL Cu ALLOY PACKAGE WEIGHT 0.1g JEDEC CODE –8–