SAMSUNG S6C0670

.
S6C0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
March. 2000.
Ver. 1.0
Prepared by:
Myoung-Sik, Suh
mail to: [email protected]
Contents in this document are subject to change without notice. No part of this document may be reproduced
or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express
written permission of LCD Driver IC Team.
S6C0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670 Specification Revision History
Version
2
Content
Date
0.0
Original
Aug.1999
1.0
“Resistor strings” , “CLK1 pulse high period”
Mar.2000
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670
CONTENTS
INTRODUCTION ................................................................................................................................................. 4
FEATURES ......................................................................................................................................................... 4
BLOCK DIAGRAM .............................................................................................................................................. 5
PIN ASSIGNMENTS............................................................................................................................................ 6
PIN DESCRIPTIONS........................................................................................................................................... 7
OPERATION DESCRIPTION .............................................................................................................................. 8
DISPLAY DATA TRANSFER............................................................................................................................ 8
EXTENSION OF OUTPUT ............................................................................................................................... 8
RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE................................................. 8
RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE............................................... 12
ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 26
RECOMMENDED OPERATION CONDITIONS ................................................................................................. 26
DC CHARACTERISTICS................................................................................................................................... 27
SINGLE EDGE AC CHARACTERISTICS.......................................................................................................... 28
DOUBLE EDGE AC CHARACTERISTICS ........................................................................................................ 29
SINGLE EDGE WAVEFORMS (VIH = 0.8 VDD1, VIL = 0.2 VDD1) ................................................................... 30
DOUBLE EDGE WAVEFORMS (VIH = 0.8 VDD1, VIL = 0.2 VDD1).................................................................. 31
RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND BLANKING PERIOD....................... 32
3
S6C0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
INTRODUCTION
The S6C0670 is a 384 / 402 channel output, TFT-LCD source driver for an 256 gray scale LCD panel. Data input
is based on digital input consisting of 8 bits by 6 dots, which can realize a full-color display of 16,700,000 color by
output of 256 values gamma-corrected.
This device has an internal D/A (Digital-to-Analog) converter for each output and 16 (8-by-2) reference voltages.
Because the output dynamic range is as large as 7.8 - 14.8 Vp-p, it is unnecessary to operate level inversion of
the LCD's common electrode. Besides, to be able to deal with dot-line inversion when mounted on a single-side,
output gray scale voltages with different polarity can be output to the odd number output pins
and the even output pins.
S6C0670 can be adopted to larger panel, and SHL (shift direction selection) pin makes the use of the LCD panel
connection conveniently. Maximum operation clock frequency is 75 MHz at 3.0 V logic operation, single edge
and it can be applied to the TFT-LCD panel of UXGA standard.
FEATURES
•
TFT active matrix LCD source driver LSI
•
256 G/S is possible through 16 (8 by 2) reference voltages and D/A converter
•
Both dot inversion display and N-line inversion display are possible
•
CMOS level input
•
Compatible with gamma-correction
•
Input data inversion function (DATPOL1,2)
•
Single edge, Double edge compatible (DEC)
•
Logic supply voltage: 2.5 - 3.6 V
•
LCD driver supply voltage: 8.0 - 15.0 V
•
Output dynamic range: 7.8 - 14.8 Vp-p
•
Maximum operating frequency: fMAX = 75 MHz
(internal data transmission rate at 3.0 V operation, single edge)
•
Output: 384 / 402 outputs
•
TCP available
4
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670
Y001
Y002
Y003
Y400
Y401
Y402
BLOCK DIAGRAM
Output Buffer
POL
VGMA1 VGMA16
D/A Converter
16
8
8
8
8
8
8
8
8
Data Latch
CLK1
8
8
8
DATPOL1
DATPOL2
Data Register
8
D10 - D17
8
D20 - D27
8
D30 - D37
8
D40 - D47
8
D50 - D57
8
24
Data Control
D00 - D07
CLK2
8
24
67bit Shift Register
DIO2
SHL
SELT
DEC
DIO1
Figure 1. S6C0670 Block Diagram
5
S6C0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
PIN ASSIGNMENTS
Y001
Y002
Y003
(Top View)
S6C0670
Y004
Y399
Y400
Y401
Y402
Figure 2. S6C0670 Pin Assignments
6
DIO1
D00
D01
D02
D03
D04
D05
D06
D07
D10
D11
D12
D13
D14
D15
D16
D17
D20
D21
D22
D23
D24
D25
D26
D27
TEST
DATPOL1
DATPOL2
POL
CLK1
CLK2
DEC
VSS1
VGMA1
VGMA2
VGMA3
VGMA4
VGMA5
VGMA6
VGMA7
VGMA8
VSS2
VDD2
VGMA9
VGMA10
VGMA11
VGMA12
VGMA13
VGMA14
VGMA15
VGMA16
SELT
SHL
VDD1
D30
D31
D32
D33
D34
D35
D36
D37
D40
D41
D42
D43
D44
D45
D46
D47
D50
D51
D52
D53
D54
D55
D56
D57
DIO2
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670
PIN DESCRIPTIONS
Symbol
VDD1
VDD2
VSS1
VSS2
Y1 - Y402
D0<0:7>
- D5<0:7>
Pin Name
Logic power supply
Driver power supply
Logic ground
Driver ground
Driver outputs
Description
2.5 - 3.6 V
8.0 - 15.0 V
Ground (0 V)
Ground (0 V)
The D/A converted 256 gray-scale analog voltage is output.
The display data is input with a width of 48 bits,
Display data input
gray-scale data (8 bits) by 6 dots (R,G,B) DX0: LSB, DX7: MSB
This pin controls the direction of shift register in cascade connection.
Shift direction control The shift direction of the shift registers is as follows.
SHL
input
SHL = H: DIO1 input, Y1 → Y402, DIO2 output
SHL = L: DIO2 input, Y402 → Y1, DIO1 output
SHL = H: Used as the start pulse input pin.
DIO1
Start pulse input/output
SHL = L: Used as the start pulse output pin.
SHL = H: Used as the start pulse output pin.
DIO2
Start pulse input/output
SHL = L: Used as the start pulse input pin.
DATPOL1,2 = L: Display data is not inverted
DATPOL1
Data inversion input
DATPOL1 = H: Display data of D0<0:7> - D2<0:7> is inverted
DATPOL2
DATPOL2 = H: Display data of D3<0:7> - D5<0:7> is inverted
POL = H: The reference voltage for odd number outputs are VGMA9 –
VGMA16 and those for even number outputs are VGMA1 – VGMA8.
POL
Polarity input
POL = L: The reference voltage for odd number outputs are VGMA1 –
VGMA8 and those for even number outputs are VGMA9 – VGMA16.
Refer to the shift register's shift clock input. When DEC is Low, the
display data is loaded to the data register at the rising edge of
CLK2
Shift clock input
CLK2.When DEC is High, the display data is loaded to the data register
at the rising and falling edge of CLK2.
Latches the contents of the data register at rising edge and transfers
them to the D/A converter. Also, after CLK1 input, clears the internal
shift register contents. After 1 pulse input on start, operates normally.
CLK1
Latch input
CLK1 input timing refers to the "Relationships between CLK1 start pulse
(DIO1, DIO2) and blanking period" of the switching characteristic
waveform. Outputs the G/S data at falling edge.
Input the gamma corrected power supplies from external source.
VGMA1
Gamma corrected power VDD2 > VGMA1 > VGMA2 > …… > VGMA15 > VGMA16 > VSS2
–
supplies
Keep gray-scale power supply unchanged during the gray-scale
VGMA16
voltage output.
SELT = L: 384 Output (Y193 - Y210 are disabled), SELT = H: 402
SELT
Output selection input
Output
DEC = L: Single Edge, the display data is loaded to the data register at
Double edge selection
DEC
the rising edge of CLK2. DEC = H: Double Edge, the display data is
input
loaded to the data register at the rising and falling edge of CLK2.
TEST = L: Normal operation mode
TEST
Test input
TEST = H: Test mode (OP AMP CUT-OFF, Rpd = 10kΩ)
7
S6C0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
OPERATION DESCRIPTION
DISPLAY DATA TRANSFER
(1) DEC = ”L”
When DIO1 (or DIO2) pulse is loaded into internal latch on the rising edge of CLK2, DIO1 (or DIO2) pulse
enables the operation of data transfer, so display data is valid on the next rising edge of CLK2. Once all the
data of 402 (or 384) channels is loaded into internal latch, it goes into stand-by state automatically, and any
new data is not accepted even though CLK2 is provided until next DIO1 (or DIO2) input. When next DIO1 (or
DIO2) is provided, new display data is valid on the 2nd rising edge of CLK2 after the rising edge of DIO1 (or
DIO2).
(2) DEC = ”H”
When DIO1 (or DIO2) pulse is loaded into internal latch on the rising (or falling) edge of CLK2, DIO1 (or DIO2)
pulse enables the operation of data transfer. display data is valid on the next falling (or rising) edge of CLK2.
Once all the data of 402 (or 384) channels is loaded into internal latch, it goes into stand-by state
automatically, and any new data is not accepted even though CLK2 is provided until next DIO1 (or DIO2)
input. When next DIO1 (or DIO2) is provided, new display data is valid on the 2nd edge of CLK2 after the
rising edge of DIO1 (or DIO2).
EXTENSION OF OUTPUT
Output pin can be adjusted to an extended screen by cascade connection.
(1) SHL = "L"
Connect DIO1 pin of previous stage to the DIO2 pin of next stage and all the input pins
except DIO1 and DIO2 are connected together in each device.
(2) SHL = "H"
Connect DIO2 pin of previous stage to the DIO1 pin of next stage and all the input pins
except DIO2 and DIO1 are connected together in each device.
RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE
The LCD drive output voltages are determined by the input data and 16 (8 by 2) gamma corrected power supplies
(VGMA1 - VGMA16). Besides, to be able to deal with dot line inversion when mounted on a single-side, gradation
voltages with different polarity can be output to the odd number output pins and the even number output pins.
Among 8-by-2 gamma corrected voltages, input gray-scale voltages of the same polarity with respect to the
common voltage, for the respective 8 gamma corrected voltages of VGMA1 - VGMA8 and VGMA9 - VGMA16.
8
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670
SHL = H
OUTPUT
Y1
Y2
-
Y3
......
Y400
First
DATA
Y401
Y402
Last
D00 - D07
D10 - D17
D20 - D27
......
D30 - D37
D40 - D47
D50 - D57
Y1
Y2
Y3
......
Y400
Y401
Y402
SHL = L
OUTPUT
DATA
Last
D00 - D07
D10 - D17
First
D20 - D27
......
D30 - D37
D40 - D47
D50 - D57
Figure 3. Relationship between Shift Direction and Output Data
VDD2
VGMA1
32
VGMA2
VGMA3
32
64
VGMA4
64
VGMA5
48
VGMA6
14
VGMA7,8
VGMA9,10
VCOM
14
VGMA11
48
VGMA12
64
VGMA13
64
VGMA14
VGMA15
32
32
VGMA16
VSS2
00H
20H
40H
60H
80H
A0H
C0H
E0H
FFH
Figure 4. Gamma Correction Curve
9
S6C0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
Table 1. Resistor Strings (R0 - R254, unit: Ω )
Name
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
10
Value
404
320
263
224
196
177
163
153
144
138
132
127
122
118
113
109
106
102
99
96
93
90
88
86
84
82
80
79
77
76
75
74
Name
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R15
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
Value
74
73
72
72
71
71
71
70
70
69
69
69
68
68
67
67
66
65
65
64
63
62
61
60
59
58
57
56
55
53
52
51
Name
R64
R65
R66
R67
R68
R69
R70
R71
R72
R73
R74
R75
R76
R77
R78
R79
R80
R81
R82
R83
R84
R85
R86
R87
R88
R89
R90
R91
R92
R93
R94
R95
Value
50
49
48
47
46
45
44
43
42
41
40
40
39
38
38
37
37
37
36
36
36
36
36
36
36
36
36
36
36
36
36
36
Name
R96
R97
R98
R99
R100
R101
R102
R103
R104
R105
R106
R107
R108
R109
R110
R111
R112
R113
R114
R115
R116
R117
R118
R119
R120
R121
R122
R123
R124
R125
R126
R127
Value
36
36
36
36
36
36
36
36
36
36
35
35
35
35
35
35
35
35
35
34
34
34
34
34
34
34
34
34
34
33
33
33
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670
Table 1. Resistor Strings (R0 - R254, unit: Ω ) (Continued)
Name
R128
R129
R130
R131
R132
R133
R134
R135
R136
R137
R138
R139
R140
R141
R142
R143
R144
R145
R146
R147
R148
R149
R150
R151
R152
R153
R154
R155
R156
R157
R158
R159
Value
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
Name
R160
R161
R162
R163
R164
R165
R166
R167
R168
R169
R170
R171
R172
R173
R174
R175
R176
R177
R178
R179
R180
R181
R182
R183
R184
R185
R186
R187
R188
R189
R190
R191
Value
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
34
34
34
34
35
35
35
36
36
36
37
37
38
38
Name
R192
R193
R194
R195
R196
R197
R198
R199
R200
R201
R202
R203
R204
R205
R206
R207
R208
R209
R210
R211
R212
R213
R214
R215
R216
R217
R218
R219
R220
R221
R222
R223
Value
38
39
39
39
40
40
40
41
41
41
42
42
42
42
43
43
43
43
44
44
45
45
46
47
48
49
51
52
54
56
59
62
Name
R224
R225
R226
R227
R228
R229
R230
R231
R232
R233
R234
R235
R236
R237
R238
R239
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
Value
65
69
73
77
82
87
92
97
103
109
115
122
128
134
141
147
154
161
168
177
187
199
215
238
270
318
396
533
811
817
831
11
S6C0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
Table 2. Relationship between Input Data and Output Voltage Value (1)
Input
data
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
G/S
Output voltage
VH0
VH1
VH2
VH3
VH4
VH5
VH6
VH7
VH8
VH9
VH10
VH11
VH12
VH13
VH14
VH15
VGMA1
VGMA1 + (VGMA2 - VGMA1) × 404 / 4288
VGMA1 + (VGMA2 - VGMA1) × 724 / 4288
VGMA1 + (VGMA2 - VGMA1) × 987 / 4288
VGMA1 + (VGMA2 - VGMA1) × 1211 / 4288
VGMA1 + (VGMA2 - VGMA1) × 1408 / 4288
VGMA1 + (VGMA2 - VGMA1) × 1585 / 4288
VGMA1 + (VGMA2 - VGMA1) × 1748 / 4288
VGMA1 + (VGMA2 - VGMA1) × 1900 / 4288
VGMA1 + (VGMA2 - VGMA1) × 2044 / 4288
VGMA1 + (VGMA2 - VGMA1) × 2182 / 4288
VGMA1 + (VGMA2 - VGMA1) × 2314 / 4288
VGMA1 + (VGMA2 - VGMA1) × 2441 / 4288
VGMA1 + (VGMA2 - VGMA1) × 2562 / 4288
VGMA1 + (VGMA2 - VGMA1) × 2680 / 4288
VGMA1 + (VGMA2 - VGMA1) × 2793 / 4288
VH16
VH17
VH18
VH19
VH20
VH21
VH22
VH23
VGMA1 + (VGMA2 - VGMA1) × 2903 / 4288
VGMA1 + (VGMA2 - VGMA1) × 3008 / 4288
VGMA1 + (VGMA2 - VGMA1) × 3110 / 4288
VGMA1 + (VGMA2 - VGMA1) × 3209 / 4288
VGMA1 + (VGMA2 - VGMA1) × 3305 / 4288
VGMA1 + (VGMA2 - VGMA1) × 3398 / 4288
VGMA1 + (VGMA2 - VGMA1) × 3488 / 4288
VGMA1 + (VGMA2 - VGMA1) × 3576 / 4288
VH24
VH25
VH26
VH27
VH28
VH29
VH30
VH31
VGMA1 + (VGMA2 - VGMA1) × 3661 / 4288
VGMA1 + (VGMA2 - VGMA1) × 3745 / 4288
VGMA1 + (VGMA2 - VGMA1) × 3826 / 4288
VGMA1 + (VGMA2 - VGMA1) × 3906 / 4288
VGMA1 + (VGMA2 - VGMA1) × 3985 / 4288
VGMA1 + (VGMA2 - VGMA1) × 4062 / 4288
VGMA1 + (VGMA2 - VGMA1) × 4138 / 4288
VGMA1 + (VGMA2 - VGMA1) × 4214 / 4288
VGMA2
VGMA2 + (VGMA3 - VGMA2) × 74 / 2065
VGMA2 + (VGMA3 - VGMA2) × 147 / 2065
VGMA2 + (VGMA3 - VGMA2) × 219 / 2065
VGMA2 + (VGMA3 - VGMA2) × 291 / 2065
VGMA2 + (VGMA3 - VGMA2) × 362 / 2065
VGMA2 + (VGMA3 - VGMA2) × 433 / 2065
VGMA2 + (VGMA3 - VGMA2) × 504 / 2065
VH32
VH33
VH34
VH35
VH36
VH37
VH38
VH39
NOTE: VDD2>VGMA1>VGMA2>VGMA3>VGMA4>VGMA5>VGMA6>VGMA7>VGMA8
12
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670
Table 2. Relationship between Input Data and Output Voltage Value (2)
Input
data
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
G/S
Output voltage
VH40
VH41
VH42
VH43
VH44
VH45
VH46
VH47
VGMA2 + (VGMA3 - VGMA2) × 574 / 2065
VGMA2 + (VGMA3 - VGMA2) × 644 / 2065
VGMA2 + (VGMA3 - VGMA2) × 713 / 2065
VGMA2 + (VGMA3 - VGMA2) × 782 / 2065
VGMA2 + (VGMA3 - VGMA2) × 851 / 2065
VGMA2 + (VGMA3 - VGMA2) × 919 / 2065
VGMA2 + (VGMA3 - VGMA2) × 987 / 2065
VGMA2 + (VGMA3 - VGMA2) × 1054 / 2065
VH48
VH49
VH50
VH51
VH52
VH53
VH54
VH55
VGMA2 + (VGMA3 - VGMA2) × 1120 / 2065
VGMA2 + (VGMA3 - VGMA2) × 1186 / 2065
VGMA2 + (VGMA3 - VGMA2) × 1251 / 2065
VGMA2 + (VGMA3 - VGMA2) × 1316 / 2065
VGMA2 + (VGMA3 - VGMA2) × 1380 / 2065
VGMA2 + (VGMA3 - VGMA2) × 1442 / 2065
VGMA2 + (VGMA3 - VGMA2) × 1504 / 2065
VGMA2 + (VGMA3 - VGMA2) × 1565 / 2065
VH56
VH57
VH58
VH59
VH60
VH61
VH62
VH63
VGMA2 + (VGMA3 - VGMA2) × 1625 / 2065
VGMA2 + (VGMA3 - VGMA2) × 1684 / 2065
VGMA2 + (VGMA3 - VGMA2) × 1742 / 2065
VGMA2 + (VGMA3 - VGMA2) × 1799 / 2065
VGMA2 + (VGMA3 - VGMA2) × 1854 / 2065
VGMA2 + (VGMA3 - VGMA2) × 1909 / 2065
VGMA2 + (VGMA3 - VGMA2) × 1962 / 2065
VGMA2 + (VGMA3 - VGMA2) × 2014 / 2065
VH64
VH65
VH66
VH67
VH68
VH69
VH70
VH71
VGMA3
VGMA3 + (VGMA4 - VGMA3) × 50 / 2368
VGMA3 + (VGMA4 - VGMA3) × 99 / 2368
VGMA3 + (VGMA4 - VGMA3) × 146 / 2368
VGMA3 + (VGMA4 - VGMA3) × 193 / 2368
VGMA3 + (VGMA4 - VGMA3) × 238 / 2368
VGMA3 + (VGMA4 - VGMA3) × 283 / 2368
VGMA3 + (VGMA4 - VGMA3) × 326 / 2368
VH72
VH73
VH74
VH75
VH76
VH77
VH78
VH79
VGMA3 + (VGMA4 - VGMA3) × 369 / 2368
VGMA3 + (VGMA4 - VGMA3) × 411 / 2368
VGMA3 + (VGMA4 - VGMA3) × 452 / 2368
VGMA3 + (VGMA4 - VGMA3) × 492 / 2368
VGMA3 + (VGMA4 - VGMA3) × 532 / 2368
VGMA3 + (VGMA4 - VGMA3) × 571 / 2368
VGMA3 + (VGMA4 - VGMA3) × 609 / 2368
VGMA3 + (VGMA4 - VGMA3) × 647 / 2368
13
S6C0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
Table 2. Relationship between Input Data and Output Voltage Value (3)
Input
data
50H
51H
52H
53H
54H
55H
56H
57H
58H
59H
5AH
5BH
5CH
5DH
5EH
5FH
60H
61H
62H
63H
64H
65H
66H
67H
68H
69H
6AH
6BH
6CH
6DH
6EH
6FH
70H
71H
72H
73H
74H
75H
76H
77H
14
DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
G/S
Output voltage
VH80
VH81
VH82
VH83
VH84
VH85
VH86
VH87
VGMA3 + (VGMA4 - VGMA3) × 684 / 2368
VGMA3 + (VGMA4 - VGMA3) × 722 / 2368
VGMA3 + (VGMA4 - VGMA3) × 758 / 2368
VGMA3 + (VGMA4 - VGMA3) × 795 / 2368
VGMA3 + (VGMA4 - VGMA3) × 831 / 2368
VGMA3 + (VGMA4 - VGMA3) × 867 / 2368
VGMA3 + (VGMA4 - VGMA3) × 903 / 2368
VGMA3 + (VGMA4 - VGMA3) × 938 / 2368
VH88
VH89
VH90
VH91
VH92
VH93
VH94
VH95
VGMA3 + (VGMA4 - VGMA3) × 974 / 2368
VGMA3 + (VGMA4 - VGMA3) × 1009 / 2368
VGMA3 + (VGMA4 - VGMA3) × 1045 / 2368
VGMA3 + (VGMA4 - VGMA3) × 1080 / 2368
VGMA3 + (VGMA4 - VGMA3) × 1116 / 2368
VGMA3 + (VGMA4 - VGMA3) × 1151 / 2368
VGMA3 + (VGMA4 - VGMA3) × 1187 / 2368
VGMA3 + (VGMA4 - VGMA3) × 1222 / 2368
VH96
VH97
VH98
VH99
VH100
VH101
VH102
VH103
VGMA3 + (VGMA4 - VGMA3) × 1258 / 2368
VGMA3 + (VGMA4 - VGMA3) × 1294 / 2368
VGMA3 + (VGMA4 - VGMA3) × 1329 / 2368
VGMA3 + (VGMA4 - VGMA3) × 1365 / 2368
VGMA3 + (VGMA4 - VGMA3) × 1401 / 2368
VGMA3 + (VGMA4 - VGMA3) × 1436 / 2368
VGMA3 + (VGMA4 - VGMA3) × 1472 / 2368
VGMA3 + (VGMA4 - VGMA3) × 1507 / 2368
VH104
VH105
VH106
VH107
VH108
VH109
VH110
VH111
VGMA3 + (VGMA4 - VGMA3) × 1543 / 2368
VGMA3 + (VGMA4 - VGMA3) × 1579 / 2368
VGMA3 + (VGMA4 - VGMA3) × 1614 / 2368
VGMA3 + (VGMA4 - VGMA3) × 1649 / 2368
VGMA3 + (VGMA4 - VGMA3) × 1685 / 2368
VGMA3 + (VGMA4 - VGMA3) × 1720 / 2368
VGMA3 + (VGMA4 - VGMA3) × 1755 / 2368
VGMA3 + (VGMA4 - VGMA3) × 1790 / 2368
VH112
VH113
VH114
VH115
VH116
VH117
VH118
VH119
VGMA3 + (VGMA4 - VGMA3) × 1825 / 2368
VGMA3 + (VGMA4 - VGMA3) × 1860 / 2368
VGMA3 + (VGMA4 - VGMA3) × 1895 / 2368
VGMA3 + (VGMA4 - VGMA3) × 1929 / 2368
VGMA3 + (VGMA4 - VGMA3) × 1964 / 2368
VGMA3 + (VGMA4 - VGMA3) × 1998 / 2368
VGMA3 + (VGMA4 - VGMA3) × 2032 / 2368
VGMA3 + (VGMA4 - VGMA3) × 2066 / 2368
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670
Table 2. Relationship between Input Data and Output Voltage Value (4)
Input
data
78H
79H
7AH
7BH
7CH
7DH
7EH
7FH
80H
81H
82H
83H
84H
85H
86H
87H
88H
89H
8AH
8BH
8CH
8DH
8EH
8FH
90H
91H
92H
93H
94H
95H
96H
97H
98H
99H
9AH
9BH
9CH
9DH
9EH
9FH
DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
G/S
Output voltage
VH120
VH121
VH122
VH123
VH124
VH125
VH126
VH127
VGMA3 + (VGMA4 - VGMA3) × 2100 / 2368
VGMA3 + (VGMA4 - VGMA3) × 2134 / 2368
VGMA3 + (VGMA4 - VGMA3) × 2168 / 2368
VGMA3 + (VGMA4 - VGMA3) × 2201 / 2368
VGMA3 + (VGMA4 - VGMA3) × 2235 / 2368
VGMA3 + (VGMA4 - VGMA3) × 2268 / 2368
VGMA3 + (VGMA4 - VGMA3) × 2302 / 2368
VGMA3 + (VGMA4 - VGMA3) × 2335 / 2368
VH128
VH129
VH130
VH131
VH132
VH133
VH134
VH135
VGMA4
VGMA4 + (VGMA5 - VGMA4) × 33 / 2149
VGMA4 + (VGMA5 - VGMA4) × 66 / 2149
VGMA4 + (VGMA5 - VGMA4) × 100 / 2149
VGMA4 + (VGMA5 - VGMA4) × 133 / 2149
VGMA4 + (VGMA5 - VGMA4) × 166 / 2149
VGMA4 + (VGMA5 - VGMA4) × 199 / 2149
VGMA4 + (VGMA5 - VGMA4) × 232 / 2149
VH136
VH137
VH138
VH139
VH140
VH141
VH142
VH143
VGMA4 + (VGMA5 - VGMA4) × 266 / 2149
VGMA4 + (VGMA5 - VGMA4) × 299 / 2149
VGMA4 + (VGMA5 - VGMA4) × 332 / 2149
VGMA4 + (VGMA5 - VGMA4) × 365 / 2149
VGMA4 + (VGMA5 - VGMA4) × 399 / 2149
VGMA4 + (VGMA5 - VGMA4) × 432 / 2149
VGMA4 + (VGMA5 - VGMA4) × 465 / 2149
VGMA4 + (VGMA5 - VGMA4) × 498 / 2149
VH144
VH145
VH146
VH147
VH148
VH149
VH150
VH151
VGMA4 + (VGMA5 - VGMA4) × 532 / 2149
VGMA4 + (VGMA5 - VGMA4) × 565 / 2149
VGMA4 + (VGMA5 - VGMA4) × 598 / 2149
VGMA4 + (VGMA5 - VGMA4) × 632 / 2149
VGMA4 + (VGMA5 - VGMA4) × 665 / 2149
VGMA4 + (VGMA5 - VGMA4) × 698 / 2149
VGMA4 + (VGMA5 - VGMA4) × 732 / 2149
VGMA4 + (VGMA5 - VGMA4) × 765 / 2149
VH152
VH153
VH154
VH155
VH156
VH157
VH158
VH159
VGMA4 + (VGMA5 - VGMA4) × 798 / 2149
VGMA4 + (VGMA5 - VGMA4) × 831 / 2149
VGMA4 + (VGMA5 - VGMA4) × 864 / 2149
VGMA4 + (VGMA5 - VGMA4) × 897 / 2149
VGMA4 + (VGMA5 - VGMA4) × 930 / 2149
VGMA4 + (VGMA5 - VGMA4) × 963 / 2149
VGMA4 + (VGMA5 - VGMA4) × 996 / 2149
VGMA4 + (VGMA5 - VGMA4) × 1029 / 2149
15
S6C0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
Table 2. Relationship between Input Data and Output Voltage Value (5)
Input
data
A0H
A1H
A2H
A3H
A4H
A5H
A6H
A7H
A8H
A9H
AAH
ABH
ACH
ADH
AEH
AFH
B0H
B1H
B2H
B3H
B4H
B5H
B6H
B7H
B8H
B9H
BAH
BBH
BCH
BDH
BEH
BFH
C0H
C1H
C2H
C3H
C4H
C5H
C6H
C7H
16
DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
G/S
Output voltage
VH160
VH161
VH162
VH163
VH164
VH165
VH166
VH167
VGMA4 + (VGMA5 - VGMA4) × 1062 / 2149
VGMA4 + (VGMA5 - VGMA4) × 1094 / 2149
VGMA4 + (VGMA5 - VGMA4) × 1127 / 2149
VGMA4 + (VGMA5 - VGMA4) × 1159 / 2149
VGMA4 + (VGMA5 - VGMA4) × 1192 / 2149
VGMA4 + (VGMA5 - VGMA4) × 1224 / 2149
VGMA4 + (VGMA5 - VGMA4) × 1257 / 2149
VGMA4 + (VGMA5 - VGMA4) × 1289 / 2149
VH168
VH169
VH170
VH171
VH172
VH173
VH174
VH175
VGMA4 + (VGMA5 - VGMA4) × 1322 / 2149
VGMA4 + (VGMA5 - VGMA4) × 1354 / 2149
VGMA4 + (VGMA5 - VGMA4) × 1387 / 2149
VGMA4 + (VGMA5 - VGMA4) × 1419 / 2149
VGMA4 + (VGMA5 - VGMA4) × 1452 / 2149
VGMA4 + (VGMA5 - VGMA4) × 1485 / 2149
VGMA4 + (VGMA5 - VGMA4) × 1517 / 2149
VGMA4 + (VGMA5 - VGMA4) × 1550 / 2149
VH176
VH177
VH178
VH179
VH180
VH181
VH182
VH183
VGMA4 + (VGMA5 - VGMA4) × 1583 / 2149
VGMA4 + (VGMA5 - VGMA4) × 1617 / 2149
VGMA4 + (VGMA5 - VGMA4) × 1650 / 2149
VGMA4 + (VGMA5 - VGMA4) × 1684 / 2149
VGMA4 + (VGMA5 - VGMA4) × 1717 / 2149
VGMA4 + (VGMA5 - VGMA4) × 1752 / 2149
VGMA4 + (VGMA5 - VGMA4) × 1786 / 2149
VGMA4 + (VGMA5 - VGMA4) × 1821 / 2149
VH184
VH185
VH186
VH187
VH188
VH189
VH190
VH191
VGMA4 + (VGMA5 - VGMA4) × 1856 / 2149
VGMA4 + (VGMA5 - VGMA4) × 1891 / 2149
VGMA4 + (VGMA5 - VGMA4) × 1927 / 2149
VGMA4 + (VGMA5 - VGMA4) × 1963 / 2149
VGMA4 + (VGMA5 - VGMA4) × 1999 / 2149
VGMA4 + (VGMA5 - VGMA4) × 2036 / 2149
VGMA4 + (VGMA5 - VGMA4) × 2073 / 2149
VGMA4 + (VGMA5 - VGMA4) × 2111 / 2149
VH192
VH193
VH194
VH195
VH196
VH197
VH198
VH199
VGMA5
VGMA5 + (VGMA6 - VGMA5) × 38 / 3080
VGMA5 + (VGMA6 - VGMA5) × 77 / 3080
VGMA5 + (VGMA6 - VGMA5) × 116 / 3080
VGMA5 + (VGMA6 - VGMA5) × 155 / 3080
VGMA5 + (VGMA6 - VGMA5) × 195 / 3080
VGMA5 + (VGMA6 - VGMA5) × 235 / 3080
VGMA5 + (VGMA6 - VGMA5) × 276 / 3080
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670
Table 2. Relationship between Input Data and Output Voltage Value (6)
Input
data
C8H
C9H
CAH
CBH
CCH
CDH
CEH
CFH
D0H
D1H
D2H
D3H
D4H
D5H
D6H
D7H
D8H
D9H
DAH
DBH
DCH
DDH
DEH
DFH
E0H
E1H
E2H
E3H
E4H
E5H
E6H
E7H
E8H
E9H
EAH
EBH
ECH
EDH
EEH
EFH
DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
G/S
Output voltage
VH200
VH201
VH202
VH203
VH204
VH205
VH206
VH207
VGMA5 + (VGMA6 - VGMA5) × 316 / 3080
VGMA5 + (VGMA6 - VGMA5) × 357 / 3080
VGMA5 + (VGMA6 - VGMA5) × 399 / 3080
VGMA5 + (VGMA6 - VGMA5) × 440 / 3080
VGMA5 + (VGMA6 - VGMA5) × 482 / 3080
VGMA5 + (VGMA6 - VGMA5) × 524 / 3080
VGMA5 + (VGMA6 - VGMA5) × 566 / 3080
VGMA5 + (VGMA6 - VGMA5) × 609 / 3080
VH208
VH209
VH210
VH211
VH212
VH213
VH214
VH215
VGMA5 + (VGMA6 - VGMA5) × 651 / 3080
VGMA5 + (VGMA6 - VGMA5) × 694 / 3080
VGMA5 + (VGMA6 - VGMA5) × 738 / 3080
VGMA5 + (VGMA6 - VGMA5) × 782 / 3080
VGMA5 + (VGMA6 - VGMA5) × 826 / 3080
VGMA5 + (VGMA6 - VGMA5) × 871 / 3080
VGMA5 + (VGMA6 - VGMA5) × 916 / 3080
VGMA5 + (VGMA6 - VGMA5) × 962 / 3080
VH216
VH217
VH218
VH219
VH220
VH221
VH222
VH223
VGMA5 + (VGMA6 - VGMA5) × 1009 / 3080
VGMA5 + (VGMA6 - VGMA5) × 1057 / 3080
VGMA5 + (VGMA6 - VGMA5) × 1106 / 3080
VGMA5 + (VGMA6 - VGMA5) × 1157 / 3080
VGMA5 + (VGMA6 - VGMA5) × 1209 / 3080
VGMA5 + (VGMA6 - VGMA5) × 1263 / 3080
VGMA5 + (VGMA6 - VGMA5) × 1320 / 3080
VGMA5 + (VGMA6 - VGMA5) × 1379 / 3080
VH224
VH225
VH226
VH227
VH228
VH229
VH230
VH231
VGMA5 + (VGMA6 - VGMA5) × 1441 / 3080
VGMA5 + (VGMA6 - VGMA5) × 1506 / 3080
VGMA5 + (VGMA6 - VGMA5) × 1574 / 3080
VGMA5 + (VGMA6 - VGMA5) × 1647 / 3080
VGMA5 + (VGMA6 - VGMA5) × 1724 / 3080
VGMA5 + (VGMA6 - VGMA5) × 1805 / 3080
VGMA5 + (VGMA6 - VGMA5) × 1892 / 3080
VGMA5 + (VGMA6 - VGMA5) × 1983 / 3080
VH232
VH233
VH234
VH235
VH236
VH237
VH238
VH239
VGMA5 + (VGMA6 - VGMA5) × 2081 / 3080
VGMA5 + (VGMA6 - VGMA5) × 2184 / 3080
VGMA5 + (VGMA6 - VGMA5) × 2293 / 3080
VGMA5 + (VGMA6 - VGMA5) × 2409 / 3080
VGMA5 + (VGMA6 - VGMA5) × 2530 / 3080
VGMA5 + (VGMA6 - VGMA5) × 2658 / 3080
VGMA5 + (VGMA6 - VGMA5) × 2792 / 3080
VGMA5 + (VGMA6 - VGMA5) × 2933 / 3080
17
S6C0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
Table 2. Relationship between Input Data and Output Voltage Value (7)
Input
data
F0H
F1H
F2H
F3H
F4H
F5H
F6H
F7H
F8H
F9H
FAH
FBH
FCH
FDH
FEH
FFH
18
DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
G/S
Output voltage
VH240
VH241
VH242
VH243
VH244
VH245
VH246
VH247
VGMA6
VGMA6 + (VGMA7 - VGMA6) × 154 / 4641
VGMA6 + (VGMA7 - VGMA6) × 314 / 4641
VGMA6 + (VGMA7 - VGMA6) × 482 / 4641
VGMA6 + (VGMA7 - VGMA6) × 659 / 4641
VGMA6 + (VGMA7 - VGMA6) × 846 / 4641
VGMA6 + (VGMA7 - VGMA6) × 1045 / 4641
VGMA6 + (VGMA7 - VGMA6) × 1260 / 4641
VH248
VH249
VH250
VH251
VH252
VH253
VH254
VH255
VGMA6 + (VGMA7 - VGMA6) × 1498 / 4641
VGMA6 + (VGMA7 - VGMA6) × 1768 / 4641
VGMA6 + (VGMA7 - VGMA6) × 2086 / 4641
VGMA6 + (VGMA7 - VGMA6) × 2482 / 4641
VGMA6 + (VGMA7 - VGMA6) × 3014 / 4641
VGMA6 + (VGMA7 - VGMA6) × 3825 / 4641
VGMA7
VGMA8
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670
Table 2. Relationship between Input Data and Output Voltage Value (8)
Input
data
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
G/S
Output voltage
VL0
VL1
VL2
VL3
VL4
VL5
VL6
VL7
VL8
VL9
VL10
VL11
VL12
VL13
VL14
VL15
VGMA16
VGMA16 + (VGMA15 - VGMA16) × 404 / 4288
VGMA16 + (VGMA15 - VGMA16) × 724 / 4288
VGMA16 + (VGMA15 - VGMA16) × 987 / 4288
VGMA16 + (VGMA15 - VGMA16) × 1211 / 4288
VGMA16 + (VGMA15 - VGMA16) × 1408 / 4288
VGMA16 + (VGMA15 - VGMA16) × 1585 / 4288
VGMA16 + (VGMA15 - VGMA16) × 1748 / 4288
VGMA16 + (VGMA15 - VGMA16) × 1900 / 4288
VGMA16 + (VGMA15 - VGMA16) × 2044 / 4288
VGMA16 + (VGMA15 - VGMA16) × 2182 / 4288
VGMA16 + (VGMA15 - VGMA16) × 2314 / 4288
VGMA16 + (VGMA15 - VGMA16) × 2441 / 4288
VGMA16 + (VGMA15 - VGMA16) × 2562 / 4288
VGMA16 + (VGMA15 - VGMA16) × 2680 / 4288
VGMA16 + (VGMA15 - VGMA16) × 2793 / 4288
VL16
VL17
VL18
VL19
VL20
VL21
VL22
VL23
VGMA16 + (VGMA15 - VGMA16) × 2903 / 4288
VGMA16 + (VGMA15 - VGMA16) × 3008 / 4288
VGMA16 + (VGMA15 - VGMA16) × 3110 / 4288
VGMA16 + (VGMA15 - VGMA16) × 3209 / 4288
VGMA16 + (VGMA15 - VGMA16) × 3305 / 4288
VGMA16 + (VGMA15 - VGMA16) × 3398 / 4288
VGMA16 + (VGMA15 - VGMA16) × 3488 / 4288
VGMA16 + (VGMA15 - VGMA16) × 3576 / 4288
VL24
VL25
VL26
VL27
VL28
VL29
VL30
VL31
VGMA16 + (VGMA15 - VGMA16) × 3661 / 4288
VGMA16 + (VGMA15 - VGMA16) × 3745 / 4288
VGMA16 + (VGMA15 - VGMA16) × 3826 / 4288
VGMA16 + (VGMA15 - VGMA16) × 3906 / 4288
VGMA16 + (VGMA15 - VGMA16) × 3985 / 4288
VGMA16 + (VGMA15 - VGMA16) × 4062 / 4288
VGMA16 + (VGMA15 - VGMA16) × 4138 / 4288
VGMA16 + (VGMA15 - VGMA16) × 4214 / 4288
VGMA15
VGMA15 + (VGMA14 - VGMA15) × 74 / 2065
VGMA15 + (VGMA14 - VGMA15) × 147 / 2065
VGMA15 + (VGMA14 - VGMA15) × 219 / 2065
VGMA15 + (VGMA14 - VGMA15) × 291 / 2065
VGMA15 + (VGMA14 - VGMA15) × 362 / 2065
VGMA15 + (VGMA14 - VGMA15) × 433 / 2065
VGMA15 + (VGMA14 - VGMA15) × 504 / 2065
VL32
VL33
VL34
VL35
VL36
VL37
VL38
VL39
NOTE: VSS2<VGMA16<VGMA15<VGMA14<VGMA13<VGMA12<VGMA11<VGMA10<VGMA9
19
S6C0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
Table 2. Relationship between Input Data and Output Voltage Value (9)
Input
data
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
20
DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
G/S
Output voltage
VL40
VL41
VL42
VL43
VL44
VL45
VL46
VL47
VGMA15 + (VGMA14 - VGMA15) × 574 / 2065
VGMA15 + (VGMA14 - VGMA15) × 644 / 2065
VGMA15 + (VGMA14 - VGMA15) × 713 / 2065
VGMA15 + (VGMA14 - VGMA15) × 782 / 2065
VGMA15 + (VGMA14 - VGMA15) × 851 / 2065
VGMA15 + (VGMA14 - VGMA15) × 919 / 2065
VGMA15 + (VGMA14 - VGMA15) × 987 / 2065
VGMA15 + (VGMA14 - VGMA15) × 1054 / 2065
VL48
VL49
VL50
VL51
VL52
VL53
VL54
VL55
VGMA15 + (VGMA14 - VGMA15) × 1120 / 2065
VGMA15 + (VGMA14 - VGMA15) × 1186 / 2065
VGMA15 + (VGMA14 - VGMA15) × 1251 / 2065
VGMA15 + (VGMA14 - VGMA15) × 1316 / 2065
VGMA15 + (VGMA14 - VGMA15) × 1380 / 2065
VGMA15 + (VGMA14 - VGMA15) × 1442 / 2065
VGMA15 + (VGMA14 - VGMA15) × 1504 / 2065
VGMA15 + (VGMA14 - VGMA15) × 1565 / 2065
VL56
VL57
VL58
VL59
VL60
VL61
VL62
VL63
VGMA15 + (VGMA14 - VGMA15) × 1625 / 2065
VGMA15 + (VGMA14 - VGMA15) × 1684 / 2065
VGMA15 + (VGMA14 - VGMA15) × 1742 / 2065
VGMA15 + (VGMA14 - VGMA15) × 1799 / 2065
VGMA15 + (VGMA14 - VGMA15) × 1854 / 2065
VGMA15 + (VGMA14 - VGMA15) × 1909 / 2065
VGMA15 + (VGMA14 - VGMA15) × 1962 / 2065
VGMA15 + (VGMA14 - VGMA15) × 2014 / 2065
VL64
VL65
VL66
VL67
VL68
VL69
VL70
VL71
VGMA14
VGMA14 + (VGMA13 - VGMA14) × 50 / 2368
VGMA14 + (VGMA13 - VGMA14) × 99 / 2368
VGMA14 + (VGMA13 - VGMA14) × 146 / 2368
VGMA14 + (VGMA13 - VGMA14) × 193 / 2368
VGMA14 + (VGMA13 - VGMA14) × 238 / 2368
VGMA14 + (VGMA13 - VGMA14) × 283 / 2368
VGMA14 + (VGMA13 - VGMA14) × 326 / 2368
VL72
VL73
VL74
VL75
VL76
VL77
VL78
VL79
VGMA14 + (VGMA13 - VGMA14) × 369 / 2368
VGMA14 + (VGMA13 - VGMA14) × 411 / 2368
VGMA14 + (VGMA13 - VGMA14) × 452 / 2368
VGMA14 + (VGMA13 - VGMA14) × 492 / 2368
VGMA14 + (VGMA13 - VGMA14) × 532 / 2368
VGMA14 + (VGMA13 - VGMA14) × 571 / 2368
VGMA14 + (VGMA13 - VGMA14) × 609 / 2368
VGMA14 + (VGMA13 - VGMA14) × 647 / 2368
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670
Table 2. Relationship between Input Data and Output Voltage Value (10)
Input
data
50H
51H
52H
53H
54H
55H
56H
57H
58H
59H
5AH
5BH
5CH
5DH
5EH
5FH
60H
61H
62H
63H
64H
65H
66H
67H
68H
69H
6AH
6BH
6CH
6DH
6EH
6FH
70H
71H
72H
73H
74H
75H
76H
77H
DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0
G/S
Output voltage
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VL80
VL81
VL82
VL83
VL84
VL85
VL86
VL87
VGMA14 + (VGMA13 - VGMA14) × 684 / 2368
VGMA14 + (VGMA13 - VGMA14) × 722 / 2368
VGMA14 + (VGMA13 - VGMA14) × 758 / 2368
VGMA14 + (VGMA13 - VGMA14) × 795 / 2368
VGMA14 + (VGMA13 - VGMA14) × 831 / 2368
VGMA14 + (VGMA13 - VGMA14) × 867 / 2368
VGMA14 + (VGMA13 - VGMA14) × 903 / 2368
VGMA14 + (VGMA13 - VGMA14) × 938 / 2368
VL88
VL89
VL90
VL91
VL92
VL93
VL94
VL95
VGMA14 + (VGMA13 - VGMA14) × 974 / 2368
VGMA14 + (VGMA13 - VGMA14) × 1009 / 2368
VGMA14 + (VGMA13 - VGMA14) × 1045 / 2368
VGMA14 + (VGMA13 - VGMA14) × 1080 / 2368
VGMA14 + (VGMA13 - VGMA14) × 1116 / 2368
VGMA14 + (VGMA13 - VGMA14) × 1151 / 2368
VGMA14 + (VGMA13 - VGMA14) × 1187 / 2368
VGMA14 + (VGMA13 - VGMA14) × 1222 / 2368
VL96
VL97
VL98
VL99
VL100
VL101
VL102
VL103
VGMA14 + (VGMA13 - VGMA14) × 1258 / 2368
VGMA14 + (VGMA13 - VGMA14) × 1294 / 2368
VGMA14 + (VGMA13 - VGMA14) × 1329 / 2368
VGMA14 + (VGMA13 - VGMA14) × 1365 / 2368
VGMA14 + (VGMA13 - VGMA14) × 1401 / 2368
VGMA14 + (VGMA13 - VGMA14) × 1436 / 2368
VGMA14 + (VGMA13 - VGMA14) × 1472 / 2368
VGMA14 + (VGMA13 - VGMA14) × 1507 / 2368
VL104
VL105
VL106
VL107
VL108
VL109
VL110
VL111
VGMA14 + (VGMA13 - VGMA14) × 1543 / 2368
VGMA14 + (VGMA13 - VGMA14) × 1579 / 2368
VGMA14 + (VGMA13 - VGMA14) × 1614 / 2368
VGMA14 + (VGMA13 - VGMA14) × 1649 / 2368
VGMA14 + (VGMA13 - VGMA14) × 1685 / 2368
VGMA14 + (VGMA13 - VGMA14) × 1720 / 2368
VGMA14 + (VGMA13 - VGMA14) × 1755 / 2368
VGMA14 + (VGMA13 - VGMA14) × 1790 / 2368
VL112
VL113
VL114
VL115
VL116
VL117
VL118
VL119
VGMA14 + (VGMA13 - VGMA14) × 1825 / 2368
VGMA14 + (VGMA13 - VGMA14) × 1860 / 2368
VGMA14 + (VGMA13 - VGMA14) × 1895 / 2368
VGMA14 + (VGMA13 - VGMA14) × 1929 / 2368
VGMA14 + (VGMA13 - VGMA14) × 1964 / 2368
VGMA14 + (VGMA13 - VGMA14) × 1998 / 2368
VGMA14 + (VGMA13 - VGMA14) × 2032 / 2368
VGMA14 + (VGMA13 - VGMA14) × 2066 / 2368
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
21
S6C0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
Table 2. Relationship between Input Data and Output Voltage Value (11)
Input
data
78H
79H
7AH
7BH
7CH
7DH
7EH
7FH
80H
81H
82H
83H
84H
85H
86H
87H
88H
89H
8AH
8BH
8CH
8DH
8EH
8FH
90H
91H
92H
93H
94H
95H
96H
97H
98H
99H
9AH
9BH
9CH
9DH
9EH
9FH
22
DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
G/S
Output voltage
VL120
VL121
VL122
VL123
VL124
VL125
VL126
VL127
VGMA14 + (VGMA13 - VGMA14) × 2100 / 2368
VGMA14 + (VGMA13 - VGMA14) × 2134 / 2368
VGMA14 + (VGMA13 - VGMA14) × 2168 / 2368
VGMA14 + (VGMA13 - VGMA14) × 2201 / 2368
VGMA14 + (VGMA13 - VGMA14) × 2235 / 2368
VGMA14 + (VGMA13 - VGMA14) × 2268 / 2368
VGMA14 + (VGMA13 - VGMA14) × 2302 / 2368
VGMA14 + (VGMA13 - VGMA14) × 2335 / 2368
VL128
VL129
VL130
VL131
VL132
VL133
VL134
VL135
VGMA13
VGMA13 + (VGMA12 - VGMA13) × 33 / 2149
VGMA13 + (VGMA12 - VGMA13) × 66 / 2149
VGMA13 + (VGMA12 - VGMA13) × 100 / 2149
VGMA13 + (VGMA12 - VGMA13) × 133 / 2149
VGMA13 + (VGMA12 - VGMA13) × 166 / 2149
VGMA13 + (VGMA12 - VGMA13) × 199 / 2149
VGMA13 + (VGMA12 - VGMA13) × 232 / 2149
VL136
VL137
VL138
VL139
VL140
VL141
VL142
VL143
VGMA13 + (VGMA12 - VGMA13) × 266 / 2149
VGMA13 + (VGMA12 - VGMA13) × 299 / 2149
VGMA13 + (VGMA12 - VGMA13) × 332 / 2149
VGMA13 + (VGMA12 - VGMA13) × 365 / 2149
VGMA13 + (VGMA12 - VGMA13) × 399 / 2149
VGMA13 + (VGMA12 - VGMA13) × 432 / 2149
VGMA13 + (VGMA12 - VGMA13) × 465 / 2149
VGMA13 + (VGMA12 - VGMA13) × 498 / 2149
VL144
VL145
VL146
VL147
VL148
VL149
VL150
VL151
VGMA13 + (VGMA12 - VGMA13) × 532 / 2149
VGMA13 + (VGMA12 - VGMA13) × 565 / 2149
VGMA13 + (VGMA12 - VGMA13) × 598 / 2149
VGMA13 + (VGMA12 - VGMA13) × 632 / 2149
VGMA13 + (VGMA12 - VGMA13) × 665 / 2149
VGMA13 + (VGMA12 - VGMA13) × 698 / 2149
VGMA13 + (VGMA12 - VGMA13) × 732 / 2149
VGMA13 + (VGMA12 - VGMA13) × 765 / 2149
VL152
VL153
VL154
VL155
VL156
VL157
VL158
VL159
VGMA13 + (VGMA12 - VGMA13) × 798 / 2149
VGMA13 + (VGMA12 - VGMA13) × 831 / 2149
VGMA13 + (VGMA12 - VGMA13) × 864 / 2149
VGMA13 + (VGMA12 - VGMA13) × 897 / 2149
VGMA13 + (VGMA12 - VGMA13) × 930 / 2149
VGMA13 + (VGMA12 - VGMA13) × 963 / 2149
VGMA13 + (VGMA12 - VGMA13) × 996 / 2149
VGMA13 + (VGMA12 - VGMA13) × 1029 / 2149
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670
Table 2. Relationship between Input Data and Output Voltage Value (12)
Input
data
A0H
A1H
A2H
A3H
A4H
A5H
A6H
A7H
A8H
A9H
AAH
ABH
ACH
ADH
AEH
AFH
B0H
B1H
B2H
B3H
B4H
B5H
B6H
B7H
B8H
B9H
BAH
BBH
BCH
BDH
BEH
BFH
C0H
C1H
C2H
C3H
C4H
C5H
C6H
C7H
DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
G/S
Output voltage
VL160
VL161
VL162
VL163
VL164
VL165
VL166
VL167
VGMA13 + (VGMA12 - VGMA13) × 1062 / 2149
VGMA13 + (VGMA12 - VGMA13) × 1094 / 2149
VGMA13 + (VGMA12 - VGMA13) × 1127 / 2149
VGMA13 + (VGMA12 - VGMA13) × 1159 / 2149
VGMA13 + (VGMA12 - VGMA13) × 1192 / 2149
VGMA13 + (VGMA12 - VGMA13) × 1224 / 2149
VGMA13 + (VGMA12 - VGMA13) × 1257 / 2149
VGMA13 + (VGMA12 - VGMA13) × 1289 / 2149
VL168
VL169
VL170
VL171
VL172
VL173
VL174
VL175
VGMA13 + (VGMA12 - VGMA13) × 1322 / 2149
VGMA13 + (VGMA12 - VGMA13) × 1354 / 2149
VGMA13 + (VGMA12 - VGMA13) × 1387 / 2149
VGMA13 + (VGMA12 - VGMA13) × 1419 / 2149
VGMA13 + (VGMA12 - VGMA13) × 1452 / 2149
VGMA13 + (VGMA12 - VGMA13) × 1485 / 2149
VGMA13 + (VGMA12 - VGMA13) × 1517 / 2149
VGMA13 + (VGMA12 - VGMA13) × 1550 / 2149
VL176
VL177
VL178
VL179
VL180
VL181
VL182
VL183
VGMA13 + (VGMA12 - VGMA13) × 1583 / 2149
VGMA13 + (VGMA12 - VGMA13) × 1617 / 2149
VGMA13 + (VGMA12 - VGMA13) × 1650 / 2149
VGMA13 + (VGMA12 - VGMA13) × 1684 / 2149
VGMA13 + (VGMA12 - VGMA13) × 1717 / 2149
VGMA13 + (VGMA12 - VGMA13) × 1752 / 2149
VGMA13 + (VGMA12 - VGMA13) × 1786 / 2149
VGMA13 + (VGMA12 - VGMA13) × 1821 / 2149
VL184
VL185
VL186
VL187
VL188
VL189
VL190
VL191
VGMA13 + (VGMA12 - VGMA13) × 1856 / 2149
VGMA13 + (VGMA12 - VGMA13) × 1891 / 2149
VGMA13 + (VGMA12 - VGMA13) × 1927 / 2149
VGMA13 + (VGMA12 - VGMA13) × 1963 / 2149
VGMA13 + (VGMA12 - VGMA13) × 1999 / 2149
VGMA13 + (VGMA12 - VGMA13) × 2036 / 2149
VGMA13 + (VGMA12 - VGMA13) × 2073 / 2149
VGMA13 + (VGMA12 - VGMA13) × 2111 / 2149
VL192
VL193
VL194
VL195
VL196
VL197
VL198
VL199
VGMA12
VGMA12 + (VGMA11 - VGMA12) × 38 / 3080
VGMA12 + (VGMA11 - VGMA12) × 77 / 3080
VGMA12 + (VGMA11 - VGMA12) × 116 / 3080
VGMA12 + (VGMA11 - VGMA12) × 155 / 3080
VGMA12 + (VGMA11 - VGMA12) × 195 / 3080
VGMA12 + (VGMA11 - VGMA12) × 235 / 3080
VGMA12 + (VGMA11 - VGMA12) × 276 / 3080
23
S6C0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
Table 2. Relationship between Input Data and Output Voltage Value (13)
Input
data
C8H
C9H
CAH
CBH
CCH
CDH
CEH
CFH
D0H
D1H
D2H
D3H
D4H
D5H
D6H
D7H
D8H
D9H
DAH
DBH
DCH
DDH
DEH
DFH
E0H
E1H
E2H
E3H
E4H
E5H
E6H
E7H
E8H
E9H
EAH
EBH
ECH
EDH
EEH
EFH
24
DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
G/S
Output voltage
VL200
VL201
VL202
VL203
VL204
VL205
VL206
VL207
VGMA12 + (VGMA11 - VGMA12) × 316 / 3080
VGMA12 + (VGMA11 - VGMA12) × 357 / 3080
VGMA12 + (VGMA11 - VGMA12) × 399 / 3080
VGMA12 + (VGMA11 - VGMA12) × 440 / 3080
VGMA12 + (VGMA11 - VGMA12) × 482 / 3080
VGMA12 + (VGMA11 - VGMA12) × 524 / 3080
VGMA12 + (VGMA11 - VGMA12) × 566 / 3080
VGMA12 + (VGMA11 - VGMA12) × 609 / 3080
VL208
VL209
VL210
VL211
VL212
VL213
VL214
VL215
VGMA12 + (VGMA11 - VGMA12) × 651 / 3080
VGMA12 + (VGMA11 - VGMA12) × 694 / 3080
VGMA12 + (VGMA11 - VGMA12) × 738 / 3080
VGMA12 + (VGMA11 - VGMA12) × 782 / 3080
VGMA12 + (VGMA11 - VGMA12) × 826 / 3080
VGMA12 + (VGMA11 - VGMA12) × 871 / 3080
VGMA12 + (VGMA11 - VGMA12) × 916 / 3080
VGMA12 + (VGMA11 - VGMA12) × 962 / 3080
VL216
VL217
VL218
VL219
VL220
VL221
VL222
VL223
VGMA12 + (VGMA11 - VGMA12) × 1009 / 3080
VGMA12 + (VGMA11 - VGMA12) × 1057 / 3080
VGMA12 + (VGMA11 - VGMA12) × 1106 / 3080
VGMA12 + (VGMA11 - VGMA12) × 1157 / 3080
VGMA12 + (VGMA11 - VGMA12) × 1209 / 3080
VGMA12 + (VGMA11 - VGMA12) × 1263 / 3080
VGMA12 + (VGMA11 - VGMA12) × 1320 / 3080
VGMA12 + (VGMA11 - VGMA12) × 1379 / 3080
VL224
VL225
VL226
VL227
VL228
VL229
VL230
VL231
VGMA12 + (VGMA11 - VGMA12) × 1441 / 3080
VGMA12 + (VGMA11 - VGMA12) × 1506 / 3080
VGMA12 + (VGMA11 - VGMA12) × 1574 / 3080
VGMA12 + (VGMA11 - VGMA12) × 1647 / 3080
VGMA12 + (VGMA11 - VGMA12) × 1724 / 3080
VGMA12 + (VGMA11 - VGMA12) × 1805 / 3080
VGMA12 + (VGMA11 - VGMA12) × 1892 / 3080
VGMA12 + (VGMA11 - VGMA12) × 1983 / 3080
VL232
VL233
VL234
VL235
VL236
VL237
VL238
VL239
VGMA12 + (VGMA11 - VGMA12) × 2081 / 3080
VGMA12 + (VGMA11 - VGMA12) × 2184 / 3080
VGMA12 + (VGMA11 - VGMA12) × 2293 / 3080
VGMA12 + (VGMA11 - VGMA12) × 2409 / 3080
VGMA12 + (VGMA11 - VGMA12) × 2530 / 3080
VGMA12 + (VGMA11 - VGMA12) × 2658 / 3080
VGMA12 + (VGMA11 - VGMA12) × 2792 / 3080
VGMA12 + (VGMA11 - VGMA12) × 2933 / 3080
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670
Table 2. Relationship between Input Data and Output Voltage Value (14)
Input
data
F0H
F1H
F2H
F3H
F4H
F5H
F6H
F7H
F8H
F9H
FAH
FBH
FCH
FDH
FEH
FFH
DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
G/S
Output voltage
VL240
VL241
VL242
VL243
VL244
VL245
VL246
VL247
VGMA11
VGMA11 + (VGMA10 - VGMA11) × 154 / 4641
VGMA11 + (VGMA10 - VGMA11) × 314 / 4641
VGMA11 + (VGMA10 - VGMA11) × 482 / 4641
VGMA11 + (VGMA10 - VGMA11) × 659 / 4641
VGMA11 + (VGMA10 - VGMA11) × 846 / 4641
VGMA11 + (VGMA10 - VGMA11) × 1045 / 4641
VGMA11 + (VGMA10 - VGMA11) × 1260 / 4641
VL248
VL249
VL250
VL251
VL252
VL253
VL254
VL255
VGMA11 + (VGMA10 - VGMA11) × 1498 / 4641
VGMA11 + (VGMA10 - VGMA11) × 1768 / 4641
VGMA11 + (VGMA10 - VGMA11) × 2086 / 4641
VGMA11 + (VGMA10 - VGMA11) × 2482 / 4641
VGMA11 + (VGMA10 - VGMA11) × 3014 / 4641
VGMA11 + (VGMA10 - VGMA11) × 3825 / 4641
VGMA10
VGMA9
25
S6C0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
ABSOLUTE MAXIMUM RATINGS
Table 3. Absolute Maximum Ratings (VSS1 = VSS2 = 0 V)
Parameter
Logic supply voltage
Driver supply voltage
Input voltage
Output voltage
Operating power dissipation
Operation temperature
Storage temperature
Symbol
VDD1
VDD2
VGMA1 - 16
Others
DIO1, 2
Y1 – Y402
Pd
Top
Tstg
Ratings
-0.3 to 5.0
-0.3 to 16
-0.3 to VDD2+0.3
-0.3 to VDD1+0.3
-0.3 to VDD1+0.3
-0.3 to VDD2+0.3
300 (1)
-20 to 75
-55 to 125
Unit
V
V
V
V
mW
°C
°C
CAUTIONS:
If LSIs are stressed beyond those listed above “absolute maximum ratings”, they may be permanently
destroyed. These are stress ratings only, and functional operation of the device at these or any other
condition beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability.
Turn on power order: VDD1 → control signal input → VDD2 → VGMA1 - VGMA16
Turn off power order: VGMA1 - VGMA16 → VDD2 → control signal input → VDD1
RECOMMENDED OPERATION CONDITIONS
Table 4. Recommended Operation Conditions (Ta = -20 to 75 °C, VSS1 = VSS2 = 0 V)
Parameter
Logic supply voltage
Driver supply voltage
Gamma corrected voltage
Driver part output voltage
Maximum clock frequency
(Single edge/Double edge)
Output load capacitance
Symbol
VDD1
VDD2 (1)
VGMA1 – VGMA8
VGMA9 – VGMA16
Vyo
fmax
(1)
CL
Min.
Typ.
2.5
3.3
8.0
12.0
0.5 VDD2
VSS2 + 0.1
VSS2 + 0.1
VDD1 = 2.5 V
VDD1 = 3.0 V
-
Max.
3.6
15.0
VDD2 - 0.1
0.5 VDD2
VDD2 - 0.1
55 / 40
75 / 55
200
NOTE: 1. Relationship between TFT-LCD panel and Pd (Pd ∝ CL * (VDD2) * fCLK1)
2
TFT-LCD panel standard
SXGA
UXGA & WUXGA
26
CL = 140pF
max. VDD2 = 15 V
max. VDD2 = 14 V
CL = 200pF
max. VDD2 = 13 V
max. VDD2 = 12 V
Unit
V
V
V
V
V
MHz
pF / PIN
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670
DC CHARACTERISTICS
Table 5. DC Characteristics (Ta = -20 to 75 °C, VDD1 = 2.5 to 3.6 V, VDD2 = 8 to 15 V, VSS1 = VSS2 = 0 V)
Parameter
High level input voltage
Low level input voltage
Input leakage current
High level output
voltage
Low level output voltage
Resistor
Symbol
VIH
VIL
IL
Condition
SHL, CLK2, D00 - D57, CLK1,
SELT, DATPOL1, DATPOL2,
DEC, POL, DIO1 (DIO2)
Min.
0.8 VDD1
0
-1
Typ.
-
Max.
VDD1
0.2 VDD1
1
VOH
DIO1 (DIO2), IO = -1.0 mA
VDD1 - 0.5
-
-
VOL
R0 R254
DIO1 (DIO2), IO = +1.0 mA
Refer to Table 1. Resistor
Strings
VDD2 = 10.0 V,
Vx = 3.5 V, Vyo = 9.5 V(1)
VDD2 = 10.0 V,
Vx = 6.5 V, Vyo = 0.5 V(1)
VSS2 + 0.1 V to VDD2 - 1.5 V
VDD2 - 1.5 V to VDD2 - 0.1 V
-
-
0.5
IVOH
Driver output current
IVOL
Rn × 0.7
V
µA
V
Rn × 1.3
Ω
-
-2.0
-1.0
mA
1.0
2.0
-
mA
-
±7
±10
±15
±20
mV
Output voltage deviation
∆VO
Output RMS voltage
deviation
dVrms(2)
Input data: 00H to FFH
-
±3
±10
Output voltage range
Vyo
Input data: 00H to FFH
VSS2 +
0.1
-
VDD2 –
0.1
IDD1
VDD1 = 3.0 V (3)
-
4.0
7.0
IDD2
VDD2 = 10 V (4)
-
10.0
15.0
Logic part dynamic
current
Driver part dynamic
current
Unit
V
mA
NOTES:
1. Vyo is the output voltage of analog output pins Y1 to Y402.
Vx is the voltage applied to analog output pins Y1 to Y402.
2. dVrms is a maximum deviation value from ideal difference between high output and low output at the same gray scale.
3. CLK1 period is defined to be 15.6 µs at fCLK2 = 54 MHz, DEC = L, data pattern = 10101010
(checkerboard pattern), Ta = 25 °C.
4, Yout Load Condition
2kΩ
4kΩ
4kΩ
YOUT
20pF
VCOM = 0.5 VDD2
2kΩ
40pF
4kΩ
20pF
4kΩ
Figure 5. Yout Load Condition
27
S6C0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
SINGLE EDGE AC CHARACTERISTICS
Table 6. AC Characteristics (Ta = -20 to 75 °C, VDD2 = 8 to 15 V, VSS1 = VSS2 = 0 V, DEC = L)
Parameter
Clock pulse width
Clock pulse low period
Clock pulse high
period
Data setup time
Data hold time
Start pulse setup time
Start pulse hold time
DATPOL-CLK2 setup
time
DATPOL-CLK2 hold
time
Start pulse delay time
CLK1 setup time
Driver output delay
time1
Driver output delay
time2
CLK1 pulse high
period
Data invalid period
Last data timing
CLK1-CLK2 time
POL-CLK1 time
28
Symbol
Condition
VDD1 =
2.5 to 3.0 V
VDD1 =
3.0 to 3.6 V
PWCLK
PWCLK(L)
-
Min.
18
3
Max.
-
Min.
13
2
Max.
-
PWCLK(H)
-
3
-
2
-
tSETUP1
tHOLD1
tSETUP2
tHOLD2
-
3
0
3
0
-
2
0
2
0
-
tSETUP4
-
3
-
2
-
tHOLD4
-
0
-
0
-
tPLH1
CL = 20 pF
-
15
-
11
tSETUP3
-
2
-
2
-
tPHL1
-
4
-
4
tPHL2
PWCLK1 = 1 µs,
Refer Figure 5. Yout
Load Condition
-
8
-
8
PWCLK1
-
(3CLK2)
2
(3CLK2)
2
tINV
tLDT
tCLK1-CLK2
tPOL-CLK1
CLK1↑ or ↓ → CLK2↑
POL↑ or ↓ → CLK1↑
1
1
8
8
-
1
1
6
6
-
Unit
ns
CLK2
period
µs
CLK2
period
ns
ns
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670
DOUBLE EDGE AC CHARACTERISTICS
Table 7. AC Characteristics (Ta = -20 to 75 °C, VDD2 = 8 to 15 V, VSS1 = VSS2 = 0 V, DEC = H)
Parameter
Clock pulse width
Clock pulse low period
Clock pulse high
period
Data setup time
Data hold time
Start pulse setup time
Start pulse hold time
DATPOL-CLK2 setup
time
DATPOL-CLK2 hold
time
Start pulse delay time
CLK1 setup time
Driver output delay
time1
Driver output delay
time2
CLK1 pulse high
period
Data invalid period
Last data timing
CLK1-CLK2 time
POL-CLK1 time
Symbol
Condition
VDD1 =
2.5 to 3.0 V
VDD1 =
3.0 to 3.6 V
PWCLK
PWCLK(L)
-
Min.
25
4
PWCLK(H)
-
4
-
3
-
tSETUP1
tHOLD1
tSETUP2
tHOLD2
-
4
0
4
0
-
3
0
3
0
-
tSETUP4
-
4
-
3
-
tHOLD4
-
0
-
0
-
tPLH1
CL = 20 pF
-
15
-
15
tSETUP3
-
1
-
1
-
tPHL1
-
4
-
4
tPHL2
PWCLK1 = 1 µs ,
Figure 5. Yout Load
Condition
-
8
-
8
PWCLK1
-
(3CLK2)
2
(3CLK2)
2
tINV
tLDT
tCLK1-CLK2
tPOL-CLK1
-
0.5
1
8
8
-
0.5
1
6
6
-
CLK1↑ or ↓ → CLK2↑
POL↑ or ↓ → CLK1↑
Max.
-
Min.
18
3
Max.
-
Unit
ns
CLK2
period
µs
CLK2
period
ns
ns
29
30
Figure 6. Waveforms, DEC = L
POL
tPOL-CLK1
LAST
DATA
tLDT
tHOLD4
tHOLD1
DXX
HI-Z
PWCLK1
tHOLD2
tSETUP4
tSETUP1
1st
DATA
1st
PWCLK(L)
0.5VDD1
tSETUP3
tSETUP2
INVALID DATA
tINV
CLK1
CLK2
Y(1:402)
CLK1
DIO2 output
(DIO1 output)
DIO1 input
(DIO2 input)
DATPOL1
DATPOL2
DXX
CLK2
PWCLK
tCLK1-CLK2
tPHL2
tPHL1
VIH
VIL
Target output voltage
Target output voltage 90%
tPLH1
LAST-1 LAST
INVALID DATA
PWCLK(H)
S6C0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
SINGLE EDGE WAVEFORMS (VIH = 0.8 VDD1, VIL = 0.2 VDD1)
POL
DXX
CLK1
CLK2
Y(1:402)
CLK1
DIO2 output
(DIO1 output)
DIO1 input
(DIO2 input)
DATPOL1
DATPOL2
DXX
CLK2
tSETUP3
tSETUP2
INVALID DATA
PWCLK
1st
tPOL-CLK1
LAST
DATA
tLDT
tHOLD1
0.5VDD1
tHOLD4
tHOLD1
2nd
tSETUP1
HI-Z
PWCLK1
tHOLD2
tSETUP4
tSETUP1
1st
DATA
tINV
LAST-2
LAST
Target output voltage
Target output voltage 90%
tPLH1
LAST-1
PWCLK(L)
INVALID DATA
tCLK1-CLK2
tPHL2
tPHL1
PWCLK(H)
VIH
VIL
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670
DOUBLE EDGE WAVEFORMS (VIH = 0.8 VDD1, VIL = 0.2 VDD1)
Figure 7. Waveforms, DEC = H
31
32
Figure 8. Waveforms
Y2N:even
number output
Y2N-1:odd
number output
POL
CLK1
DXX
CLK1
DIO1 input
(DIO2 input)
CLK2
Nth
DATA
Last data
N-1th
DATA
VGMA9 - VGMA16
VGMA1 - VGMA8
HI-Z
VGMA1- VGMA8
VGMA9 - VGMA16
VGMA1 - VGMA8
HI-Z
First data in
the next line
2nd
DATA
1/2CLK2 (DEC = H )
1st
DATA
VGMA9 - VGMA16
HI-Z
blanking time = Min. 4CLK2
INVALID DATA
Charge sharing period
tLDT
2CLK2(Min.)
0.5VDD1
HI-Z
S6C0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND
BLANKING PERIOD