Ordering number : ENN6171 CMOS IC LC72344W, 72345W Low-Voltage ETR Controller with On-Chip DC-DC Converter Overview Package Dimensions The LC72344W and LC72345W are low-voltage electronic tuning microcontrollers that include a DC-DC converter, a PLL that operates up to 230 MHz, a 1/4 duty 1/2 bias LCD driver and other functions on chip. The built-in DC-DC converter provided by these ICs can easily implement a tuning system voltage generator circuit, and furthermore, since the transistor required for the low-pass filter is built in, these ICs can contribute to further end product cost reductions. Additionally, the DC-DC converter output voltage can be provided to other external ICs, making these products optimal for low-voltage portable audio equipment that includes a radio receiver. unit: mm 3190-SQFP64 [LC72344W, 72345W] 12.0 10.0 1.25 1.25 0.15 33 0.5 12.0 10.0 1.25 32 1 1.7max 17 64 16 0.1 • Program memory (ROM): 3072 × 16 bits (6 KB) LC72344W 4096 × 16 bits (8 KB) LC72345W • Data memory (RAM): 192 × 4 bits LC72344W 256 × 4 bits LC72345W • Cycle time: 40 µs (all 1-word instructions) • Stack: 8 levels • LCD driver: 48 to 76 segments (1/4 duty, 1/2 bias drive) • Interrupts: One external interrupt Timer interrupts (1, 5, 10, and 50 ms) • A/D converter: Two input channels (5-bit successive approximation conversion) • Input ports: 6 ports (of which 2 can be switched for use as A/D converter inputs) • Output ports: 6 ports (of which 1 can be switched for use as the beep tone output and 2 are opendrain ports) • I/O ports: 16 ports (of which 8 can be switched for use as LCD ports as mask options) 0.18 49 1.25 Functions 0.5 48 0.5 0.5 SANYO: SQFP64 (Continued on next page.) Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 31000RM (OT) No. 6171-1/13 LC72344W, 72345W (Continued from preceding page.) • PLL: Supports dead band control (two types) Reference frequencies: 1, 3, 5, 6.25, 12.5, and 25 kHz • Input frequencies: FM band: 10 to 230 MHz AM band: 0.5 to 10 MHz • Input sensitivity: FM band: 35 mV rms (50 mV rms at 130 MHz or higher frequency) AM band: 35 mV rms • External reset input: During CPU and PLL operation, instruction execution is started from location 0. • Built-in power-on reset circuit: The CPU starts executing from location 0 when power is first applied. • Static power-on function: Backup state clear function using the BATT pin. • • • • • • • • • Halt mode: The controller operating clock is stopped. Backup mode: The crystal oscillator is stopped. Beep tone: 1.5 and 3.1 kHz Built-in DC-DC converter: Two systems (One system can be used as an external circuit power supply by providing an external transistor.) Built-in low-pass filter amplifier: An external low-pass filter amplifier circuit is no longer required in end products. Remaining power check function: The battery voltage can be directly converted to a digital value by the A/D converter. Memory retention voltage: 0.9 V or higher. VDD voltage: 0.9 to 1.8 V Package: SQFP-64 (0.5 mm lead pitch) 49 S1 50 COM4 51 COM3 52 COM2 53 COM1 54 BRES 55 VDD 56 FMIN 57 AMIN 58 VSS 59 EO 60 AIN 61 AOUT 62 AGND 63 TEST1 64 XIN Pin Assignment XOUT 1 48 S2 TEST2 2 47 S3 PA3 3 46 S4 PA2 4 45 S5 PA1 5 44 S6 PA0 6 43 S7 PB3 7 42 S8 PB2 8 PB1 9 40 S10 PB0 10 39 S11 PC3 11 38 S12/PH0 PC2 12 37 S13/PH1 PC1 13 36 S14/PH2 PC0 14 35 S15/PH3 PD3 15 34 S16/PG0 PD2 16 33 S17/PG1 29 30 31 32 VCON VADJ PG3/S19 PG2/S18 25 VDC3 28 24 VDC1 VREF 23 ADI0/PF0 27 22 ADI1/PF1 VDC2 21 BATT 41 S9 VSS 26 20 BEEP/PE0 PE1 19 18 INT/PD0 PD1 17 LC72344W LC72345W (Top view) No. 6171-2/13 LC72344W, 72345W Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol Maximum supply voltage Input voltage Output voltage Output current Allowable power dissipation Conditions Ratings Unit VDD(1)max VDD –0.3 to +0.3 V VDD(2)max VDC1 –0.3 to +4.0 V VDD(3)max VDC2 –0.3 to +4.0 V VDD(4)max VDC3 –0.3 to +4.0 V VIN(1) PF, FMIN, AMIN, AIN, BATT, and BRES –0.3 to VDD(3) to +0.3 V VIN(2) PA, PC, PD, PG, and PH –0.3 to VDD(1) to +0.3 V VOUT(1) AOUT, and PE –0.3 to +15 VOUT(2) V PB, PC, PD, PG, and PH –0.3 to VDD(1) +0.3 V VOUT(3) VREF, and EO –0.3 to VDD(3) +0.3 V VOUT(4) COM1 to COM4, S1 to S19 –0.3 to VDD(4) +0.3 IOUT(1) PC, PD, PG, PH, and EO 0 to 3 mA IOUT(2) PB 0 to 1 mA IOUT(3) AOUT, and PE 0 to 2 mA IOUT(4) S1 to S20 IOUT(5) COM1 to COM4 Pdmax Ta = –20 to +70°C V 300 µA 3 mA 200 mW Operating temperature Topr –20 to +70 °C Storage temperature Tstg –45 to +125 °C Allowable Operating Ranges at Ta = –20 to +70°C, VDD = 0.9 to 1.8 V Parameter Supply voltage Input high-level voltage Input low-level voltage Input amplitude Input voltage range Input frequency Symbol Conditions Ratings min typ Unit max VDD(1) The voltage applied to the VDD pin 0.9 1.5 1.8 V VDD(2) The voltage applied to the VDC1 pin 0.9 1.5 1.8 V VDD(3) The voltage applied to the VDC2 pin 1.8 2.1 2.4 V VDD(4) The voltage applied to the VDC3 pin 2.6 3.0 3.4 VDD(5) Memory retention voltage 0.9 V V VIH(1) Ports PC, PD, PG, and PH 0.7 VDD(1) VDD(1) V VIH(2) Port PA 0.8 VDD(1) VDD(1) V VIH(3) Port PF 0.8 VDD(1) VDD(3) V VIH(4) Ports BRES and BATT 0.6 VDD(1) VDD(3) V VIL(1) Ports PC, PD, PG, and PH 0 0.3 VDD(1) V VIL(2) Port PA 0 0.2 VDD(1) V VIL(3) Port PF 0 0.2 VDD(1) V VIL(4) Ports BRES and BATT 0 0.2 VDD(1) VIN(1) XIN 0.5 0.6 Vrms 0.035 0.35 Vrms 0.05 0.35 Vrms VIN(2) FMIN, AMIN: VDD(3) = 2.1 V VIN(3) FMIN: VIN(4) ADI0, ADI1, and VDD FIN(1) XIN: FIN(2) FMIN: VIN(2), VDD(3) = 2.1 V FIN(3) FMIN: VIN(3), VDD(3) = 2.1 V FIN(4) AMIN(L): VIN(2), VDD(3) = 2.1 V 0.5 VDD(3) = 2.1 V CI ≤ 35 kΩ 0 70 VDD(4) 75 V V 80 kHz 10 130 MHz 130 230 MHz 10 MHz No. 6171-3/13 LC72344W, 72345W Electrical Characteristics under allowable operating conditions Parameter Input high-level voltage Input low-level voltage Input floating voltage Pull-down resistor Hysteresis Output high-level voltage Output low-level voltage Output off leakage current Symbol IIH(1) XIN: VDD(1) = 1.8 V, VDD(2) = 1.8 V, VDD(3) = 2.1 V IIH(2) FMIN, and AMIN: VDD(3) = 2.1 V IIH(3) Current drain Ratings min typ Unit max 3 µA 20 µA Ports BRES, BATT, and PF: VDD(3) = 2.1 V 4 µA IIH(4) Ports PA (no pull-down resistor), PC, PD, PG, and PH: VDD(1) = 1.8 V 3 µA IIL(1) XIN: VDD(1) = VDD(2) = VDD(3) = VSS –3 µA IIL(2) FMIN, and AMIN: VDD(3) = VSS IIL(3) IIL(4) VIF RPD(1) RPD(2) 3 –3 8 –8 –20 µA Ports BRES, BATT, and PF: VDD(3) = VSS –4 µA Ports PA (no pull-down resistor), PC, PD, PG, and PH: VDD(1) = VSS –3 µA Port PA pull-down resistor present Port PA pull-down resistor: VDD(1) = 1.3 V 0.05 VDD(1) 75 TEST1 and TEST2 pull-down resistors 100 200 10 V kΩ kΩ BRES 0.1 VDD(3) 0.2 VDD(3) VOH(1) PB: IO = 1 mA VDD(1) – 0.7 VDD(1) VOH(2) PC, PD, PG, PH: IO = 1 mA VDD(1) – 0.3 VDD(1) V VOH(3) EO: IO = –500 µA VDD(3) – 0.3 VDD(3) V VOH(4) XOUT IO = 1 µA VDD(3) – 0.3 VDD(3) V VH V VDD(1) – 0.3 VDD(1) V VOH(5) S1 to S20: IO = 20 µA VDD(4) – 1 V VOH(6) COM1, CM2, COM3, and COM4: IO = 100 µA VDD(4) – 1 V VOH(7) VREF: IO = 1 mA VDD(3) – 1 VOL(1) PB: IO = –50 µA 0.3 VDD(1) VOL(2) VOL(3) V 0.7 VDD(1) V PC, PD, PG, and PH: IO = –1 mA 0.3 VDD(1) V EO: IO = –500 µA 0.3 VDD(3) V VOL(4) XOUT: IO = –1 µA 0.3 VDD(3) V VOL(5) S1 to S20: IO = –20 µA VDD(4)–2 V VOL(6) COM1, COM2, COM3, and COM4: IO = –100 µA VDD(4)–2 V VOL(7) PE: IO = 2 mA 0.6 VDD(1) V VOL(8) AOUT: IO = 1 mA, AIN = 1.3 V: VDD(4) = 3 V IOFF(1) PB, PC, PD, PG, PH, and E0 ports IOFF(2) AOUT and PE ports –100 100 nA ADI0 and ADI1, VDD –1/2 +1/2 LSB A/D converter error Internal clock frequency Conditions –3 600 0.5 V 3 µA fosc(1) FM, and PLLSTOP: VDD(3) = 2.1 V, Vcon = OPEN 300 fosc(2) AM 450 900 kHz 1200 kHz IDD1(1) VDD(1) = 1.5 V, VDD(3) = 2.1 V, VDD(4) = 3.0 V: FIN(2) 130 MHz, Ta = 25°C 1 mA IDD2(2) VDD(1) = 1.5 V, VDD(3) = 2.1 V, VDD(4) = 3.0 V: FIN(2) 130 MHz, Ta = 25°C 5 mA IDD3(3) VDD(1) = 1.5 V, VDD(3) = 2.1 V, VDD(4) = 3.0 V: FIN(2) 130 MHz, Ta = 25°C 1 mA IDD1(4) VDD(1) = 1.5 V, VDD(3) = 2.1 V, VDD(4) = 3.0 V: Halt mode, Ta = 25°C *1 0.1 mA IDD2(5) VDD(1) = 1.5 V, VDD(3) = 2.1 V, VDD(4) = 3.0 V: Halt mode, Ta = 25°C *1 0.3 mA IDD3(6) VDD(1) = 1.5 V, VDD(3) = 2.1 V, VDD(4) = 3.0 V: Halt mode, Ta = 25°C *1 0.1 mA IDD1(7) VDD(1) = 1.5 V, VDD(3) = 2.1 V, VDD(4) = 3.0 V: With the oscillator stopped, Ta = 25°C * 100 nA IDD2(8) VDD(1) = 1.5 V, VDD(3) = 2.1 V, VDD(4) = 3.0 V: With the oscillator stopped, Ta = 25°C * 500 nA IDD3(9) VDD(1) = 1.5 V, VDD(3) = 2.1 V, VDD(4) = 3.0 V: With the oscillator stopped, Ta = 25°C * 100 nA The halt mode current drain is due to 20 instructions being executed every 125 ms. No. 6171-4/13 LC72344W, 72345W *1 Halt mode current drain test conditions *2 Backup mode current drain test conditions IDD1 A 7 pF 1.5 V 75 kHz XOUT XIN 7 pF VDD RES XOUT VDC2 IDD2 A 2.2 V VDC3 A 3V IDD3 VSS FMIN 1.5 V 75 kHz PA,PF AIN IDD1 A 7 pF BATT AMIN XIN 7 pF RES VDC2 IDD2 A 2.2 V VDC3 A 3V AIN IDD3 VSS FMIN BATT AMIN AGND AGND TEST1, 2 TEST1, 2 Leave all ports other than those mentioned above open. Select output mode for PC and PD. Select the segment function for S12 to S19. VDD Leave all ports other than those mentioned above open. Select output mode for PC and PD. Select the segment function for S12 to S19. No. 6171-5/13 LC72344W, 72345W Block Diagram DIVIDER XIN REFERENCE DIVIDER PHASE DETECTOR EO SYSTEM CLOCK GENERATOR XOUT 1/2 FMIN 1/16,1/17 PROGRAMMBLE DIVIDER AMIN 1/2 PLL DATA LATCH PLL CONTROL 1/2 1/2 VSS COUNT END TIME BASE CONTROL 4 UNIVERSAL COUNTER (20 bits) RES S1 LCDA/B SEG 7 LA 80 LCPA/B * S11 P-ON RESET RAM 192 × 4 bits (LC72344) 256 × 4 bits (LC72345) TEST1 TEST2 PA0 ADDRESS DECODER BANK BUS DRIVER PA1 PA2 PA3 BUS CONTROL ROM PB0 PB1 PB2 PB3 PC0 PC1 PC2 PC3 INT/PD0 PD1 PD2 PD3 * DATA LATCH / BUS DRIVER DATA LATCH / BUS DRIVER DATA LATCH / BUS DRIVER 3k × 16 bits AGND S12/PH3 DATA LATCH / BUS DRIVER S16/PG3 S13/PH2 S14/PH1 S15/PH0 S17/PG2 S18/PG1 S19/PG0 4k × 16 bits INSTRUCTION DECODER (LC72345) SKIP ADDRESS DECORDER JMP CAL RETURN INTERRUPT RESET 14 ADDRESS COUNTER 14 BANK STACK COM4 COMMON DRIVER COM3 COM2 COM1 BEEP TONE CF JUDGE LATCH A DATA LATCH / BUS DRIVER PE0/BEEP MPX PE0/BEEP ALU VDC3 VDC1 DATA LATCH / BUS DRIVER (LC72344) AIN AOUT LCD PORT DRIVER LATCH B VDD VDC2 VCON MPX TIMER 0 VREF MPX (5 bits) VADJ DATA BUS DATA LATCH / BUS DRIVER PF0/ADI0 PF1/ADI1 BATT RC OSCILLATOR CIRCUIT No. 6171-6/13 LC72344W, 72345W Pin Functions Pin No. Pin I/O Function 64 XIN I 1 XOUT O 63 TEST1 I IC testing. 2 TEST2 I These pins must be connected to ground. 6 PA0 5 PA1 4 PA2 I 3 PA3 Special-purpose ports for key return signal input designed with a low threshold voltage. When a key matrix is formed in combination with port PB, simultaneous multiple key presses with up to 3 keys can be detected. The pull-down resistors are set up for all four pins at the same time with the IOS instruction (PWn = 2.b1). This setting cannot be specified for individual pins. In backup mode, these pins go to the input disabled state, and the pull-down resistors are disabled after a reset. I/O circuit 75 kHz crystal oscillator connections — Input with built-in pull-down resistor Unbalanced CMOS push-pull output 10 PB0 9 PB1 8 PB2 7 PB3 14 PC0 13 PC1 12 PC2 General-purpose I/O ports. 11 PC3 18 INT/PD0 PD0 can be used as an external interrupt port. The IOS instruction (Pwn = 4, 5) is used for switching the general-purpose I/O port function, and these ports can be set to input or output in 1-bit units. (0: input, 1: output) 17 PD1 In backup mode they go to the input disabled high-impedance state. 16 PD2 After a reset, they switch to the general-purpose input port function. 15 PD3 O Unbalanced CMOS outputs. These outputs are switched with the IOS 0 instruction. Since these outputs are unbalanced, no diodes are required to prevent short circuits due to simultaneous multiple key presses. These outputs go to the high-impedance output state in backup mode. After a reset, they go to the high-impedance output state and remain in that state until an output instruction (OUT, SPB, or RPB) is executed. CMOS push-pull output I/O (*) General-purpose output and beep tone output shared function ports (PE0 only). The BEEP instruction is used to switch PE0 between the general-purpose output port and beep tone output functions. To use PE0 as a general-purpose output port, execute a BEEP instruction N-channel open-drain output with b2 set to 0. Set b2 to 1 to use PE0 as the beep tone output port. The b0 and b1 bits are used to select the beep tone frequency. There are two beep tone frequencies supported. 20 BEEP/PE0 19 PE1 *: When PE0 is set up as the beep tone output, executing an output instruction to PN0 only changes the state of the internal output latch, it does not affect the beep tone output in any way. Only the PE0 pin can be switched between the general-purpose output function and the beep tone output function; the PE1 pin only functions as a general-purpose output. These pins go to the high-impedance state in backup mode and remain in that state until an output instruction or a BEEP instruction is executed. Since these ports are open-drain ports, resistors must be inserted between these pins and VDD. These ports are set to their generalpurpose output port function after a reset. Continued on next page. No. 6171-7/13 LC72344W, 72345W Continued from preceding page. Pin No. Pin I/O Function I/O circuit General-purpose input and A/D converter input shared function ports. 23 PF0/ADI0 22 PF1/ADI1 I The IOS instruction (Pwn = FH) is used to switch between the general-purpose input and A/D converter port functions. The general-purpose input and A/D converter port functions can be switched in a bit units, with 0 specifying general-purpose input, and 1 specifying the A/D converter input function. To select the A/D converter function, set up the A/D converter pin with an IOS instruction with Pwn set to 1. The A/D converter is started with the UCC instruction (b3 = 1, b2 = 1). The ADCE flag is set when the conversion completes. The INR instruction is used to read in the data. CMOS input/analog input *: If an input instruction is executed for one of these pins which is set up for analog input, the read in data will be at the low level since CMOS input is disabled. In backup mode these pins go to the input disabled high-impedance state. These ports are set to their general-purpose input port function after a reset. The A/D converter is a 5-bit successive approximation type converter, and features a conversion time of 1.28 ms. Note that the full-scale A/D converter voltage (1FH) is (63/96) times VDC3. LCD driver segment output and general-purpose I/O shared function ports. The IOS instruction* is used for switching both between the segment output and generalpurpose I/O functions and between input and output for the general-purpose I/O port function. • When used as segment output ports 31 PG3/S19 32 PG2/S18 33 PG1/S17 34 PG0/S16 CMOS push-pull output The general-purpose I/O port function is selected with the IOS instruction (Pwn = 8). b0 = S16 to 19/PG0 to 3 (0: Segment output, 1: PG0 to 3) The general-purpose I/O port function is selected with the IOS instruction (Pwn = 9). b0 = S12 to 15/PH0 to 3 (0: Segment output, 1: PH0 to 3) • When used as general-purpose I/O ports 35 PH3/S15 36 PH2/S14 37 PH1/S13 38 PH0/S12 O The IOS instruction (Pwn = 6,7) is used to select input or output. Note that the mode can be set in a bit units. b0 = PG0 b1 = PG1 b2 = PG2 b3 = PG3 (*) ( 0: Input 1: Output ) b0 = PH0 b1 = PH1 b2 = PH2 b3 = PH3 ( 0: Input 1: Output ) In backup mode, these pins go to the input disabled high-impedance state if set up as general-purpose outputs, and are fixed at the low level if set up as segment outputs. These ports are set up as segment outputs after a reset. Although the general-purpose port/LCD port setting is a mask option, the IOS instruction must be used as described above to set up the port function. CMOS push-pull output LCD driver segment output pins. A 1/4-duty 1/2-bias drive technique is used. 39 to 49 S11 to S1 O The frame frequency is 75 Hz. In backup mode, these outputs are fixed at the low level. After a reset, these outputs are fixed at the low level. LCD driver common output pins. 50 COM4 51 COM3 52 COM2 53 COM1 54 RES I 21 BATT I A 1/4-duty 1/2-bias drive technique is used. O The frame frequency is 75 Hz. In backup mode, these outputs are fixed at the low level. After a reset, these outputs are fixed at the low level. System reset input. In CPU operating mode or halt mode, applications must apply a low level for at least one full machine cycle to reset the system and restart execution with the PC set to location 0. This pin is connected in parallel with the internal power on reset circuit. Battery presence/absence discrimination. The internal clock oscillator starts when a high level is input to this pin. The IN instruction can be used to determine whether or not a battery is present. Continued on next page. No. 6171-8/13 LC72344W, 72345W Continued from preceding page. Pin No. Pin I/O Function 24 VDC1 I VDC3 (3 V) step-up control. 27 VDC2 I 2.1 V power supply. Apply either the voltage stepped-up by the DC-DC converter or an equivalent voltage (2.1 V typical). 25 VDC3 I 3 V power supply. Apply either the voltage stepped-up by VDC1 or an equivalent voltage (3 V typical). 28 VREF O VDC2 step-up transistor drive. 29 VCON I Frequency adjustment for the internal RC oscillator circuit. The RC oscillator frequency can be lowered by inserting a capacitor between this pin and ground. 30 VADJ O The VDC3 voltage can be adjusted by inserting a resistor between this pin and ground. I/O circuit CMOS amplifier input FM VCO (local oscillator) input. 56 FMIN I This pin is selected with the PLL instruction CW1. The input must be capacitor coupled. Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode. AM VCO (local oscillator) input. This pin and the bandwidth are selected with the PLL instruction CW1. 57 AMIN I CW1 b1, b0 Bandwidth 11 0.5 to 10 MHz (MW, LW) CMOS amplifier input The input must be capacitor coupled. Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode. CMOS push-pull output 59 EO O Main charge pump output. When the local oscillator frequency divided by N is higher than the reference frequency a high level is output, when lower, a low level is output, and the pin is set to the high-impedance state when the frequencies match. This output goes to the high-impedance state in backup mode, in halt mode, after a reset, and in PLL stop mode. 60 AIN 61 AOUT 62 AGND 26 VSS 58 VSS 55 VDD O Transistor used for the low-pass filter amplifier. Connect AGND to ground. Power supply pin. — This pin must be connected to ground. This pin must be connected to ground. — This pin must be connected to VDD. Supports A/D converter. Note: *Applications must establish the output data in advance with an OUT, SPB, or RPB instruction and then set the pin to output mode with an IOS instruction when using the I/O switchable ports as output pins. No. 6171-9/13 LC72344W, 72345W DC-DC Converter Application Sample VDC3 LCD, A/D converter, and power reset 3 V system comparator + VDC1 TU+B VDC2 Internal power supply VADJ 2.1 V system comparator + VREF FM mode Reference voltage AM mode VCON RC oscillator Local AM signal IC internal circuits VDD Supply voltage (0.9 to 1.8 V) Low-Pass Filter Application Sample EO IC internal circuits AIN Varactor AOUT TU+B AGND No. 6171-10/13 LC72344W, 72345W LC72344W and LC72345W Instruction Set Terminology Subtraction instructions Addition instructions Instruction group ADDR b C DH DL I M N Rn Pn PW r ( ), [ ] M (DH, DL) Mnemonic : Program memory address : Borrow : Carry : Data memory address High (Row address) [2 bits] : Data memory address Low (Column address) [4 bits] : Immediate data [4 bits] : Data memory address : Bit position [4 bits] : Resister number [4 bits] : Port number [4 bits] : Port control word number [4 bits] : General register (One of the address from 00H to 0FH of BANKO) : Contents of register or memory : Data memory specified by DH, DL Operand Function 1st 2nd AD r M Add M to r ADS r M AC r M M ACS r Operational function Instruction format f e d c b a r ← (r) + (M) 0 1 0 0 0 0 9 DH 8 7 6 DL 5 4 3 2 r 1 Add M to r, then skip if carry r ← (r) + (M), skip if carry 0 1 0 0 0 1 DH DL r Add M to r with carry r ← (r) + (M) + C 0 1 0 0 1 0 DH DL r Add M to r with carry, then skip if carry r ← (r) + (M) + C skip if carry 0 1 0 0 1 1 DH DL r AI M I Add I to M M ← (M) + I 0 1 0 1 0 0 DH DL I AIS M I Add I to M, then skip if carry M ← (M) + I, skip if carry 0 1 0 1 0 1 DH DL I AIC M I Add I to M with carry M ← (M) + I + C 0 1 0 1 1 0 DH DL I Add I to M with carry, then skip if carry M ← (M) + I + C, skip if carry 0 1 0 1 1 1 DH DL I AICS M I SU r M Subtract M from r r ← (r) – (M) 0 1 1 0 0 0 DH DL r r ← (r) – (M), skip if borrow 0 1 1 0 0 1 DH DL r SUS r M Subtract M from r, then skip if borrow SB r M Subtract M from r with borrow r ← (r) – (M) – b 0 1 1 0 1 0 DH DL r Subtract M from r with borrow, then skip if borrow r ← (r) – (M) – b, skip if borrow 0 1 1 0 1 1 DH DL r SBS r M SI M I Subtract I from M M ← (M) – I 0 1 1 1 0 0 DH DL I M ← (M) – I, skip if borrow 0 1 1 1 0 1 DH DL I SIS M I Subract I from M, then skip if borrow SIB M I Subtract I from M with borrow M ← (M) – I – b 0 1 1 1 1 0 DH DL I I Subtract I from M with borrow, then skip if borrow M ← (M) – I – b, skip if borrow 0 1 1 1 1 1 DH DL I SIBS M 0 Continued on next page. No. 6171-11/13 LC72344W, 72345W Jump and subroutine instructions Bit test instructions Transfer instructions Logical operation instructions Comparison instruction Instruction group Continued from preceding page. Mnemonic SEQ Operand 1st 2nd r M Function Operational function Instruction format f e d c b a 9 8 7 6 5 4 3 2 1 Skip if r equal to M (r) – (M), skip if zero 0 0 0 1 0 0 DH DL r SEQI M I Skip if M equal to I (M) – I, skip if zero 0 0 0 1 1 0 DH DL I SNEI M I Skip if M not equal to I (M) – I, skip if not zero 0 0 0 0 0 1 DH DL I (r) – (M), skip if not borrow 0 0 0 1 1 0 DH DL r (M) – I, skip if not borrow 0 0 0 1 1 1 DH DL I SGE r M Skip if r is greater than or equal to M SGEI M I Skip if M is greater than equal to I SLEI M I Skip if M is less than I (M) – I, skip if borrow 0 0 0 0 1 1 DH DL I AND r M AND M with r r ← (r) AND (M) 0 0 1 0 0 0 DH DL r ANDI M I AND I with M M ← (M) AND I 0 0 1 0 0 1 DH DL I OR r M OR M with r r ← (r) OR (M) 0 0 1 0 1 0 DH DL r ORI M I OR I with M M ← (M) OR I 0 0 1 0 1 1 DH DL I EXL r M Exclusive OR M with r r ← (r) XOR (M) 0 0 1 1 0 0 DH DL r EXLI M I Exclusive OR M with M M ← (M) XOR I 0 0 1 1 1 0 DH DL I 0 0 0 0 0 0 SHR r carry (r) Shift r right with carry 0 0 1 1 1 0 r LD r M Load M to r r ← (M) 1 1 0 1 0 0 DH DL r ST M r Store r to M M ← (r) 1 1 0 1 0 1 DH DL r [DH, Rn] ← (M) 1 1 0 1 1 0 DH DL r M ← [DH, Rn] 1 1 0 1 1 1 DH DL r MVRD r M Move M to destination M referring to r in the same row MVRS M r Move source M referring to r to M in the same row MVSR M1 M2 Move M to M in the same row [DH, DL1] ← [DH, DL2] 1 1 1 0 0 0 DH DL1 DL2 MVI M I Move I to M M←I 1 1 1 0 0 1 DH DL I if M (N) = all 1s, then skip 1 1 1 1 0 0 DH DL N 1 0 1 DH DL N TMT M N Test M bits, then skip if all bits specified are true TMF M N Test M bits, then skip if all bits specified are false if M (N) = all 0s, then skip 1 1 1 JMP ADDR Jump to the address PC ← ADDR 1 0 0 ADDR (13 bits) CAL ADDR Call subroutine PC ← ADDR Stack ← (PC) + 1 1 0 1 ADDR (13 bits) Return from subroutine PC ← Stack 0 0 0 0 0 0 0 0 1 0 0 0 Return from interrupt PC ← Stack, BANK ← Stack, CARRY ← Stack 0 0 0 0 0 0 0 0 1 0 0 1 RT RTI 0 No. 6171-12/13 LC72344W, LC72345W Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of March, 2000. Specifications and information herein are subject to change without notice. PS No. 6171-13/13