Ordering number :EN5544 CMOS LSI LC72P366 On-Chip One-Time Programmable PROM Single-Chip PLL Controller Overview Package Dimensions The LC72P366 is a single-chip PLL-plus-controller onetime programmable PROM microcontroller that corresponds to the Sanyo LC72358N, LC72362N, and LC72366. The LC72P366 has the same package and pin assignment as the LC72358N, LC72362N, and LC72366 mask ROM versions, and provides 32 KB of on-chip PROM, organized as 16k words by 16 bits. The LC72P366 can prove useful in reducing the startup times for initial production runs and for reducing the switchover time when end-product specifications change. unit: mm 3174-QFP80E [LC72P366] Features • 32 KB (16k words × 16 bits) of on-chip PROM — This is a one-time programmable 32 KB (16k-word × 16-bit) PROM. • Pin compatible with the mask ROM versions, i.e. identical package and pin assignment. Writing Sanyo ROMs Sanyo provides a for-fee ROM writing service that consists of writing data to the PROM in one-time programmable PROM microcontrollers, printing, screening, and data readout verification. Contact your Sanyo sales representative for details. SANYO: QIP80E • CCB is a trademark of SANYO ELECTRIC CO., LTD. • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN N3096HA (OT) No. 5544-1/14 LC72P366 Pin Assignment No. 5544-2/14 LC72P366 Block Diagram No. 5544-3/14 LC72P366 Specifications Absolute Maximum Ratings at Ta = 25˚C, VSS = 0 V Parameter Maximum supply voltage Input voltage Symbol VIN Output voltage Output current Allowable power dissipation Conditions Ratings VDD max Unit –0.3 to +6.5 All input pins V –0.3 to VDD +0.3 V –0.3 to +15 V VOUT(1) Port J VOUT(2) All output ports other than VOUT(1) IOUT(1) Port J 0 to +5 mA mA –0.3 to VDD +0.3 V IOUT(2) Ports D, E, F, G, K, L, M, N, O, P, and Q, EO1, EO2, EO3, SUBPD 0 to +3 IOUT(3) Ports B and C 0 to +1 mA Pd max Ta = –30 to +70˚C 400 mW Operating temperature Topr –30 to +70 ˚C Storage temperature Tstg –45 to +125 ˚C Allowable Operating Ranges at Ta = –30 to +70˚C, VDD = 3.5 to 5.5 V Parameter Supply voltage Input high-level voltage Input low-level voltage Input frequency Input amplitude Input voltage range Symbol Conditions Ratings min typ max Unit VDD(1) CPU and PLL circuit operating 4.5 5.5 V VDD(2) CPU operating 4.0 5.5 V VDD(3) Memory retention voltage 1.3 5.5 V VIH(1) Ports E, H, I, L, M, and Q, HCTR, LCTR (when selected for input) 0.7 VDD VDD V VIH(2) Ports F, G, and K, LCTR (in period measurement mode), HOLD 0.8 VDD VDD V VIH(3) SNS VIH(4) Port A 5.0 2.5 VDD V 0.6 VDD VDD V VIL(1) Ports E, H, I, L, M, and Q, HCTR, LCTR (when selected for input) 0 0.3 VDD V VIL(2) Ports A, F, G, and K, LCTR (in period measurement mode) 0 0.2 VDD V V VIL(3) SNS 0 1.3 VIL(4) HOLD 0 0.4 VDD fIN(1) XIN 4.0 4.5 V 5.0 MHz MHz fIN(2) FMIN : VIN(2), VDD(1) 10 150 fIN(3) FMIN : VIN(3), VDD(1) 10 130 MHz fIN(4) AMIN(H) : VIN(3), VDD(1) 2.0 40 MHz fIN(5) AMIN(L) : VIN(3), VDD(1) 0.5 10 MHz fIN(6) HCTR : VIN(3), VDD(1) 0.4 12 MHz fIN(7) LCTR : VIN(3), VDD(1) 100 500 kHz fIN(8) LCTR (in period measurement mode): VIH(2), VIL(2), VDD(1) 1 20 × 103 Hz VIN(1) XIN 0.5 1.5 Vrms VIN(2) FMIN 0.10 1.5 Vrms VIN(3) FMIN, AMIN, HCTR, LCTR 0.07 1.5 Vrms VIN(4) ADI0 to ADI5 0 VDD V No. 5544-4/14 LC72P366 Electrical Characteristics in the Allowable Operating Ranges Parameter Input high-level current Symbol Pull-down resistance Hysteresis Output low-level voltage Output off leakage current Unit max XIN : VI = VDD = 5.0 V 2.0 5.0 15 µA FMIN, AMIN, HCTR, LCTR : VI = VDD = 5.0 V 4.0 10 30 µA IIH(3) Ports A, E, F, G, H, I, K, L, M, and Q, SNS, HOLD, HCTR, LCTR, and with no pull-down resistor on port A, VI = VDD = 5.0 V With input mode selected for ports E, F, G, K, L, M, and Q 3.0 µA IIH(4) Port A: pull-down resistor present IIL(1) XIN:VI = VSS 2.0 5.0 15 µA IIL(2) FMIN, AMIN, HCTR, LCTR : VSS 4.0 10 30 µA IIL(3) Ports A, E, F, G, H, I, K, L, M, and Q, SNS, HOLD, HCTR, LCTR, and with no pull-down resistor on port A, VI = VSS With input mode selected for ports E, F, G, K, L, M, and Q 3.0 µA VIF 50 Port A: pull-down resistor present RPD(1) Port A: pull-down resistor present VDD = 5 V RPD(2) TEST1, TEST2 µA 0.05 VDD 200 100 0.1 VDD 0.2 VDD V VDD – 1.0 V 10 Ports F, G, and K, LCTR (in period measurement mode) V 75 kΩ kΩ VOH(1) Ports B and C: IO = –1 mA VDD – 2.0 VOH(2) Ports D, E, F, G, K, L, M, N, O, P, and Q: IO = –1 mA VDD – 1.0 V VOH(3) EO1, EO2, EO3, SUBPD : IO = –500 µA VDD – 1.0 V VOH(4) XOUT : IO = –200 µA VDD – 1.0 VOL(1) Ports B and C: IO = 50 µA VOL(2) V 1.0 2.0 V Ports D, E, F, G, K, L, M, N, O, P, and Q: IO = 1 mA 1.0 V 1.0 VOL(3) EO1, EO2, EO3, SUBPD : IO = 500 µA VOL(4) XOUT : IO = 200 µA 1.5 VOL(5) Port J: IO = 5 mA 2.0 V IOFF(1) Ports B, C, D, E, F, G, K, L, M, N, O, P, and Q –3.0 +3.0 µA IOFF(2) EO1, EO2, EO3, SUBPD –100 +100 nA IOFF(3) Port J –5.0 +5.0 µA ADI0 to ADI5 : VDD(1) –1/2 +1/2 LSB A/D conversion error Rejected pulse width PREJ Power down detection voltage VDET Current drain typ IIH(2) VH Output high-level voltage Ratings min IIH(1) Input low-level current Input floating voltage Conditions SNS 50 3.0 µs 3.5 4.0 V 12 24 mA IDD(1) VDD(1) : fIN(2) = 130 MHz, Ta = 25˚C IDD(2) VDD(2): halt mode*, Ta = 25˚C (See figure 1.) IDD(3) VDD = 5.5 V, oscillator stopped Ta = 25˚C (See figure 2.) 5 µA IDD(4) VDD = 2.5 V, oscillator stopped Ta = 25°C (See figure 2.) 1 µA 0.45 mA Note: * Executing 20 STEP instructions every millisecond. With the PLL and counter circuits stopped. Test Circuit Diagrams Note: With PB to PG, and PJ to PQ all open. However, with PE to PG, PK to PM, and PQ selected for output. Figure 1 IDD(2) in Halt Mode Note: With PA to PQ all open. Figure 2 IDD(3) and IDD(4) in Backup Mode No. 5544-5/14 LC72P366 Pin Functions Pin No. Symbol 30 PA0 29 PA1 28 PA2 27 PA3 26 PB0 25 PB1 24 PB2 23 PB3 22 PC0 21 PC1 20 PC2 19 PC3 18 PD0 17 PD1 16 PD2 15 PD3 14 PE0 13 PE1/SCK2 12 PE2/SO2 11 PE3/SI2 10 PF0 9 PF1/SCK1 8 PF2/SO1 7 PF3/SI1 6 PG0 5 PG1/SCK0 4 PG2/SO0 3 PG3/SI0 I/O Pull-down resistor included Input O Unbalanced CMOS push-pull Key source signal output-only ports. Since the output transistor circuit is an unbalanced CMOS structure, diodes to prevent shorting due to multiple key presses are not required. In clock stop mode, these pins go to the output high-impedance state. During the power-on reset, these pins go to the output high-impedance state and hold that state until an output instruction is executed. O CMOS push-pull Output-only ports. In clock stop mode, these pins go to the output high-impedance state. During the power-on reset, these pins go to the output high-impedance state and hold that state until an output instruction is executed. CMOS push-pull General-purpose I/O port/serial I/O pin shared-function ports. The F and G port inputs are Schmitt inputs. The E ports is a normal input. The IOS instruction switches these ports between general-purpose I/O ports and serial I/O ports, and between input and output for general-purpose I/O ports. • When used as general-purpose I/O ports these pins: Can be set for input or output in bit units (bit I/O), and are set for use as general-purpose I/O ports by the IOS instruction with PWn = 0. b0 = SI/O 0 0 ...................general-purpose port b1 = SI/O 1 1 ...................SI/O port b2 = SI/O 2 are set for input or output by the IOS instruction in bit units. PE..............PWn = 4 0 ...................Input PF..............PWn = 5 1 ...................Output PG .............PWn = 6 • When used as serial I/O ports these pins: Are set for serial I/O port use by the IOS instruction with PWn = 0, and are accessed by reading and writing the serial I/O data buffer with the INR and OUTR instructions. Note: Pin setup states when used as serial I/O ports: PE0, PF0, PG0 ......General-purpose I/O PE1, PF1, PG1 ......SCK output in internal clock mode SCK input in external clock mode PE2, PF2, PG2......SO output PE3, PF3, PG3......SI input In clock stop mode, input is disabled and these pins go to the high-impedance state. During the power-on reset, these pins become general-purpose input ports. — Connections for a 4.5 MHz crystal oscillator CMOS tristate Main charge pump outputs These pins output a high level when the frequency generated by dividing the local oscillator signal frequency by N is higher than the reference frequency, and a low level when that frequency is lower. These pins go to the high-impedance state when the frequencies match. These pins go to the high-impedance state when the HOLD pin is set low in the hold enable state. In clock stop mode, during the power-on reset and in the PLL stop state, these pins go to the high-impedance state. I I/O 1 XIN I XOUT O EO1 77 EO2 Function Key return signal input-only ports. The threshold voltage is set to a relatively low value. When a key matrix is formed in combination with the PB and PC ports, up to three simultaneous key presses can be detected. The pull-down resistors are set by the IOS instruction with PWn = 2 for all four pins at the same time and cannot be set on an individual pin basis. Input is disabled in clock stop mode. 80 78 I/O type O Continued on next page. No. 5544-6/14 LC72P366 Continued from preceding page. Pin No. Symbol 76 VSS 73 VDD 31 VDD 75 FMIN I/O — I I/O type Function — Power supply connections Input FM VCO (local oscillator) input This pin is selected by the PLL instruction CW1 (b1, b0 are ignored). Capacitor coupling must be used for signal input. Input is disabled when the HOLD pin is set low in the hold enable state. Input is disabled in clock stop mode, during the power-on reset, and in the PLL stop state. AM VCO (local oscillator) input This pin is selected and the band set by the PLL instruction CW1 (b1, b0). 74 AMIN I Input b1 b0 1 0 2 to 40 MHz (SW) Band 1 1 0.5 to 10 MHz (MW, LW) Capacitor coupling must be used for signal input. Input is disabled when the HOLD pin is set low in the hold enable state. Input is disabled in clock stop mode, during the power-on reset, and in the PLL stop state. Sub-charge pump output This pin, in combination with the main charge pump, allows the construction of a highspeed locking circuit. The DZC instruction controls the sub-charge pump. 72 SUBPD O CMOS tristate b3 b2 0 0 High impedance Operation 0 1 Only operates in the unlocked state (450 kHz) 1 0 Only operates in the unlocked state (900 kHz) 1 1 Normal operation This pin goes to the high-impedance state when the HOLD pin is set low in the hold enable state. This pin goes to the high-impedance state in clock stop mode, during the power-on reset, and in the PLL stop state. 71 EO3 O CMOS tristate Second PLL charge pump output This pin outputs a low level when the frequency generated by dividing the local oscillator signal frequency by N is higher than the reference frequency, and a high level when that frequency is lower. This pin goes to the high-impedance state when the frequencies match. (Note that this pin’s output logic is the opposite of that of the EO1 and EO2 pins.) This pin goes to the high-impedance state when the HOLD pin is set low in the hold enable state. This pin goes to the high-impedance state in clock stop mode, during the power-on reset, and in the PLL stop state. Continued on next page. No. 5544-7/14 LC72P366 Continued from preceding page. Pin No. 70 69 68 Symbol HCTR LCTR SNS I/O I I I I/O type Function Input Universal counter/general-purpose input shared-function input port The IOS instruction b3 with PWn = 3 switches the pin function between universal counter input and general-purpose input. • Frequency measurement The universal counter function is selected by an IOS instruction with PWn = 3 and b3 = 0. HCTR frequency measurement mode is set up by a UCS instruction with b3 = 0 and b2 = 0, and counting is started with a UCC instruction after the count time is selected. The CNTEND flag is set when the count completes. To operate this circuit as an AC amplifier in this mode, the input must be capacitor coupled. • General-purpose input pin use The general-purpose input port function is selected by an IOS instruction with PWn = 3 and b3 = 1. An internal register (address: 0EH) input instruction INR (b0) is used to acquire data from this pin. Input is disabled in clock stop mode. (The input pin will be pulled down.) During the power-on reset, the universal counter function is selected. Input Universal counter (frequency and period measurement)/general-purpose input sharedfunction input port The IOS instruction b2 with PWn = 3 switches the pin function between universal counter input and general-purpose input. • Frequency measurement The universal counter function is selected by an IOS instruction with PWn = 3 and b2 = 0. LCTR frequency measurement mode is set up by a UCS instruction with b3 = 0 b2 = 1, and counting is started with a UCC instruction after the count time is selected. The CNTEND flag is set when the count completes. To operate this circuit as an AC amplifier in this mode, the input must be capacitor coupled. • Period measurement With the universal counter function selected, set up period measurement mode with a UCS instruction with b3 = 1 and b2 = 0, and start the count with a UCC instruction after selecting the count time. The CNTEND flag will be set when the count completes. In this mode, the signal must be input with DC coupling to turn off the bias feedback resistor. • General-purpose input pin use The general-purpose input port function is selected by an IOS instruction with PWn = 3, b2 = 1. An internal register (address: 0EH) input instruction INR (b1) is used to acquire data from this pin. Input is disabled in clock stop mode. (The input pin will be pulled down.) During the power-on reset, the universal counter function (in HCTR frequency measurement mode) is selected. Input Voltage sense/general-purpose input pin shared-function port This circuit is designed for a relatively low input threshold voltage. • Voltage sense pin usage This input pin is used to determine whether or not a power failure occurred after recovery from backup (clock stop) mode. An internal sense F/F is used for this determination. The sense F/F is tested with a TUL instruction (b2). • General-purpose input port usage When used as a general-purpose input port, the state is sensed by using a TUL instruction (b3). Since, unlike other input ports, input is not disabled in clock stop mode and during the power-on reset, special care is required with respect to through currents. Continued on next page. No. 5544-8/14 LC72P366 Continued from preceding page. Pin No. 67 Symbol HOLD 66 PH0/ADI0 65 PH1/ADI1 64 PH2/ADI2 63 PH3/ADI3 62 PI0/ADI4 61 PI1/ADI5 60 PJ0 59 PJ1 58 PJ2 57 PJ3 56 PK0/INT0 55 PK1/INT1 54 PK2 53 PK3 52 to 45 PL0 to PL3 PM0 to PM3 I/O I/O type Function Input PLL control and clock stop mode control Setting this pin low in the hold enabled state disables input to the FMIN and AMIN pins and sets the EO pin to the high-impedance state. To enter clock stop mode, set the HOLDEN flag, set this pin low, and execute a CKSTP instruction. To clear clock stop mode, set this pin high. Input General-purpose input port/A/D converter shared-function pins The IOS instruction with PWn = 7 or 8 switches the pin function between general-purpose input ports and A/D converter inputs. • General-purpose input port usage Specify general-purpose input port usage with the IOS instruction with PWn = 7 or 8 in bit units. • A/D converter usage Specify A/D converter usage with the IOS instruction with PWn = 7 or 8 in bit units. Specify the pin to convert with the IOS instruction with PWn = 1. Start a conversion with the UCC instruction (b2). The ADCE flag will be set when the conversion competes. Note: Executing an input instruction for a port specified for ADI usage will always return low since input is disabled. These pins must be set up for general-purpose input port usage before an input instruction is executed. Input is disabled in clock stop mode. During the power-on reset, these pins go to the general-purpose input port function. N-channel open drain General-purpose output ports An external pull-up resistor is required since these pins are open-drain circuits. In clock stop mode, these pins go to the transistor off state (high level output). During the power-on reset, these pins are set up as general-purpose output ports and go to the transistor off state (high level output). I/O CMOS push-pull General-purpose I/O/external interrupt shared-function ports There is no instruction that switches the function of these ports between general-purpose ports and external interrupt ports. These pins function as external interrupt pins at the point where the external interrupt enable flag is set. • General-purpose I/O port usage These pins can be set for input or output in bit units (bit I/O). The IOS instruction is used to specify input or output in bit units. • External interrupt pin usage This function can be used by setting the external interrupt enable flags (INT0EN and INT1EN) in status register 2. The corresponding pin must be set up for input. To enable interrupt operation, the interrupt enable flag (INTEN) in status register 1 also must be set. The IOS instruction with PWn = 3, b1 = INT1, and b0 = INT0 is used to select rising or falling edge detection. In clock stop mode, input is disabled and these pins go to the high impedance state. During the power-on reset, these pins function as general-purpose input ports. I/O CMOS push-pull General-purpose I/O ports The IOS instruction is used to specify input or output. In clock stop mode input is disabled and these pins go to the high impedance state. During the power-on reset, these pins function as general-purpose input ports. I I O Continued on next page. No. 5544-9/14 LC72P366 Continued from preceding page. Pin No. Symbol 44 PN0/BEEP 43 PN1 42 PN2 41 PN3 40 to 33 PO0 to PO3 PP0 to PP3 32 PQ0 79 TEST1 2 TEST2 I/O I/O type Function O CMOS push-pull General-purpose output port/BEEP tone shared-function output pins The BEEP instruction switches between the general-purpose output port and BEEP tone functions. • General-purpose output port usage The BEEP instruction with b3 = 0 sets up the general-purpose output port function. Pins PN1 to PN3 are general-purpose output-only pins. • BEEP output usage The BEEP instruction with b3 = 1 sets up BEEP output. The BEEP instruction bits b0, b1 and b2 sets the frequency. When set up as the BEEP port, executing an output instruction will set the internal latch data but has no influence on the output. These pins go to the output high-impedance state in clock stop mode. These pins go to the output high-impedance state during the power-on reset and hold that state until an output instruction is executed. O CMOS push-pull Output-only ports These pins go to the output high-impedance state in clock stop mode. These pins go to the output high-impedance state during the power-on reset and hold that state until an output instruction is executed. CMOS push-pull General-purpose I/O ports The IOS instruction is used to specify input or output. The OUTR and INR instructions are used for output and input. The bit set, reset and test instruction cannot be used. In clock stop mode input is disabled and these pins go to the high impedance state. During the power-on reset, these pins function as general-purpose input ports. I/O LSI test pins These pins must be either left open or connected to ground. Usage Notes The LC72P366 is provided for use in initial shipments of products designed to use the Sanyo LC72358N, LC72362N, or LC72366. Keep the following points in mind when using this product. • Differences between the LC72P366 and the LC72358N, LC72362N, and LC72366 Parameter Operating temperature CPU operating voltage Power down detection voltage (VDET) LC72P366 LC72358N, 72362N, 72366 –30 to +70˚C –40 to +85˚C Minimum 4.0 V Minimum 3.5 V Typical Typical Maximum 5.5 V Maximum 5.5 V Minimum 3.0 V Minimum 2.7 V Typical 3.5 V Typical 3.0 V Maximum 4.0 V Maximum 3.3 V • ROM ordering procedure when using Sanyo’s for-fee PROM programming service — When ordering one-time programmable versions and mask versions at the same time: The customer must provide the mask ROM version program, the mask ROM version order forms, and the one-time programmable version order forms. — When order just the one-time programmable version: The customer must provide the one-time programmable version program and the one-time programmable version order forms. No. 5544-10/14 LC72P366 • Conditions required for mounting the LC72P366 1. Products programmed by the user: Mount the LC72P366 using the following procedure when using products shipped from Sanyo without the PROM having been programmed. 2. Products programmed by Sanyo: Mount the LC72P366 using the following procedure when using products shipped from Sanyo with the PROM programmed by Sanyo. [Caution] • Due to the nature of the product, it is not possible for Sanyo to fully test one-time programmable PROM microcontrollers (i.e., products with blank PROMs) before shipment to the customer. This means that there will be some amount of yield reduction after programming. Usage Procedures • Programming the on-chip PROM There are two methods for writing the LC72P366 on-chip PROM as follows: — Using a general-purpose PROM programmer A general-purpose PROM programmer can be used if a special-purpose PROM programming adapter (product name: LC72P366 EPROM PROGRAMMER) is used. The write procedure used is the 27512 or 27C512 (with Vpp = 12.5 V) Intel fast write method. Specify 0000H to 7FFFH as the address settings. — Using the RE32N in-circuit emulator: The RE32N in-circuit emulator can be used if a special-purpose PROM programming adapter (product name: LC72P366 RE32N) is used. Use the PGOTP command as the write method. • Special-purpose writing adapters Since there are two special-purpose PROM programming adapters as mentioned above, the correct adapter must be used. General-purpose EPROM programmer adapter In-circuit emulator RE32 adapter : Product name LC72P366 EPROM PROGRAMMER : Catalog no. NDK-DC-018 : Product name LC72P366 RE32N : Catalog no. NDK-DC-020 No. 5544-11/14 LC72P366 Comparison instructions Subtraction instructions Addition instructions Instruction group LC72P366 Instruction Overview Abbreviations : ADDR : Program memory address b : Borrow C : Carry DH : Data memory address high (Row address) [2 bits] DL : Data memory address low (Column address) [4 bits] I : Immediate data [4 bits] M : Data Memory address N : Bit position [4 bits] Pn : Port number [4 bits] PWn : Port control word number [4 bits] r : General register (on of location 00 to 0FH in the current bank) Rn : Register number [4 bits] ( ) : Contents of register or memory ( )n : Contents of bit N of register or memory Operand Mnemonic Machine code Function Operation 1st 2nd D15 14 13 12 11 10 9 AD r M Add M to r r ← (r) + (M) 0 1 0 0 0 0 DH 8 7 6 DL 5 4 3 2 r 1 ADS r M Add M to r, then skip if carry r ← (r) + (M) skip if carry 0 1 0 0 0 1 DH DL r AC r M Add M to r with carry r ← (r) + (M) + C 0 1 0 0 1 0 DH DL r ACS r M Add M to r with carry, then skip if carry r ← (r) + (M) + C skip if carry 0 1 0 0 1 1 DH DL r AI M I Add I to M M ← (M) + I 0 1 0 1 0 0 DH DL I AIS M I Add I to M, then skip if carry M ← (M) + I skip if carry 0 1 0 1 0 1 DH DL I AIC M I Add I to M with carry M ← (M) + I + C 0 1 0 1 1 0 DH DL I AICS M I Add I to M with carry, then skip if carry M ← (M) + I+ C skip if carry 0 1 0 1 1 1 DH DL I SU r M Subtract M from r r ← (r) – (M) 0 1 1 0 0 0 DH DL r SUS r M Subtract M from r, then skip if borrow r ← (r) – (M) skip if borrow 0 1 1 0 0 1 DH DL r SB r M Subtract M from r with borrow r ← (r) – (M) – b 0 1 1 0 1 0 DH DL r SBS r M Subtract M from r with borrow, then skip if borrow r ← (r) – (M) – b skip if borrow 0 1 1 0 1 1 DH DL I SI M I Subtract I from M M ← (M) – I 0 1 1 1 0 0 DH DL I SIS M I Subtract I from M, then skip if borrow M ← (M) – I skip if borrow 0 1 1 1 0 1 DH DL I SIB M I Subtract I from M with borrow M ← (M) – I – b 0 1 1 1 1 0 DH DL I SIBS M I Subtract I from M with borrow, then skip if borrow M ← (M) – I – b skip if borrow 0 1 1 1 1 1 DH DL I SEQ r M Skip if r equal to M (r) – (M) skip if zero 0 0 0 1 0 0 DH DL r SEQI M I Skip if M equal to I (M) – I skip if zero 0 0 0 1 0 1 DH DL I SNEI M I Skip if M not equal to I (M) – I skip if not zero 0 0 0 0 0 1 DH DL I SGE r M Skip if r is greater than or equal to M (r) – (M) skip if not borrow 0 0 0 1 1 0 DH DL r SGEI M I Skip if M is greater than (M) – I or equal to I skip if not borrow 0 0 0 1 1 1 DH DL I SLEI M I Skip if M is less than I 0 0 0 0 1 1 DH DL I (M) – I skip if zero D0 Continued on next page. No. 5544-12/14 LC72P366 Operand Mnemonic 1st 2n AND r M Machine code Function AND M with r Operation r ← (r) AND (M) D15 14 13 12 11 10 0 0 1 0 0 9 0 8 7 6 5 DH DL 4 3 2 1 ANDI M I AND I with M M ← (M) AND I 0 0 1 0 0 1 DH DL I r M OR M with r r ← (r) OR (M) 0 0 1 0 1 0 DH DL r ORI M I OR I with M M ← (M) OR I 0 0 1 0 1 1 DH DL r EXL r M Exclusive OR I with r r ← (r) XOR I 0 0 1 1 0 1 DH DL r EXLI M I Exclusive OR I with M M ← (M) XOR I 0 0 1 1 0 1 DH DL 0 0 0 0 0 0 SHR r Shift r right with carry carry (r) 0 0 1 D0 r OR ▲ Logical instructions Instruction group Continued from preceding page. I 1 1 0 r Internal register F/F test transfer instructions instructions Status register instructions Jump and subroutine instructions Bit test instructions Transfer instructions ▲ LD r M Load M to r r ← (M) 1 1 0 1 0 0 DH DL r ST M r Store r to M M ← (r) 1 1 0 1 0 1 DH DL r MVRD r M Move M to destinsation M referring to r in the same row [DH, rn] ← (M) 1 1 0 1 1 0 DH DL r MVRS M r Move M to destinsation M referring to r in the same row M ← [DH, rn] 1 1 0 1 1 1 DH DL r MVSR M1 M2 1 1 1 0 0 0 DH DL1 DL2 MVI M I Move I to M M←I 1 1 1 0 0 1 DH DL I TMT M N Test M bits, then skip if all bits specified are true if M (N) = all “1”, then skip 1 1 1 1 0 0 DH DL N TMF M N Test M bits, then skip if all bits specified are false if M (N) = all “0”, then skip 1 1 1 1 0 1 DH DL N Move source M referring [DH, DL1] ← [DH, DL2] to r to M in the same row JMP ADDR Jump to the address PC ← ADDR 1 0 CAL ADDR Call subroutine Stack ← (PC) + 1 1 1 0 0 RT Return from subroutine PC ← Stack 0 0 0 0 0 0 0 0 1 0 0 0 RTS Return from subroutine and skip PC ← Stack + 1 0 0 0 0 0 0 0 0 1 0 1 0 RTB Return from subroutine with bank data PC ← Stack BANK ← Stack 1 1 1 1 1 1 1 1 1 1 0 0 RTBS Return from subroutine PC ← Stack + 1 with bank data and skip BANK ← Stack 1 1 1 1 1 1 1 1 1 1 0 1 RTI Return from interrupt PC ← Stack BANK ← Stack CARRY ← Stack 0 0 0 0 0 0 0 0 1 0 0 1 ADDR (14 bits) ADDR (12 bits) SS I N Set status register (Status reg I) N ← 1 1 1 1 1 1 1 1 1 0 0 0 I RS I N Reset status register (Status reg I) N ← 0 1 1 1 1 1 1 1 1 0 0 1 I TST I N Test status register true if (Status reg I) N = all “1”, then skip 1 1 1 1 1 1 1 1 0 1 I N TSF I N Test status register false if (Status reg I) N = “0”, then skip 1 1 1 1 1 1 1 1 1 0 I N TUL N Test unlock F/F then skip if it has not been set if Unlock FF (N) = all “0”, then skip 0 0 0 0 0 0 0 0 1 1 PLL M r Load M to PLL register PLL reg ← PLL data 1 1 1 1 1 0 DH DL r INR M Rn Input register/port data to M M ← (Rn reg) 0 0 1 1 1 0 DH DL Rn OUTR M Rn Output contents of M to register/port Rn reg ← (M) 0 0 1 1 1 1 DH DL Rn 0 1 N N N Continued on next page. No. 5544-13/14 LC72P366 Instruction group Continued from preceding page. Operand Mnemonic Other instructions Bank switching instructions I/O instructions Hardware control instructions SIO 1st 2n I1 I2 Machine code Function Serial I/O control Operation SIO reg ← I1,I2 D15 14 13 12 11 10 0 0 0 0 0 0 9 8 0 1 7 6 5 4 I1 3 2 1 UCS I Set I to UCCW1 UCCW1 ← I 0 0 0 0 0 0 0 0 0 0 0 1 I UCC I Set I to UCCW2 UCCW2 ← I 0 0 0 0 0 0 0 0 0 0 1 0 I BEEP I Beep control BEEP reg ← I 0 0 0 0 0 0 0 0 0 1 1 0 I DZC I Dead zone control DZC reg ← I 0 0 0 0 0 0 0 0 1 0 1 1 I 1 1 0 0 TMS N Set timer register Timer reg ← I 0 0 0 0 0 0 0 0 IOS PWn N Set port control word IOS reg PWn ← N 1 1 1 1 1 1 1 0 IN M Pn Input port data to M M ← (Pn) 1 1 1 0 1 0 OUT M Pn Output contents of M to port Pn ← M 1 1 1 0 1 1 SPB Pn N Set port bits (Pn) N ← 1 0 0 0 0 0 0 1 RPB Pn N Reset port bits (Pn) N ← 0 0 0 0 0 0 0 1 TPT Pn N Test port bit, then skip if all bits specified are true if (Pn) N = all “1”, then skip 1 1 1 1 1 1 TPF Pn N Test port bits, then skip if all bits specified are false if (Pn) N = all “0”, then skip 1 1 1 1 1 D0 I2 N PWn N DH DL Pn DH DL Pn 0 Pn N 1 Pn N 0 0 Pn N 1 0 1 Pn N BANK I Select Bank BANK ← I 0 0 0 0 0 0 0 0 0 1 1 1 I HALT I Halt mode control HALT reg ← I, then CPU click stop 0 0 0 0 0 0 0 0 0 1 0 0 I CKSTP Clock stop stop X’tal OSC if HOLD = 0 0 0 0 0 0 0 0 0 0 1 0 1 NOP No operation No operation 0 0 0 0 0 0 0 0 0 0 0 0 ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 1996. Specifications and information herein are subject to change without notice. No. 5544-14/14