SANYO LC72F3781

Ordering number : EN*A0459A
LC72F3781
CMOS IC
Electronic tuning radio for car audio
ETR Controller
Overview
The LC72F3781 is a ETR controller with an on-chip one-time PROM for use with the LC723781N, 2N, 3N, 4 and 5
mask versions. Since it has the equivalent electrical performance, pin layout and package as these mask versions, it is
ideally suited for checking program operations, starting the initial shipment of finished products and reducing the
switchover time frame when specifications are changed.
The PROM size is 128 Kbytes (64K × 16 bits).
Functions
• ROM
• RAM
• Stack
• Serial I/O
• External interrupts
• Internal interrupts
: Up to 64K steps (65,535×16-bits)
The subroutine area holds 4K steps (4,096×16-bits)
: Up to 16K×4-bits (In banks 00 through FF)
: 32levels
: Three channels. These circuits can support both 2-wire and 3-wire 8-bit communication
techniques, and can be switched between MSB first and LSB first operation.
One of six internally generated serial transfer clock rates can be selected: 12.5kHz,
37.5kHz, 187.5kHz, 281.25kHz, 375kHz, and 450kHz
: Seven interrupt inputs (pins INT0 through INT5, and the HOLD pin)
These interrupts can be set to switch between rising and falling edges, although the HOLD
pin only supports falling edge detection.
: Seven interrupts ; four internal timer interrupts, and three serial I/O interrupts.
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
92006HKIM No.0459-1/17
LC72F3781
• Interrupt nesting levels
: 14 levels
Interrupts are prioritized in hardware as follows :
HOLD pin>INT0 pin>INT1 pin>INT2 pin>INT3 pin>INT4 pin>INT5 pin>
S-I/O0>S-I/O1>S-I/O2>Internal TMR0>Internal TMR1>Internal TMR2>
Internal TMR3
• A/D Converter
: 8-bit resolution and 8 inputs
• General-purpose ports
: Input ports : 13
Output ports : 4
I/O ports : 62 (These pins can be switched between input and output in 1-bit units.)
• PLL block
: Includes a sub-charge pump for high-speed locking.
Supports dead zone control.
Built-in unlock detection circuit
Twelve reference frequencies : 1kHz, 3kHz, 3.125kHz, 5kHz, 6.25kHz, 9kHz,
10kHz, 12.5kHz, 25kHz, 30kHz, 50kHz, and 100kHz
• Universal counter
: This 20-bit counter can be used for either frequency or period measurement and
supports four measurement (calculation) periods : 1ms, 4ms, 8ms, and 32ms
• Timers
: Two fixed timers and two programmable timers (8-bit counters)
TMR0
: Supports four periods : 10µs, 100µs, 1ms, and 5ms
TMR1
: Supports four periods : 10µs, 100µs, 1ms, and 10ms
TMR2 and TMR3 : Programmable 8-bit counters.
Input clocks with 10µs, 100µs, and 1ms
One 125-ms timer flip-flop provided
• Beep circuit
: Provides 12 fixed beep tones :
500Hz, 1kHz, 2kHz, 2.08kHz, 2.2kHz, 2.5kHz, 3kHz, 3.125kHz, 3.33kHz,
3.75kHz, 4.17kHz, and 7.03kHz
Programmable 8-bit beep tone generator.
Reference clocks with frequencies of 50kHz, 15kHz, and 5kHz.
• Reset
: Built-in voltage detection reset circuit
External reset pin
• Cycle time
: 1.33µs/833ns (All instructions are one word), X’tal : 4.5MHz/7.2MHz
Supports software switching (Initial cycle time is 1.33µs)
• Halt mode
: The microcontroller operating clock is stopped in Halt mode.
There are four conditions that can clear Halt mode : Interrupt requests,
timer flip-flop overflows, port PA inputs, and HOLD pin inputs.
• Operating supply voltage : 4.5 to 5.5V (Microcontroller block only : 3.5 to 5.5V)
• Package
: QIP100E
• Development tools
: Emulator
: RE128V
Evaluation chip
: LC72EV3780
Evaluation board
: EB-72EV3780
No.0459-2/17
LC72F3781
Specifications
Absolute Maximum Ratings at Ta = 25°C VSS = 0V
Parameter
Symbol
Conditions
Maximum supply voltage
VDD max
Input voltage
VIN1
PC-PORT
VIN2
All input pins other than VIN1
Output voltage
Output current
Ratings
Unit
-0.3 to +6.5
VOUT1
PJ-PORT
VOUT2
PC-PORT
VOUT3
All input pins other than VOUT1 and VOUT2
IOUT1
PC, PJ-PORT
IOUT2
PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PP PQ,
V
-0.3 to +8
V
-0.3 to VDD+0.3
V
-0.3 to +14
V
-0.3 to +8
V
-0.3 to VDD+0.3
V
PR, PS, PT-PORT, EO1, EO2, SUBPD
Ta = -40 to +85 °C
0 to +5
mA
0 to +3
mA
400
mW
Allowable power dissipation
Pd max
Operating temperature
Topr
-40 to +85
°C
Storage temperature
Tstg
-40 to +125
°C
Allowable Operating Range at Ta = -40 to +85°C, VDD = 3.5 to 5.5V
Parameter
Symbol
Ratings
Pins
min
Supply voltage
Input high-level
typ
uit
mx
VDD1
CPU and PLL operation
VDD2
CPU operation
3.5
5.5
VDD3
Memory retention
1.1
5.5
VIH1
PB, PC, PH, PI, PL, PM, PN, PP, PO, PQ, PR, PS,
0.7VDD
VDD
V
0.8VDD
VDD
V
2.5
VDD
V
0.6VDD
VDD
V
0
0.3VDD
V
0
0.2VDD
V
voltage
PT-PORT, HCTR, LCTR, INEO, SUBPD
4.5
5.0
5.5
V
(with the I/O ports set to input mode)
VIH2
PD, PE, PF, PG, PK-PORT,
LCTR (in period measurement mode), HOLD, RESET
Input low-level voltage
VIH3
SNS
VIH4
PA-PORT
VIL1
PB, PC, PH, PI, PL, PM, PN, PP, PO, PQ, PR, PS,
PT-PORT, HCTR, LCTR, INEO, SUBPD
(with the I/O ports set to input mode)
VIL2
PA, PD, PE, PF, PG, PK-PORT,
LCTR (in period measurement mode), RESET
Input frequency
Input amplitude
Input voltage range
VIL3
SNS
0
1.1
V
VIL4
HOLD
0
0.4VDD
V
FIN1
XIN
4.0
8.0
MHz
FIN2
FMIN : VIN2, VDD1
10
150
MHz
FIN3
FMIN : VIN3, VDD1
10
130
MHz
FIN4
AMIN(H) : VIN3, VDD1
2.0
40
MHz
FIN5
AMIN(L) : VIN3, VDD1
0.5
10
MHz
FIN6
HCTR : VIN3, VDD1
0.4
12
MHz
FIN7
LCTR : VIN3, VDD1
100
500
kHz
1
3
FIN8
LCTR (in period measurement) : VIH2, VIL2, VDD1
VIN1
XIN
4.5
20×10
Hz
0.5
1.5
Vrms
1.5
Vrms
Vrms
VIN2
FMIN
0.07
VIN3
FMIN, AMIN, HCTR, LCTR
0.04
1.5
VIN6
ADI0 to ADI7
0
VDD
V
No.0459-3/17
LC72F3781
Electrical Characteristics in the allowable operating ranges
Parameter
Symbol
Ratings
Pins
min
Input high-level current
unit
typ
max
IIH1
XIN : VI = VDD = 5.0V
2.0
5.0
15
µA
IIH2
FMIN, AMIN, HCTR, LCTR : VI = VDD = 5.0V
4.0
10
30
µA
IIH3
PA, PB, PC, PD, PE, PF, PG, PH, PI, PK, PL, PM, PN, PO,
PP, PQ, PR, PS, PT-PORT, SNS, HOLD, RESET, HCTR,
3
µA
LCTR, INEO, SUBPD : VI = VDD = 5.0V
(with the ports PB, PC, PD, PE, PF, PG, PK, PL, PM, PN,
PP, PO, PQ, PR, PS, and PT-PORT set to input mode)
Input low-level current
IIL1
XIN : VI = VDD = VSS
2.0
5.0
15
µA
IIL2
FMIN, AMIN, HCTR, LCTR : VI = VDD = VSS
4.0
10
30
µA
3
µA
IIL3
PA, PB, PC, PD, PE, PF, PG, PH, PI, PK, PL, PM, PN, PO,
PP, PQ, PR, PS, PT-PORT, SNS, HOLD, RESET, HCTR,
LCTR, INEO, SUBPD : VI = VSS
(with the ports PB, PC, PD, PE, PF, PG, PK, PL, PM, PN,
PP, PO, PQ, PR, PS, and PT-PORT set to input mode)
Hysteresis
VH
PD, PE, PF, PG, PK-PORT, RESET,
0.1VDD
LCTR (in period measurement)
Output high-level voltage
VOH1
PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PP, PQ, PR,
PS, PT-PORT : IO = -1mA
Output low-level voltage
0.2VDD
VDD-1.0
V
VOH2
EO1, EO2, SUBPD : IO = -500µA
VDD-1.0
V
VOH3
XOUT : IO = -200µA
VDD-1.0
V
VOL1
PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PP PQ, PR,
1.0
PS, PT-PORT : IO = -1mA
Output off leakage
V
VOL2
EO1, EO2, SUBPD : IO = -500µA
1.0
V
VOL3
XOUT : IO = -200µA
1.5
V
VOL4
PC, PJ-PORT : IO = -5mA
2.0
V
IOFF1
PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PP, PQ, PR,
-3
+3
µA
-100
+100
nA
-5
+5
µA
-1.5
+1.5
current
PS, PT-PORT
IOFF2
EO1, EO2, SUBPD
IOFF3
PC, PJ-PORT
A/D conversion error
ADI0 to ADI7
Rejected pulse width
PREJ1
Power down detection
VDET
SNS
2.7
voltage
Power supply current
V
3.0
LSB
50
µs
3.3
V
IDD1
VDD1 : FIN2 = 130MHz Ta = 25°C
5
10
mA
IDD2
VDD1 : FIN2 = 130MHz Ta = 25°C
5.5
11
mA
IDD3
VDD2 : Halt mode Ta = 25°C, X’tal : 4.5 MHz
IDD4
VDD2 : Halt mode Ta = 25°C, X’tal : 7.2MHz
IDD5
Backup mode (OSC stopped)
VDD = 5.5V, Ta = 25°C
IDD6
*1 (Fig. 1)
*2 (Fig. 2)
Backup mode (OSC stopped)
VDD = 2.5V, Ta = 25°C
*2 (Fig. 2)
0.45
mA
0.55
mA
5
µA
1
µA
*1 : Twenty instruction steps are executed every millisecond. The PLL, universal counter, and other functions are stopped.
No.0459-4/17
LC72F3781
Test Circuits
20pF
20pF
4.5MHz
A
XOUT VDD RES
XIN
LCTR
VSS
FMIN
AMIN
HCTR
TEST 1, 2
SNS
HOLD
PA, PH, PI
Ports PB through PG, and PJ through PT
are all left open. However, ports PB through PG,
PK through PT, SUBPD are left open in output mode.
ILC05525
Figure 1. IDD2 in Halt Mode
20pF
4.5MHz
A
20pF
XOUT VDD RES
XIN
LCTR
VSS
FMIN
AMIN
HCTR
TEST 1, 2
SNS
HOLD
Ports PA through PT are all left open.
ILC05526
Figure 2. IDD3 and IDD4 in Backup Mode
Package Dimensions
unit:mm (typ)
3151A
23.2
0.8
20.0
51
50
100
31
14.0
81
1
17.2
80
30
0.65
0.3
0.15
0.1
3.0max
(2.7)
(0.58)
SANYO : QIP100E(14X20)
No.0459-5/17
LC72F3781
XIN
1
INEO
HCTR(IN)
LCTR(IN)
SNS
92
91
90
89
88
TEST2
2
VSSADC
SUBPD(IN)
93
PH3/ADI3
VDDPLL
94
PH2/ADI2
AMIN
95
PH1/ADI1
FMIN
96
PH0/ADI0
VSSPLL
97
RESET
EO2
98
87 86
85
84
83
82
81
HOLD
EO1
100 99
XOUT
TEST1
Pin Assignment
I
80
PI0/ADI4
79
PI1/ADI5
78
PI2/ADI6
77
PI3/ADI7
76
PJ0
75
PJ1
I
VREG
3
A/D-C
INPUT-port
VSSCPU
4
SI0/PG3
5
SO0/PG2
6
High-voltage output port
(open drain)
O
I/O
SCK0/PG1
7
74
PJ2
PG0
8
73
PJ3
SI1/PF3
9
72
PK0/INT0
71
PK1/INT1
70
PK2/INT2
69
PK3/INT3
68
PL0
67
PL1
66
PL2
65
PL3
64
PM0
63
PM1
I/O-port
SO1/PF2
(schmitt)
10
I/O
SCK1/PF1
11
PF0
12
SI2/PE3
13
SO2/PE2
14
SCK2/PE1
15
PE0
16
PD3
17
PD2
18
I/O
I/O-port
(schmitt)
I/O
I/O
LC72F3781
(QIP100E)
I/O
I/O
PD1/INT5
19
62
PM2
PD0/INT4
20
61
PM3
60
PN0/BEEP
59
PN1
58
PN2
57
PN3
56
PO0
PC3
21
PC2
22
Middle-voltage I/O-port
I/O
I/O
PC1
23
PC0
24
PB3
25
I/O-port
(output : open drain)
I/O-port
PB2
26
55
PO1
PB1
27
54
PO2
PB0
28
53
PO3
PA3
29
52
PP0
51
PP1
I/O
I
I/O
I/O
I/O
I/O
I/O
31
32
33
34
35
36
37
38
39
40
41
42
43
44 45
46
47
48
49
50
PA0
PT1
PT0
PS3
PS2
PS1
PS0
VDDPORT
VSSPORT
PR3
PR2
PR1
PQ3
PQ2
PQ1
PQ0
PP3
PP2
30
PA1
PA2
I/O
PR0
INPUT-port
Topview
ILC05527
No.0459-6/17
LC72F3781
Block Diagram
XIN
DIVIDER
SELECTOR
REFERENCE DIVIDER
PHASE
DETECTOR
EO1
EO2
SYSTEM CLOCK
GENERATOR
XOUT
FMIN
1/16, 1/17
SUB
C.P.
UNLOCK
F/F
PROGRAMMBLE DIVIDER
SUBPD
AMIN
SNS
SNS
SNSF/F
DATA
LATCH
PLL DATA LATCH
VDD
VSS
BUS
DRIVE.
V-DET
TIMER
PROG×2
FIX×2
HCTR
1/2
UNIVERSAL
COUNTER
(20bits)
INEO
DATA
LATCH
PT1
PT0
BUS
DRIVE.
PS3
PS2
PS1
PS0
DATA
LATCH
LCTR
BUS
DRIVE.
RESET
HOLD
TEST1
TEST2
PA0
PA1
PA2
PA3
PB0
PB1
PB2
PB3
PC0
PC1
PC2
PC3
INT4/PD0
INT5/PD1
PD2
PD3
DTR/ADR
ADDRESS
DATA
LATCH
RAM
16K×4bit
DECODER
BUS
DRIVE.
BANK
DATA
LATCH
BUS
DRIVE.
BUS
CONTROL
BUS
DRIVE.
PP3
PP2
PP1
PP0
DATA
LATCH
BUS
DRIVE.
ROM
64K×16bit
BUS
DRIVE.
INSTRUCTION
DECODER
DATA
LATCH
BUS
DRIVE.
PQ3
PQ2
PQ1
PQ0
BUS
DRIVE.
DATA
LATCH
DATA
LATCH
PR3
PR2
PR1
PR0
PO3
PO2
PO1
PO0
DATA
LATCH
BUS
DRIVE.
ADDRESS
DECODER
SKIP
DATA
LATCH
INTERRUPT
PE0
SCK2/PE1
SO2/PE2
SI2/PE3
PF0
SCK1/PF1
SO1/PF2
SI1/PF3
DATA
LATCH
BUS
DRIVE.
PROGRAM
COUNTER
BUS
DRIVE.
DATA
LATCH
PF
BEEP GEN
(PRG/FIX)
STACK 32×27bits
(PC, BANK, CF, PF)
BUS
DRIVE.
LATCH
A
MPX
PN3
PN2
PN1
PN0/BEEP
JUDGE
DATA
LATCH
BUS
DRIVE.
SIO×3
PM3
PM2
PM1
PM0
ALU
PG0
SCK0/PG1
SO0/PG2
SI0/PG3
ADI0/PH0
ADI1/PH1
ADI2/PH2
ADI3/PH3
DATA
LATCH
STATUS
READ
REGISTER
BUS
DRIVE.
BUS
DRIVE.
DATA
LATCH
BUS
DRIVE.
MPX(8ch)
ADI4/PI0
ADI5/PI1
ADI6/PI2
ADI7/PI3
DATA
LATCH
LATCH
B
BUS
DRIVE.
A/D-C
(8bits)
INTERRUPT
CONTROL
STATUS
WRITE
REGISTER
BUS
PK3/INT3
PK2/INT2
PK1/INT1
PK0/INT0
INTERRUPT
DATA
LATCH
BUS
DRIVE.
PL3
PL2
PL1
PL0
PJ3
PJ2
PJ1
PJ0
ILC05528
No.0459-7/17
LC72F3781
Pin Description
Pin name
Pin No.
I/O
PA0
32
I
Pin explanation
PA1
31
These ports are designed with a low threshold voltage.
PA2
30
Input is disabled in Backup mode.
PA3
29
Dedicated input ports.
Equivalent circuit
BACK UP
ILC05529
I/O
General-purpose I/O ports.
PB0
28
PB1
27
The mode (input or output) is set using the IOS2 instruction.
PB2
26
Input is disabled and the pins go to the high-impedance state in
PB3
25
Backup mode.
BACK UP
These ports are set up as general-purpose input ports after a power
on reset.
ILC05530
PC0
24
PC1
23
I/O
General-purpose I/O ports (middle-voltage input and output).
The mode (input or output) is set using the IOS2 instruction.
PC2
22
External pull-up resistors are required since the output circuits are
PC3
21
open drain.
BACK UP
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
ILC05531
on reset.
PD0/INT4
20
PD1/INT5
19
I/O
General-purpose I/O and external interrupt shared function ports.
The input formats are Schmitt inputs.
PD2
18
The external interrupt function is enabled when the external interrupt
PD3
17
enable flag is set.
• When used as general-purpose I/O ports :
BACK UP
The mode (input or output) is set in 1-bit units using the IOS2
instruction.
• When used as external interrupt pins :
The external interrupt functions are enabled by setting the
corresponding external interrupt enable flag (INT4EN or INT5EN).
In this case, the pins must be set to input mode in advance.
ILC05532
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
Continued on next page.
No.0459-8/17
LC72F3781
Continued from preceding page.
Pin name
Pin No.
I/O
PE0
16
I/O
Pin explanation
PE1/SCK2
15
The input formats are Schmitt inputs. The PE1/SCK2 and PE2/SO2
PE2/SO2
14
pins can be switched to function as open drain outputs.
PE3/SI2
13
The IOS1 instruction is used to switch between the general-purpose
Equivalent circuit
General-purpose I/O ports with shared functions as serial I/O ports.
PF0
12
I/O port and serial I/O port functions.
PF1/SCK1
11
• When used as general-purpose I/O ports :
PF2/SO1
10
The pins are set to the general-purpose I/O port function using the
PF3/SI1
9
IOS1 instruction.
PG0
8
The mode (input or output) is set in 1-bit units using the IOS1
PG1/SCK0
7
PG2/SO0
6
PG3/SI0
5
BACK UP
ILC05532
instruction
• When used serial I/O ports :
The pins are set to the serial I/O port function using the IOS1
instruction.
[Pin states when set to the serial I/O port function]
PE0, PF0, PG0 … General-purpose I/O
BACK UP
PE1, PF1, PG1 … SCK input or output
PE2, PF2, PG2 … SO output
Open drain Control
PE3, PF3, PG3 … SI input
The PE1/SCK2 and PE2/SO2 pins can be switched to function as
open drain outputs with the IOS2 instruction. When using this circuit
type, the external pull-up resistors must be connected to the same
power supply as that used by the IC.
PE1/PE2-Port
Input is disabled and the pins go to the high-impedance state in
ILC05533
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
XIN
1
I
XOUT
100
O
Connections for 4.5MHz/7.2MHz crystal oscillator element
XIN
XOUT
ILC05534
EO1
98
EO2
97
O
Main charge pump outputs.
These pins output a high level when the frequency of the local
oscillator divided by n is higher than that of the reference frequency,
and they output a low level when that frequency is lower.
They go to the high-impedance state when the frequencies match.
These pins go to the high-impedance state in Backup mode, after a
power on reset, and in the PLL stopped state.
VDDPORT
VDDPLL
39
-
ILC05535
Power supply connections.
93
The VDDPORT and VSSPORT pins are mainly supply power for the
VSSCPU
VSSPORT
VSSADC
4
peripheral I/O blocks.
40
The VDDPLL and VSSPLL pins are mainly for the PLL circuits and
81
the regulator.
VSSPLL
96
The VSSCPU pin is mainly used by the CPU block.
The VSSADC pin is mainly used by the ADC block.
Since all the VDD and VSS pins are independent, all must be
connected to the same power supply.
VREG
3
O
Internal low voltage output.
Connect a bypass capacitor to this pin.
Continued on next page.
No.0459-9/17
LC72F3781
Continued from preceding page.
Pin name
Pin No.
I/O
FMIN
95
I
Pin explanation
Equivalent circuit
FM VCO (local oscillator) input.
This pin is selected with CW1 in the PLL instruction.
The signal input to this pin must be capacitor coupled.
Input is disabled in Backup mode, after a power on reset, and in the
PLL stopped state.
AMIN
94
I
AM VCO (local oscillator) input.
This pin is selected and the band set with CW1 (b1, b0) in the PLL
instruction.
b1
b0
Band
1
0
2 to 40MHz (SW, AM upconversion)
1
1
0.5 to 10MHz (MW, LW)
PLL Stop instruction
ILC05536
The signal input to this pin must be capacitor coupled.
Input is disabled in Backup mode, after a power on reset, and in the
PLL stopped state.
SUBPD
92
I/O
Sub-charge pump output and general-purpose input shared function
port.
The IOS2 instruction is used for switching between the sub-charge
pump output and general-purpose input functions.
• When used as the sub-charge pump output :
The sub-charge pump output function is set up with the IOS2
instruction.
A high-speed locking circuit can be formed by using this pin in
BACK UP
conjunction with the main charge pump.
The sub-charge pump is controlled using the DZC instruction.
b3
b2
0
0
0
1
1
0
1
1
Operation
High impedance
Only operates when the PLL is unlocked
(450kHz)
Only operates when the PLL is unlocked
ILC05537
(900kHz)
Normal operation
• When used as a general-purpose input :
The general-purpose input function is set up with the IOS2
instruction.
Data is read from the port using the INR instruction.
This pin goes to the high-impedance state in Backup mode, after a
power on reset, and in the PLL stopped state.
INEO
91
I
Dedicated input port.
Data is read from the port using the INR instruction
BACK UP
Input is disabled in Backup mode.
ILC05538
Continued on next page.
No.0459-10/17
LC72F3781
Continued from preceding page.
Pin name
Pin No.
I/O
Pin explanation
HCTR
90
I
Universal counter and general-purpose input shared function input port.
Equivalent circuit
The IOS1 instruction is used for switching between the universal
counter and general- purpose input functions.
• When used for frequency measurement :
The universal counter function is set up with the IOS1 instruction.
The counter is controlled using UCS and UCC instructions.
Since this pin functions as an AC amplifier in this mode, the input
signal must be input with capacitor coupling.
• When used as a general-purpose input pin :
The general-purpose input function is set up with the IOS1
instruction.
Data is read from the port using the INR (b0) instruction.
Input is disabled in Backup mode. (The input pin will be pulled down.)
The universal counter function is selected after a power on reset.
LCTR
89
I
Universal counter (frequency or period measurement) and generalpurpose input shared function input port.
The IOS1 instruction is used for switching between the universal
counter and general-purpose input functions.
PLL Stop instruction
ILC05536
• When used for frequency measurement :
The universal counter function is set up with the IOS1 instruction.
Set up LCTR frequency measurement mode with the UCS
instruction, and control operation with the UCC instruction.
Since this pin functions as an AC amplifier in this mode, the input
signal must be input with capacitor coupling.
• When used for period measurement :
The universal counter function is set up with the IOS1 instruction.
Set up LCTR frequency measurement mode with the UCS
instruction, and control operation with the UCC instruction.
Since the bias feedback resistor is disconnected in this mode, the
input signal must be input with DC coupling.
• When used as a general-purpose input pin :
The general-purpose input port function is set up with the IOS1
instruction.
Data is read from the port using the INR (b1) instruction.
Input is disabled in Backup mode. (The input pin will be pulled down.)
The universal counter function (HCTR frequency measurement mode)
is selected after a power on reset.
SNS
88
I
Voltage sense and general-purpose input shared function port.
This input circuit is designed with a low input threshold voltage.
• When used as a voltage sense input :
The pin is used to test for power failures on the return from Backup
mode.
Application can test this condition using the internal SNS flip-flop.
The SNS flip-flop can be tested with the TST instruction.
(This usage requires external components, capacitors and resistors.
For the sample application circuit, see the user’s manual.)
ILC05539
• When used as a general-purpose input port :
When used as a general-purpose input port the pin state can be
tested with the TST instruction.
Unlike the other input ports, input to this pin is not disabled in Backup
mode and after a power on reset. As a result, through currents must
be taken into account when designing applications that use this pin as
a general-purpose input.
HOLD
87
I
Power supply monitor (with interrupt function)
This is designed with a high input threshold voltage.
This pin is normally connected to the ACC line and used for power off
detection.
When a power off state is detected, the HOLDON flag and the hold
interrupt request flag will be set.
ILC05539
To enter Backup mode, execute a CKSTP instruction when the HOLD
pin is low. Set this pin high to clear Backup mode.
Continued on next page.
No.0459-11/17
LC72F3781
Continued from preceding page.
Pin name
Pin No.
I/O
RESET
86
I
Pin explanation
Equivalent circuit
System reset pin.
When the CPU is operating or in Halt mode, the system is reset when
this pin is held low for at least one machine cycle. Execution starts
with the PC pointing to location 0. At this time the SNS flip-flop is set.
ILC05540
A low level must be applied for at least 50ms when power is first
applied.
PH0/ADI0
85
PH1/ADI1
84
The IOS1 instruction is used to switch between the general-purpose
PH2/ADI2
83
input and the A/D converter input functions.
PH3/ADI3
82
• When used as general-purpose input ports :
PI0/ADI4
81
PI1/ADI5
80
PI2/ADI6
79
PI3/ADI7
78
I
General-purpose input and A/D converter input shared function ports.
The general-purpose input port function is set up with the IOS1
instruction. (In bit units)
• When used as A/D converter input pins :
BACK UP
The A/D converter input port function is set up with the IOS1
instruction. (In bit units)
The pin whose voltage is to be converted is specified with the IOS1
To the
A/D converter input
instruction, and the conversion is started with UCC instruction.
Note : Since input is disabled for ports specified for the ADI function,
ILC05541
executing an input instruction for such a port will always return
a low level.
Input is disabled in Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
O
General-purpose output ports (high-voltage output)
PJ0
76
PJ1
75
Since these are open-drain output circuits, external pull-up resistors
PJ2
74
are required.
PJ3
73
The internal transistors are turned off (resulting in a high-level output)
BACK UP
in Backup mode and after a power on reset.
ILC05542
PK0/INT0
72
PK1/INT1
71
I/O
General-purpose I/O and external interrupt shared function ports.
The input formats are Schmitt inputs.
PK2/INT2
70
The external interrupt function is enabled when the external interrupt
PK3/INT3
69
enable flag is set.
• When used as general-purpose I/O ports :
BACK UP
The mode (input or output) is set in 1-bit units using the IOS1
instruction.
• When used as external interrupt pins :
The external interrupt functions are enabled by setting the
corresponding external interrupt enable flag (INT0EN through
INT3EN). Here, the pins must be set to input mode in advance.
ILC05543
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
Continued on next page.
No.0459-12/17
LC72F3781
Continued from preceding page.
Pin name
Pin No.
I/O
PL0 to 3
68 to 61
I/O
PM0 to 3
Pin explanation
Equivalent circuit
General-purpose I/O ports
The mode is switched between input and output with the IOS
instruction.
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
PN0/BEEP
60
I/O
General-purpose I/O port and beep tone output shared function ports.
PN1
59
The IOS2 instruction is used to switch between the general-purpose
PN2
58
I/O port and the beep tone output functions.
PN3
57
• When used as general-purpose I/O ports :
The general-purpose I/O port function is set up with the IOS2
instruction.
BACK UP
(Pins PN1 through PN3 are dedicated general-purpose output pins.)
• When used as the beep tone output pin :
The beep tone output function is set up with the IOS2 instruction.
The frequency is set up with the BEEP instruction.
When this pin is used as the beep tone output pin, executing an
ILC05544
output instruction for this pin only sets the internal latch and has no
influence on the output.
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
PO0 to 3
56 to 49
I/O
PP0 to 3
General-purpose I/O ports
The mode is switched between input and output with the IOS
instruction.
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
PQ0 to 3
48 to 41
PR0 to 3
38 to 33
I/O
General-purpose I/O ports.
The mode is switched between input and output with the IOS
PS0 to 3
instruction, and data is input with the INR instruction and output with
PT0 to 3
the OUTR instruction.
BACK UP
The SPB, RPB, TPT, and TPF instruction cannot be used with these
ports.
Input is disabled and the pins go to the high-impedance state in
Backup mode.
ILC05544
These ports are set up as general-purpose input ports after a power
on reset.
TEST1
99
LSI test pins.
TEST2
2
These pins must be connected to GND.
No.0459-13/17
LC72F3781
Concerning Differences from the LC723781N, 2N, 3N, 4 and 5 Mask Versions
Item
Mask version (LC723781N, 2N, 3N, 4 and 5)
OTP version (LC72F3781)
Design rule
0.35µ process
0.45µ process
ROM
Masked ROM structure
Flash ROM structure
Write mode
Not available
Available
Design Considerations
1) Although the electrical specifications are the same for the mask and OTP versions, differences may arise in the actual
values for the threshold level of the input ports, output current of the output ports, input sensitivity, etc. Variations
may also be found from lot to lot. It must therefore be kept in mind that if finished products are designed using the
actual values of the samples, these variations may prevent the finished products from operating.
2) The undesirable radiation level is not listed among the specifications. Since differences may arise between the mask
and OTP versions, this must be kept in mind when designing the finished products.
Concerning ROM Writing
1) The job of writing data onto the ROM in-house at SANYO Semiconductor is not currently supported.
2) The LC72F3781 circuit board must be requested as the data writing board.
3) The AF-9706 or AF-9708 made by Ando or the 1890A or 1881XP made by Minato is recommended as the ROM
writer.
No.0459-14/17
LC72F3781
Example of Writing Data onto the on-chip Flash ROM of the LC72F3781
(using the AF-9706 or AF-9708)
I. Writing the data using the AF-9706 or AF-9708 (made by Ando) PROM programmer
1. ROMTYPE settings
ROMTYPE
→
→
→
→
→
→
Select [MAKER]
Select [SST]
Select [29EE010]
SET
SET
SET
2. Start/stop address settings
FUNCTION
→
1
: Address setting mode
* The address that corresponds to the ROM capacity provided in the table below must be set as the stop address.
Type No.
ROM capacity
Stop address
LC723781N
40KB
9FFF
LC723782N
48KB
BFFF
LC723783N
64KB
FFFF
LC723784
96KB
17FFF
LC723785
128KB
1FFFF
3. Executing data erasure
DEVICE
→
B
→
SET : For data erasure execution.
F
→
SET
4. Executing data writing
DEVICE
→
: For program and verify execution.
II. Writing board
The writing board is shown in the figure below. The position of pin 1 must be checked before connecting to the
EPROM programmer.
Pin 1 of LC72F3781
Pin 1 of EPROM
programmer
Note: The writing adapter has been changed.
To be used for the general-purpose EPROM programmer: Model LC72F3781-ADP-N EPROM programmer
No.0459-15/17
LC72F3781
Example of writing data onto the on-chip Flash ROM of the LC72F3781
(using the 1890A)
I. Data writing method
1. ROMTYPE settings
DEVICE
→
D734
→
ENTRY
→
ENTRY : Device code [29EE010]
2. Start/stop address settings
EDIT
→
PAE : Address setting mode
<1> Since BEGIN ADD is displayed, 00000 →
ENTRY
<2> Since END ADD is displayed, 1FFFF →
ENTRY (128kbytes = 1FFFF)
<3> Since BUF ADD is displayed, 00000 →
ENTRY
* The address that corresponds to the ROM capacity provided in the table below must be set as the stop address.
Type No.
ROM capacity
Stop address
LC723781N
40KB
9FFF
LC723782N
48KB
BFFF
LC723783N
64KB
FFFF
LC723784
96KB
17FFF
LC723785
128KB
1FFFF
3. Executing data writing
PROG
→
PAE
: For program and verify execution.
II. Writing board
The writing board is shown in the figure below. The position of pin 1 must be checked before connecting to the
EPROM programmer.
Pin 1 of LC72F3781
Pin 1 of EPROM
programmer
Note: The writing adapter has been changed.
To be used for the general-purpose EPROM programmer: Model LC72F3781-ADP-N EPROM programmer
No.0459-16/17
LC72F3781
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellctual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of September, 2006. Specifications and information herein are subject
to change without notice.
PS No.0459-17/17