Ordering number : EN*5519A CMOS LSI LC74411N, LC74411NE PIP Controller Preliminary Overview Package Dimensions The LC74411N and LC74411NE are digital processing controllers for PIP (picture-in-picture) systems in TV sets and VCRs. These ICs incorporate three circuits, a multiplexed A/D converter, field memory, and a D/A converter, to implement the PIP digital processing block in a single chip. unit: mm 3071-DIP64S [LC74411N] Features • Horizontal resolution: 450 pixels* • Single-chip implementation of the three circuits required in a PIP digital processing block: A/D converter, field memory, and D/A converter circuits • High image quality provided by vertical filtering • I2C bus adopted • Built-in PLL circuit (requires an external low-pass filter) • Supports NTSC and PAL, TV and VCR applications, and multi-format (NTSC and PAL) applications. • External control function • 8-bit D/A converter (PWM type): 6 pins • General-purpose ports: 8 pins • Sub-screen specifications • Display on/off, frame/no frame, frame color switching, wipe function • Display position - Specifiable as an 8-bit value for each of the horizontal and vertical directions. • Size Vertical reduction: 1/3, 1/4 Horizontal reduction: 1/3, 1/4 – The horizontal size can be adjusted by adjusting the PLL divisor – The display area vertical and horizontal positions can be varied independently. • Horizontal resolution (Y signal): about 190 dots • Quantization: 6 bits • Operating supply voltage LC74411NE : 5 V ±5% LC74411N : 5 V ±10% • Package LC74411NE : QFP64E LC74411N : DIP64S Note: D/A clock Y 11.6 MHz R-Y 2.9 MHz B-Y 2.9 MHz SANYO: DIP64S unit: mm 3159-QFP64E [LC74411NE] SANYO: QIP64E When the main screen synchronization PLL uses the standard value (PLL4 : 0 = 10110) SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 93196HA (OT) No. 5519-1/14 LC74411N, LC74411NE Pin Assignments No. 5519-2/14 LC74411N, LC74411NE Block Diagram No. 5519-3/14 LC74411N, LC74411NE LC74411N and LC74411NE Based PIP System Function Overview • Reduction sizes – Vertical : 1/3, 1/4; The vertical filter coefficient can be selected. – Horizontal : 1/3, 1/4; Variable at the PLL. • Still image – Field still image • Display position – Eight bits in each of the vertical and horizontal directions • Frame – Frame or no frame can be selected. – Frame types differ according to the insertion method Pin frame : A pin output that goes high at the frame position (for frame insertion by the application) DAC frame : Frame overlapped onto the image signal. Four bits for each of the Y, R-Y, and B-Y signals. • Wipe – Supports eleven different types of wipe. • Blanking size – The vertical and horizontal directions can be specified independently (6 bits each) – Eleven form specification types • Memory clear – The image data written to memory can be set to a fixed value. – Either 25% white or blue can be selected. • Wide-aspect-ratio TV support – Aspect compensation function • Support for NTSC, PAL, and multi-format systems • External control function using the I2C bus – Incorporates six on-chip 8-bit D/A converter circuits – Provides eight general-purpose port pins. • Wide range of settings and adjustments – Sub-screen displacement, color shifting, and other settings can be adjusted using the I2C bus. No. 5519-4/14 LC74411N, LC74411NE Sub-Screen Size The vertical and horizontal directions can be controlled independently. • Vertical size – 1/3: Three scan lines are compressed to one. – 1/4: Four scan lines are compressed to one. • Horizontal size – 1/3: A/D clock : D/A clock = 1:3 – 1/4: A/D clock : D/A clock = 1:4 When 1/4 compression is used, the output data will be 3/4 of 1/3 of the input data. – Aspect ratio correction function The horizontal size is adjusted by changing the VCO frequency (system clock). This frequency can be changed from –30% to +30%. Wipe Function The WTOP, WBOT, WLEFT, and WRIGHT operations can be specified independently. Display Area Function This function controls an area to be blanked. The vertical and horizontal directions can be set independently. The operating mode is set using the wipe function WTOP, WBOT, WLEFT, and WRIGHT parameters. No. 5519-5/14 LC74411N, LC74411NE Application Examples • Exclusion of the masked area from a letterbox screen • Small display Minimizes the hidden sections of the main screen. Internal Control Registers Bit Address MSB 7 LSB 6 5 4 3 2 1 0 Function 00H SBY STL NT/PAL D-BLUE D-FIX FILD VDF-C0 POUT 01H VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0 Mode settings Vertical display position 02H HP7 HP6 HP5 HP4 HP3 HP2 HP1 HP0 Horizontal display position 03H 0 SIZE-V SIZE-H DAFRM YFC5 YFC4 YFC3 YFC2 Sub-screen size, frame color 04H RFC5 RFC4 RFC3 RFC2 BFC5 BFC4 BFC3 BFC2 Frame color 05H 0 0 0 PLL4 PLL3 PLL2 PLL1 PLL0 PLL value 06H PHP-M PHP-S WPE WP-MOD WTOP WBOT WLEFT WRIGHT 07H 0 0 VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 08H 0 0 HBS5 HBS4 HBS3 HBS2 HBS1 HBS0 09H V-BLK H-BLK CL-AJ1 CL-AJ0 WV-AJ1 WV-AJ0 WH-AJ1 WH-AJ0 Fine adjustment Wipe Vertical display range Horizontal display range 0AH 0 YC-AJ2 YC-AJ1 YC-AJ0 YCFAJ1 YCFAJ0 FM-AJ1 FM-AJ0 Fine adjustment 0BH DAC1-7 DAC1-6 DAC1-5 DAC1-4 DAC1-3 DAC1-2 DAC1-1 DAC1-0 PWMDAC 0CH DAC2-7 DAC2-6 DAC2-5 DAC2-4 DAC2-3 DAC2-2 DAC2-1 DAC2-0 PWMDAC 0DH DAC3-7 DAC3-6 DAC3-5 DAC3-4 DAC3-3 DAC3-2 DAC3-1 DAC3-0 PWMDAC 0EH DAC4-7 DAC4-6 DAC4-5 DAC4-4 DAC4-3 DAC4-2 DAC4-1 DAC4-0 PWMDAC 0FH DAC5-7 DAC5-6 DAC5-5 DAC5-4 DAC5-3 DAC5-2 DAC5-1 DAC5-0 PWMDAC 10H DAC6-7 DAC6-6 DAC6-5 DAC6-4 DAC6-3 DAC6-2 DAC6-1 DAC6-0 PWMDAC 11H PORT7 PORT6 PORT5 PORT4 PORT3 PORT2 PORT1 PORT0 General-purpose ports 0: These bits must be set to 0. No. 5519-6/14 LC74411N, LC74411NE Register Data Overview Address Register 00H SBY STL NT/PAL D-BLUE D-FIX FILD VDF-CO POUT Notes Standby mode (The PLL circuit operates.) Still image (Writes to internal memory are stopped.) Format selection (H: NTSC, L:PAL) Memory clear data selection (Valid when D-FIX = 1) (H: blue, L: gray) Memory clear (Holds the data written to memory at a fixed value.) Field display selection Vertical filter coefficient selection Sub-screen display on/off 01H VP7 to 0 Sub-screen vertical position 02H HP7 to 0 Sub-screen horizontal position 03H SIZE-V SiZE-H DAFRM YFC5 to 2 Vertical compression specification H: 1/4, L: 1/3 Horizontal compression specification H: 1/4, L: 1/3 D/A converter frame on/off D/A converter frame color (Y) 04H RFC5 to 2 BFC5 to 2 D/A converter frame color (R-Y) D/A converter frame color (B-Y) 05H PLL4 to 0 PLL divisor value (The standard value is 10110.) 06H PHP-M, S WPE WP-MOD WTOP to WRIGHT Field discrimination inversion/noninversion Wipe or display area function enable Wipe or display area function selection (H: wipe) Wipe or display area function format specification 07H VBS5 to 0 Display area range setting (vertical) 08H HBS5 to 0 Display area range setting (horizontal) 09H V-BLK, H-BLK CL-AJ1, 0 WV-AJ1, 0 WH-AJ1, 0 0AH YC-AJ2 to 0 YCFAJ1, 0 FM-AJ1, 0 C phase (with respect to Y) adjustment D/A converter frame C phase (with respect to Y) adjustment D/A converter frame left/right width adjustment D/A converter frame output range specification (Normally set to 00B) A/D converter clamping potential adjustment (Can be monitored from the CLAMP pin.) Write vertical direction adjustment Write horizontal direction adjustment 0BH DAC1-7 to 0 External control D/A converter (8-bit PWM) data 0CH DAC2-7 to 0 External control D/A converter (8-bit PWM) data 0DH DAC3-7 to 0 External control D/A converter (8-bit PWM) data 0EH DAC4-7 to 0 External control D/A converter (8-bit PWM) data 0FH DAC5-7 to 0 External control D/A converter (8-bit PWM) data 10H DAC6-7 to 0 External control D/A converter (8-bit PWM) data 11H PORT7 to 0 Data for the general-purpose output ports No. 5519-7/14 LC74411N, LC74411NE Pin Functions Pin No. Pin I/O 21 RES I Initialization circuit 45 44 43 42 53 52 51 50 V-M H-M V-S H-S I I I I Main screen vertical synchronizing signal (negative polarity) Synchronization separation Main screen horizontal synchronizing signal (negative polarity) circuit IC Sub-screen vertical synchronizing signal (negative polarity) Sub-screen horizontal synchronizing signal (negative polarity) 14 22 SCL I Microcontroller 15 23 SDA 64E 64S 13 Connection I/O Microcontroller Function Reset Serial clock Serial data 16 24 ADDR0 I DVSS 17 25 ADDR1 I DVSS 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 PORT0 PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 PORT7 O O O O O O O O General-purpose ports 27 28 29 30 31 32 35 36 37 38 39 D/A1 D/A2 D/A3 D/A4 D/A5 D/A6 O O O O O O PWM D/A converter outputs 36 35 34 44 43 42 FRAME SOUT SOUT2 O O O 38 39 41 40 46 47 49 48 NC NC DVDD DVSS 64 63 62 61 8 7 6 5 YA-IN RA-IN BA-IN LVL-IN I I I I 37 45 CLAMP O Must be connected to VSS in normal operation. Analog circuits Analog circuits Frame pulse output Main/sub-screen switching signal No connection No connection Power supply Ground Digital system power supply Digital system power supply Analog circuits Analog circuits Analog circuits Circuit type Sub-screen analog input (Y) Sub-screen analog input (R-Y) Sub-screen analog input (B-Y) Preset voltage For use by user monitoring circuits A/D converter clamp pulse Notes:The 64E pin numbers refer to the LC74411NE and the 64S pin numbers refer to the LC74411N. The letter "S" in an inverter indicates Schmitt input characteristics. Continued on next page. No. 5519-8/14 LC74411N, LC74411NE Continued from preceding page. Pin No. Pin I/O 64E 64S 60 59 58 57 1 2 4 3 2 1 9 10 VRH1 VRH2 VRM VRB ADVDD ADVSS 54 53 52 51 50 55 56 62 61 60 59 58 63 64 YA-OUT RA-OUT BA-OUT VREF BIAS DAVDD DAVSS O O O I — 10 11 8 18 19 16 CP-M FC-M R-M O I — 9 12 17 20 VDD-M VSS-M 5 4 7 6 3 13 12 15 14 11 CP-S FC-S R-S VDD-S VSS-S O I — 49 48 47 46 33 18 57 56 55 54 41 26 TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 I I I I I I Connection Function Power supply or VRH2 Open or VRH1 Capacitor Capacitor and VREF Power supply Ground Low-pass filter Low-pass filter Oscillator range setting resistor Power supply Ground Analog circuits Analog circuits Analog circuits VRB Capacitor Power supply Ground Sub-screen digital analog output (Y) Sub-screen digital analog output (R-Y) Sub-screen digital analog output (B-Y) D/A converter analog setting pin Low-pass filter Low-pass filter Oscillator range setting resistor Power supply Ground Charge pump output Oscillator control voltage input Circuit type Analog system power supply (D/A converter) VCO power supply Low-pass filter Charge pump output Low-pass filter Oscillator control voltage input Oscillator range setting resistor Power supply VCO power supply Ground Testing (These pins must connected to DVSS.) DVSS Specifications Absolute Maximum Ratings at Ta = 25 ±2°C, VSS = 0 V Ratings Unit Maximum supply voltage Parameter VDD max Symbol –0.3 to +7.0 V Maximum input voltage VIN max –0.3 to VDD +0.3 V VOUT max –0.3 to VDD +0.3 Maximum output voltage Allowable power dissipation Pd max Conditions LC74411NE LC74411N V 550 mW 600 mW Operating temperature Topr –10 to +70 °C Storage temperature Tstg –55 to +125 °C Allowable Operating Ranges at Ta = –10 to +70°C, VSS = 0 V Parameter Symbol Supply voltage VDD Digital input high-level voltage VIH Digital input low-level voltage VIL Analog input voltage Reference voltage min typ max Unit LC74411NE Conditions 4.75 5.0 5.25 V LC74411N 4.5 5.0 5.5 0.7VDD 0.3VDD The YA-IN, RA-IN, and BA-IN pins VREF 0.8VDD V Vp-p ADVDD-VRB 2.7 V V VDD V No. 5519-9/14 LC74411N, LC74411NE Electrical Characteristics at Ta = 25 ±2°C, VDD = 5 V ±5% (LC74411NE), VDD = 5 V ±10% (LC74411N), VSS = 0 V Parameter Output high-level voltage Output low-level voltage Symbol Conditions min typ max Unit VOH1 IOH = –1 mA, the CP-M and CP-S pins VDD–1 VOH2 IOH = –1 mA, pins other than CP-M and CP-S VDD–1 VOL1 IOL = 1 mA, the CP-M and CP-S pins 1.0 V VOL2 IOL = 3 mA, the SDA pin 0.4 V VOL3 IOL = 2 mA, pins other than the pins mentioned above 0.4 V RES = VSS, DC pin inputs, no output loads 10 µA V V Quiescent current drain IDDST Reference voltage (M) VRM When VRH1 is connected to ADVDD 0.9VDD Reference voltage (B) VRB When VRH1 is connected to ADVDD 0.8VDD Input leakage current ILK VI = VDD, VSS –1 Output leakage current IOZ VI = VDD, VSS; the CP-M and CP-S pins –1 D/A converter output resistance RDA V V +1 µA +1 µA Ω 300 Switching Characteristics at Ta = 25 ±2°C, VDD = 5 V ±5% (LC74411NE), VDD = 5 V ±10% (LC74411N), VSS = 0 V Parameter Symbol Conditions min typ max Unit Vertical synchronizing signal Pulse width tVW Rise time tVR 300 ns Fall time tVF 300 ns 1 µs Horizontal synchronizing signal Pulse width tHW Rise time tHR 300 ns Fall time tHF 300 ns 100 kHz 1 µs I2C timing SCL frequency tSCL Bus release time tBUF 4.7 µs tHD STA 4.0 µs SCL low period tLOW 4.7 µs SCL high period tHIGH 4.0 µs µs Start/hold Data hold time tHD DAT 0 Data setup time tSU DAT 250 ns Rise time tR 1000 ns Fall time tF 300 ns Stop setup time tSU STO 4.0 µs No. 5519-10/14 LC74411N, LC74411NE Sub-Screen Digital Processing Specifications Item NTSC (fH = 15734Hz) Order Frequency fT (MHz) 480 fH 7.552 Y only A/D converter sampling fTY 3.776 0.944 0.944 fCY 736 fH 11.58 R-Y signal fCR fCB 2.895 2.875 184 fH 2.895 Number of horizontal bits 2.875 288 Y only 192 R-Y only 48 B-Y only Number of vertical lines 48 73 Number of horizontal bits Readout display*2 11.50 184 fH B-Y signal Write 0.938 6 bits Y signal (MHz)*1 0.938 60 fH Number of bits in quantization D/A converter clock 3.750 60 fH B-Y only fTB 7.500 240 fH R-Y only fTR PAL (fH = 15625Hz) Y, R–Y, Y, B–Y, Y, –, Y, –, ······ 85 268 Y only 180 R-Y only 44 B-Y only Number of vertical lines 44 72 84 Note: 1. When the PLL divisor has its standard value (PLL4:0 = 10110). 2. Target values are shown. (The number of horizontal bits varies with, for example, the frame width adjustment.) Initialization (1) RES pin: Reset The RES pin must be held low when power is first applied with the timing shown in the figure. (2) Internal control registers After a reset, the chip goes to the standby state (SBY = high). When developing the microcontroller software, that software must be designed so that it transmits data for all registers. Also note that data values of zero (0) must be sent for the control registers that have ‘0’ entries in the control register table. No. 5519-11/14 LC74411N, LC74411NE I2C Control Data format Data 1 is stored at register address A1. Data 2 is stored at register address A1 + 1, i.e., the address given by incrementing A1. If the address exceeds 11H, it wraps to 00H. Slave address: A6 A5 A4 A3 A2 A1 A0 R/W 0 0 1 0 0 1 1 0 Synchronizing Signal Input • Sync separation The LC74411N and LC74411NE require sync separated (including AFC processing) V and H signals for both the main and sub-screen. Since V is used for field discrimination and H is used as the PLL reference signal, these signals must be provided reliably. – The H-M and H-S pin inputs are assumed to be delayed about 1 µs from the video signal’s horizontal synchronizing signal and set to standard values. – Equalizing pulses must be excluded. – Since noise on the synchronizing signal will disrupt the display, these lines should be placed carefully. – If the synchronizing signal is unstable, the sub-screen display may be disrupted. We recommend turning off subscreen display in such cases. • Field discrimination circuit Since the circuit discriminates based on the phase difference between the falling edges of the H and L signals, these signals must be provided with the timing shown in the figure below. No. 5519-12/14 LC74411N, LC74411NE Clamp Pulses • A/D converter clamping Since clamp pulses are output to the built-in A/D converter with the timing shown in the figure below, they are set up to fall in the pedestal range. The clamp pulses can be monitored at the CLAMP pin. On a reset or in standby mode, the H-S input signal becomes positive polarity and is output without change. • D/A converter clamp External Control Output Blanking No. 5519-13/14 LC74411N, LC74411NE ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of September, 1996. Specifications and information herein are subject to change without notice. No. 5519-14/14