FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12545-1E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89960 Series
MB89965/P965A/F969A/
MB89PV960
■ DESCRIPTION
The MB89960 series is a single-chip microcontroller that utilizes the F2MC-8L core for low voltage and high speed
performance. The microcontroller contains a range of peripheral functions including timers, a serial interface, I2C
interface, A/D converter, and external interrupts. The internal I2C interface complies with the SM bus standard
and supports an SM bus battery controller.
■ FEATURES
• Range of package options
• QFP and MQFP packages (0.8 mm pitch)
• LQFP package (0.5 mm and 0.65 mm pitch)
• High speed operation at low voltage
Minimum instruction execution time = 0.4 µs (for a 10 MHz oscillation)
• F2MC-8L CPU core
Instruction set optimized for controller applications
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instructions
• Bit manipulation instructions, etc.
• Dual-clock control system
• Main clock : 10 MHz max.
(Four speed settings available, oscillation halts in sub-clock mode)
• Sub-clock : 32.768 kHz (Operation clock for sub-clock mode)
•
•
•
•
Four channels
8/16-bit timer/counter (8-bit × 2 channels or 16-bit × 1 channel)
21-bit timebase timer
Clock prescaler (15-bit)
• Serial I/O
Selectable transfer format (MSB-first or LSB-first) supports communications with a wide range of devices.
• A/D converter
10-bit × 4 channels
MB89960 Series
• External interrupts
• External interrupt 1 (3 channels)
Three independent interrupt inputs can be used to recover from low-power consumption modes (with edgedetection function)
• External interrupt 2 (1 channel with 8 inputs)
Eight inputs can be used to recover from low-power consumption modes (with “L” level detection function)
•
•
•
•
Low-power consumption modes (standby modes)
Stop mode (As all oscillations halt in sub-clock mode, current consumption falls to almost zero.)
Sleep mode (The CPU stops to reduce the current consumption to approximately 1/3 of normal.)
Clock mode (All operation halts other than the clock prescaler resulting in very low power consumption.)
• I2C interface*
• Supports Intel SM bus and Philips I2C bus standards.
• Uses a two-wire data transfer protocol.
•
•
•
•
Max. 35 I/O ports
Output-only ports (N-ch open drain)
General-purpose I/O ports (CMOS)
Output-only ports (CMOS)
:6
: 21
:8
* : I2C license
The customer is licensed to use the Philips I2C patent when using this product in an I2C system that complies
with the Philips I2C standard specifications.
■ PACKAGE
2
Plastic LQFP, 48-pin
Plastic QFP, 48-pin
Plastic QFP, 48-pin
(FPT-48P-M05)
(FPT-48P-M13)
(FPT-48P-M16)
Ceramic MQFP, 48-pin
Plastic LQFP, 64-pin
(MQP-48C-P01)
(FPT-64P-M09)
MB89960 Series
■ PRODUCT LINEUP
Part No.
Prameter
Classification
MB89965
MB89P965A
Mass-produced
products
(mask ROM products)
One-time product
ROM size
16 K × 8-bit (Internal mask ROM)
RAM size
512 × 8-bit
CPU functions
Ports
MB89F969A
MB89PV960
Flash product
Piggyback/
evaluation product
for testing and
development
60 K × 8-bit
32 K × 8-bit
(External ROM) *
1024 × 8-bit
Number of instructions
Instruction bit length
Instruction length
Data bit length
Minimum execution time
Interrupt processing time
: 136
: 8-bit
: 1 to 3 bytes
: 1-, 8-, 16bits
: 0.4 µs (at 10 MHz)
: 3.6 µs (at 10 MHz)
Output-only ports (N-ch open drain)
: 6 (4 pins are shared with analog inputs)
(2 pins are shared with resource I/O)
:8
: 21 (shared with resource I/O)
35 (max.)
Output-only ports (CMOS)
General-purpose I/O ports (CMOS)
Total
21-bit
Timebase timer Four interrupt intervals selectable 0.82 ms, 3.3 ms, 26.2 ms, or 419.4 ms (approx.) (for
main clock)
Watchdog timer
Reset trigger period : 419.4 ms (10 MHz main clock)
500 ms (32.768 MHz sub-clock)
One channel. Supports Intel SM bus (version 1.0) and Philips I2C bus standards.
Uses a 2-wire protocol for communications with other devices.
Peripheral
functions
I2C interface
Included/Not included
(Specified when ordering. See “Ordering Information” for details.)
Included
8/16-bit timer/
counter Timer
2 channel 8-bit timer/counter operation (independent operation clocks for timer 1 and
timer 2) or 16-bit timer/counter operation (operation clock period : 0.8 µs to 204.8 µs)
can execute an event counter operation and output a square wave using an external
Clock.
1 or 16-bit timer/counter operation mode
Serial I/O
8 bits
LSB-first or MSB-first selectable
Transfer clocks : External or three internal clocks (0.8 µs, 3.2 µs, 12.8 µs)
External
interrupt 1
(edge)
Selectable edge detection (rising, falling, or either edge)
3 independent channels
These can also be used to recover from standby modes (edge detection is still available
in stop mode) .
External
interrupt 2
(level)
1 channel with 8 inputs (“L” level interrupts, independent input enable)
This can also be used to recover from standby modes (level detection is still available in
stop mode) .
(Continued)
3
MB89960 Series
(Continued)
Part No.
MB89965
Prameter
MB89P965A
MB89F969A
MB89PV960
4 channel × 10-bit resolution
A/D conversion time : 15.2 µs (MB89965, MB89P965A, MB89F969A)
13.2 µs (MB89PV960)
Continuous activation is available using the output from the 8/16-bit timer/counter or
timebase timer.
Reference voltage input (AVR)
Periph- A/D converter
eral
functions
15-bit
Clock prescaler
Interrupt interval : 31.25 ms, 0.25 s, 0.50 s, 1.00 s (for a 32.768 kHz sub-clock)
Low power consumption (standby modes)
Sleep mode, stop mode, and clock mode
Process
CMOS
Operating voltage
3.5 V to 5.5 V
* : Use the MBM27C256A-20TVM as the external ROM (Operating voltage : 4.5 V to 5.5 V)
Note : Unless otherwise stated, clock periods and conversion times are for 10 MHz operation with the main clock
operating at maximum speed.
■ PACKAGES AND CORRESPONDING PRODUCTS
Part No.
MB89F969A
MB89PV960
FPT-48P-M05
×
×
FPT-48P-M13
×
×
FPT-48P-M16
×
×
Package
MB89P965A
FPT-64P-M09
×
×
MQP-48C-P01
×
×
: Available
× : Not available
4
MB89965
×
×
MB89960 Series
■ DIFFERENCES AMONG PRODUCTS
1.
Memory Space
Please take note of the differences among products before testing and developing software for the MB89960
series.
• The RAM and ROM configurations differ among products.
• If the bottom stack address is set at the top RAM address, this will need to be relocated if changing to a different
product.
2. Current Consumption
• In the case of the MB89PV960, add the current consumed by the EPROM which is connected to the top socket.
• When operated at low speed, one-time PROM and EPROM products will consume more current than mask
ROM products. However, the current consumption in sleep/stop modes is the same.
3. Functional Differences Between MB89960 Series
MB89965/P965A/F969A
MB89PV960
Power-on reset delay time
Regulator stabilization delay time,
regulator recovery time,
oscillation stabilization delay time
Oscillation stabilization delay time
External reset delay time in stop/
sub-clock mode or external
interrupt delay time in main stop
mode
Regulator recovery time,
oscillation stabilization delay time
Oscillation stabilization delay time
Port pin pull-up resistors
Software-selectable
Not available
A/D conversion time
38 instruction cycles
33 instruction cycles
Always present regardless of ICCR :
DMPB bit setting
Disabled if ICCR : DMPB bit = “1”
I2C noise elimination circuit
4. Mask Options
Functions that can be selected as options and the methods used to specify these options vary by the product.
Before using mask options, check section “
Mask Options”.
5
MB89960 Series
■ PIN ASSIGNMENT
48
47
46
45
44
43
42
41
40
39
38
37
P40/AN0
P41/AN1
P42/AN2
P43/AN3
AVR
AVSS
P44/SDA
P45/SCL
P30/SCK
P31/SO
P32/SI
P33/EC
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
P34/TO/CLK
C
P00/INT20
P01/INT21
P02/INT22
P03/INT23
P04/INT24
P05/INT25
P06/INT26
P07/INT27
P10/INT10
P11/INT11
P24
P23
P22
P21
P20
P17
VSS
P16
P15
P14
P13
P12/INT12
13
14
15
16
17
18
19
20
21
22
23
24
AVCC
RST
MOD0
MOD1
X0
X1
VCC
X0A
X1A
P27
P26
P25
(FPT-48P-M05)
(FPT-48P-M13)
(FPT-48P-M16)
(Continued)
6
MB89960 Series
(Continued)
69
70
71
72
73
74
75
76
60
59
58
57
56
55
54
53
36
35
34
33
32
31
30
29
28
27
26
25
P34/TO/CLK
N.C.
P00/INT20
P01/INT21
P02/INT22
P03/INT23
P04/INT24
P05/INT25
P06/INT26
P07/INT27
P10/INT10
P11/INT11
P24
P23
P22
P21
P20
P17
VSS
P16
P15
P14
P13
P12/INT12
13
14
15
16
17
18
19
20
21
22
23
24
77
78
79
80
49
50
51
52
1
2
3
4
5
6
7
8
9
10
11
12
AVCC
RST
MOD0
MOD1
X0
X1
VCC
X0A
X1A
P27
P26
P25
68
67
66
65
64
63
62
61
48
47
46
45
44
43
42
41
40
39
38
37
P40/AN0
P41/AN1
P42/AN2
P43/AN3
AVR
AVSS
P44/SDA
P45/SCL
P30/SCK
P31/SO
P32/SI
P33/EC
(TOP VIEW)
(MQP-48C-P01)
* : Pin assignment on package top (MB89PV960)
Pin
Pin
Pin No.
Pin No.
Pin No.
Name
Name
Pin
Name
Pin No.
Pin
Name
49
VPP
57
N.C.
65
O4
73
OE
50
A12
58
A2
66
O5
74
N.C.
51
A7
59
A1
67
O6
75
A11
52
A6
60
A0
68
O7
76
A9
53
A5
61
O1
69
O8
77
A8
54
A4
62
O2
70
CE
78
A13
55
A3
63
O3
71
A10
79
A14
56
N.C.
64
VSS
72
N.C.
80
VCC
N.C. : Internally connected. Do not use.
(Continued)
7
MB89960 Series
(Continued)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
N.C.
N.C.
P24
P23
P22
P21
P20
P17
VSS
P16
P15
P14
P13
P12/INT12
N.C.
N.C.
TEST
MOD2
AVCC
RST
MOD0
MOD1
X0
X1
VCC
X0A
X1A
P27
P26
P25
N.C.
N.C.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
N.C.
N.C.
P40/AN0
P41/AN1
P42/AN2
P43/AN3
AVR
AVSS
P44/SDA
P45/SCL
P30/SCK
P31/SO
P32/SI
P33/EC
N.C.
N.C.
(TOP VIEW)
(FPT-64P-M09)
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
N.C.
N.C.
P34/TO/CLK
C
P00/INT20
P01/INT21
P02/INT22
P03/INT23
P04/INT24
P05/INT25
P06/INT26
P07/INT27
P10/INT10
P11/INT11
N.C.
N.C.
MB89960 Series
■ PIN DESCRIPTIONS
Pin No.
Pin Name
MQFP-48*
LQFP-48*1
QFP-48*2
LQFP-64*
5
5
7
X0
6
6
8
X1
8
8
10
X0A
9
9
11
X1A
3
3
5
MOD0
4
4
6
MOD1
3
2
4
Function
A
Oscillator connection pins for the main clock oscillator (crystal oscillator or similar) .
When using an external clock, input the clock
signal to X0 and leave X1 open.
B
Oscillator connection pins for the sub-clock oscillator (crystal oscillator or similar) .
When using an external clock (low speed :
32.768 kHz) , input the clock signal to X0A and
leave X1A open.
C
Input pins for setting the memory access mode.
Connect directly to VSS.
D
Reset I/O pin
This is an N-ch open-drain output type with pullup resistor and a hysteresis input type. The pin
outputs “L” when an internal reset is present.
Similarly, inputting “L” initializes the internal circuits.
E
General-purpose I/O ports
Also serves as the external interrupt 2 inputs
(wakeup inputs) . The external interrupt 2 inputs
are hysteresis inputs.
4
RST
27 to 34
37 to 44
P00/INT20
to
P07/INT27
24 to 26
24 to 26
30,
35,
36
P10/INT10
to
P12/INT12
E
General-purpose I/O ports
Also serves as the external interrupt 1 inputs
(wakeup inputs) . The external interrupt 1 inputs
are hysteresis inputs.
18,
20 to 23
18,
20 to 23
24,
26 to 29
P13
to
P17
E
General-purpose I/O ports
10 to 17
10 to 17
12 to 14
19 to 23
P20
to
P27
G
General-purpose outoput-only ports
40
40
54
P30/SCK
F
General-purpose I/O port
Also serves as the serial clock I/O.
A hysteresis input.
39
39
53
P31/SO
F
General-purpose I/O port
Also serves as the serial I/O data output.
A hysteresis input.
27 to 34
2
Circuit
Type
*1 : FPT-48P-M05
(Continued)
*2 : FPT-48P-M16, FPT-48P-M13
*3 : MQP-48C-P01
*4 : FPT-64P-M09
9
MB89960 Series
(Continued)
Pin No.
Pin Name
Circuit
Type
52
P32/SI
F
General-purpose I/O port
Also serves as the serial I/O data input.
A hysteresis input.
51
P33/EC
F
General-purpose I/O port
Also serves as the external clock input for the 8/
16-bit timer/counter. A hysteresis input.
F
General-purpose I/O port
Also serves as the overflow output for the 8/16bit timer/counter and the CLK clock
output. A hysteresis input.
MQFP-48*
LQFP-48*1
QFP-48*2
LQFP-64*
38
38
37
37
3
Function
36
36
46
P34/TO/
CLK
35
45
C
Connect a 0.1 µF capacitor on the MB89965,
MB89P965A, and MB89F969A.
45 to 48
45 to 48
59 to 62
P40/AN0
to
P43/AN3
H
General-purpose Nch open-drain outputs.
Also serves as the A/D converter analog inputs.
42
42
56
P44/SDA
I
General-purpose Nch open-drain output.
Also serves as the I2C interface data output.
41
41
55
P45/SCL
I
General-purpose Nch open-drain output.
Also serves as the I2C interface clock I/O.
7
7
9
VCC
Power supply pin
19
19
25
VSS
Power supply (GND) pin
1
1
3
AVCC
A/D converter power supply pin
Use this pin at the same voltage as VCC.
44
44
58
AVR
A/D converter reference voltage input pin
43
43
57
AVSS
A/D converter power supply pin
Use this pin at the same voltage as VSS.
35
15 to 18
31 to 34
47 to 50
63, 64
N.C.
These pins are not connected.
Do not connect these on the MB89PV960.
1
TEST
C
TEST pin. Connect directly to VSS.
Only used on the MB89F969A.
Treat as an N.C. pin on the MB89965.
C
Memory access mode setting pin. Connect directly to VSS.
Only used on the MB89F969A.
Treat as an N.C. pin on the MB89965.
2
*1 : FPT-48P-M05
*2 : FPT-48P-M16, FPT-48P-M13
*3 : MQP-48C-P01
*4 : FPT-64P-M09
10
4
MOD2
MB89960 Series
• Pin Descriptions for External EPROM (MB89PV960 only)
Pin No.
Pin Name
I/O
Function
49
Vpp
O
“H” level output pin
50
51
52
53
54
55
A12
A7
A6
A5
A4
A3
O
Address output pins
58
59
60
A2
A1
A0
O
Address output pins
61
62
63
O1
O2
O3
I
Data input pins
64
VSS
65
66
67
68
69
O4
O5
O6
O7
O8
I
Data input pins
70
CE
O
ROM chip enable pin
Outputs “H” during standby mode.
71
A10
O
Address output pin
73
OE
O
ROM output enable pin
Always outputs “L”.
75
76
77
78
79
A11
A9
A8
A13
A14
O
Address output pins
80
VCC
EPROM power supply pin
56
57
72
74
N.C.
Internally connected pins
Always leave open circuit.
Power supply (GND) pin
11
MB89960 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
X1
Nch
Pch
Pch
X0
High speed clock (main clock oscillation)
• Oscillation feedback resistor
A
Nch
Main clock control signal
X1A
Nch
Pch
Pch
X0A
Low speed clock (sub-clock oscillation)
• Oscillation feedback resistor
B
Nch
Nch
Sub-clock control signal
• CMOS input
C
R
Pch
• Output pull-up resistor (Pch)
approx. 50 kΩ (at 5 V)
• Hysteresis input
D
Nch
R
Pch
Pull-up
Pch
• CMOS output
• CMOS input
• Selectable pull-up resistor
approx. 50 kΩ (at 5 V)
E
Nch
Port
Resource
(Continued)
12
MB89960 Series
(Continued)
Type
Circuit
R
Pch
Remarks
Pull-up
• CMOS output
• Hysteresis input
• Selectable pull-up resistor
approx. 50 kΩ (at 5 V)
Pch
F
Nch
Resource
Pch
• CMOS output
G
Nch
R
Pch
•
•
•
•
Pull-up
H
Nch
Nch-open drain output
Analog input (A/D converter)
Selectable pull-up resistor
(The pull-up resistor cannot be used
when used as an analog input.)
approx. 50 kΩ (at 5 V)
Analog input
Nch
I
SMB buffer
SMB input
I2C buffer
• Nch open drain output
• Selectable SMB or I2C
input buffer
I2C input
13
MB89960 Series
■ HANDLING DEVICES
1.
Do not exceed maximum rated voltage (to prevent latch-up)
Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input or output pins
other than medium- and high voltage pins or if the voltage applied between VCC and VSS higher the rating.
If latch-up occurs, the power supply current increases rapidly resulting in thermal damage to circuit elements.
Therefore, ensure that maximum ratings are not exceeded in circuit operation.
Similarly, when turning the analog power supply on or off, ensure the analog power supply voltages (AVCC and
AVR) and analog input voltages do not exceed the digital power supply (VCC) .
2. Power supply voltage fluctuations
Rapid fluctuation of the voltage may cause the device to misoperate, even if the voltage remains within the
allowed operating range.
The standard for power supply voltage stability is a peak-to-peak VCC ripple voltage at the mains supply frequency
(50 to 60 Hz) of 10% or less of VCC and a transient voltage change rate of 0.1 V/ms or less such as when turning
the power supply on or off.
3.
Treatment of unused input pins
Leaving unused input pins unconnected can cause misoperation or permanent damage to the device due to
latchup. Always pull-up or pull-down unused input pins using a 2 kΩ or larger resistor.
If some I/O pins are unused, either set as outputs and leave open circuit or set as inputs and treat in the same
way as input pins.
4.
Treatment of N.C. pins
Always leave N.C. (internally connected) pins open.
5. Treatment of power supply pins on microcontrollers with an A/D converter
Even if not using the A/D converter, connect to be AVCC = VCC and AVSS = AVR = VSS.
6. Precautions on using an external clock
An oscillation stabilization delay occurs after a power-on reset or when recovering from sub-clock or stop mode,
even if an external clock is used.
14
MB89960 Series
■ PROGRAMMING SPECIFICATIONS FOR ONE-TIME PROM PRODUCTS
The MB89P965A has a “PROM mode” that enables the microcontroller to be programmed using a generalpurpose ROM programmer via a special adaptor. Note, however, that electronic signature mode is not available.
1. ROM Programmer Adaptor and Recommended ROM Writers
Package Name
Adaptor Part No.
Recommended Programmer Manufacturer and Model
Sun Hayato Co. Ltd.
Ando Denki Co. Ltd.
FPT-48P-M05
ROM2-48LQF-32DP-8LA
FPT-48P-M13
ROM2-48QF2-32DP-8LA
AF9708 (ver 1.44 or later)
AF9709 (ver 1.44 or later)
FPT-48P-M16
ROM2-48QF-32DP-8LA
• Enquiries
Sun Hayato Co. Ltd. : TEL 03-3986-0403
Ando Denki Co. Ltd. : TEL 044-549-7300
2. PROM Mode Memory Map
Normal operating mode
0000H
I/O
0080H
RAM
0100H
0200H
Generalpurpose
registers
0280H
Not available
PROM mode
(addresses on ROM programmer)
0000H
C000H
Program
area
(PROM)
FFFFH
Program
area
(PROM)
3FFFH
3. PROM Programming Procedure (When using an Ando EPROM programmer)
1) Set the EPROM programmer type code to 17209.
2) Load the program data into addresses 0000H to 3FFFH in the EPROM programmer.
3) Use the EPROM programmer to program to addresses C000H to FFFFH.
4. Programming Yield
Due to the nature of OTPROM memory, a program test to all bits on a blank OTPROM microcontroller cannot
be performed at Fujitsu. For this reason, a programming yield of 100% cannot be assured at all times.
15
MB89960 Series
■ PROGRAMMING AND ERASING FLASH MEMORY ON THE MB89F969A
1. Flash Memory
The flash memory is located between 1000H and FFFFH in the CPU memory map and incorporates a flash
memory interface circuit that allows read access and program access from the CPU to be performed in the same
way as mask ROM. Programming and erasing flash memory is also performed via the flash memory interface
circuit by executing instructions in the CPU. This enables the flash memory to be updated in place under the
control of the CPU, providing an efficient method of updating program and data.
2. Flash Memory Features
•
•
•
•
•
•
•
•
60 K byte × 8-bit configuration (16 K + 8 K + 8 K + 28 K sectors)
Automatic programming algorithm (Embedded algorithm* : Equivalent to MBM29LV200)
Includes an erase pause and restart function
Data polling and toggle bit for detection of program/erase completion
Detection of program/erase completion via CPU interrupt
Compatible with JEDEC-standard commands
Sector Protection (sectors can be combined in any combination)
No. of program/erase cycles : 10,000 (min.)
Embedded Algorithm is a trademark of Advanced Micro Devices.
3. Procedure for Programming and Erasing Flash Memory
Programming and reading flash memory cannot be performed at the same time. Accordingly, to program or
erase flash memory, the program must first be copied from flash memory to RAM so that programming can be
performed without program access from flash memory.
4. Flash Memory Register
• Control status register (FMCS)
Address
bit7
002EH
bit6
bit5
bit4
INTE RDYINT
WE
RDY
R/W
R/W
R
R/W
bit3
bit2
Reserved Reserved
R/W
R/W
bit0
Initial value
Reserved
000X00-0B
R/W
bit1
5. Sector Configuration
The table below shows the sector configuration of flash memory and lists the addresses of each sector for both
during CPU access a flash memory programming.
• Sector configuration of flash memory
Flash Memory
CPU Address
Programmer Address
16 K bytes
FFFFH to C000H
1FFFFH to 1C000H
8 K bytes
BFFFH to A000H
1BFFFH to 1A000H
8 K bytes
9FFFH to 8000H
19FFFH to 18000H
28 K bytes
7FFFH to 1000H
17FFFH to 11000H
* : Programmer address
The programmer address is the address to be used instead of the CPU address when programming data from
a parallel flash memory programmer. Use the programmer address on programming or erasing using a generalpurpose parallel programmer.
16
MB89960 Series
6. ROM Programmer Adaptor and Recommended ROM Programmers
Package Name
FPT-64P-M09
Adaptor Part No.
Recommended Programmer Manufacturer and Model
Sun Hayato Co. Ltd.
Ando Denki Co. Ltd.
FLASH-64QF2-32DP-8LF
AF9708 (ver 1.60 or later)
AF9709 (ver 1.60 or later)
• Enquiries
Sun Hayato Co. Ltd. : TEL 03-3986-0403
Ando Denki Co. Ltd. : TEL 044-549-7300
17
MB89960 Series
■ PROGRAMMING A PIGGYBACK/EVALUATION EPROM
1. EPROM Type
MBM27C256A-20TVM
2. Programming Adaptor
Use the following programming adaptor (made by Sun Hayato Co. Ltd.) to program the EPROM using a ROM
programmer.
• Programming adaptor
Package
Adaptor Socket Part No.
LCC-32 (Square)
Enquiries
ROM-32LC-28DP-S
Sun Hayato Co. Ltd. : TEL03-3986-0403
3. Memory Space
Normal operating mode
0000H
I/O
0080H
RAM
0280H
Not available
EPROM mode
(addresses on ROM programmer)
0000H
8000H
Program
area
(PROM)
FFFFH
Program
area
(PROM)
7FFFH
4. EPROM Programming Procedure
(1) Setup the EPROM programmer to the MBM27C256A.
(2) Load the program data into addresses 0000H to 7FFFH in the EPROM programmer.
(3) Use the ROM programmer to program to addresses 0000H to 7FFFH.
18
MB89960 Series
■ BLOCK DIAGRAM
Main clock
High speed
oscillator circuit
(Max. 10 MHz)
Sub-clock
X0A
X1A
Timebase timer
Clock control
Reset circuit
(watchdog timer)
Low speed
oscillator circuit
(32.768 kHz)
16-bit
timer/counter
8-bit
timer/counter 2
Clock prescaler
5
8
External interrupt 2
(Level)
3 External interrupt 1
(edge)
P34/TO/CLK
8-bit
timer/counter 1
Internal data bus
3
Port 1
P10/INT10
to P12/INT12
8
Port 0
CMOS I/O port
P00/INT20
to P07/INT27
RST
Port 3
X0
X1
P33/EC
P32/SI
P31/SO
P30/SCK
8-bit
serial I/O
CMOS I/O port
P13 to P17
AVR
AVCC
AVSS
8
P20 to P27
Port 2
CMOS I/O port
CMOS output port
4
4
Port 4
10-bit
A/D converter
R A M
F2MC-8L
C P U
I2C interface
R O M
Nch open drain
output port
P40/AN0
∼ P43/AN3
P44/SDA
P45/SCL
Other pins
MOD0, MOD1, Vcc, Vss, C
19
MB89960 Series
■ CPU CORE
1. Memory Space
(1) Structure of memory space
• I/O area (address : 0000H to 007FH)
• Assign the control registers, data registers, and similar of the internal peripheral functions.
• As the I/O area is allocated as part of the memory space, it can be accessed in the same way as memory.
Direct addressing also provides high speed access.
•
•
•
•
•
•
RAM area
Static RAM is provided as an internal data area.
The size of internal RAM differs between products.
Addresses 80H to FFH provide high speed access using direct addressing.
Addresses 100H to 1FFH are used as the general-purpose register area.
The initial value of RAM after a reset is undefined.
•
•
•
•
ROM area
ROM memory is provided as the internal program area.
The size of internal ROM differs between products.
Addresses FFC0H to FFFFH are used for the vector table and similar.
(2) Memory map
MB89965
MB89P965A
MB89F969A
0000H
0000H
I/O
I/O
0080H
0080H
RAM
RAM
Registers
0280H
RAM
0100H
Registers
0200H
0200H
I/O
0080H
0100H
0100H
MB89PV960
0000H
0480H
1000H
Registers
0200H
Not available
0480H
Not available
Not available
8000H
C000H
ROM
ROM
ROM
FFC0H
FFC0H
FFC0H
FFFFH
FFFFH
FFFFH
Vector table
(Reset, interrupt, vector call instruction)
20
MB89960 Series
2. Registers
The MB89960 series provides two types of registers: dedicated registers in the CPU and general-purpose
registers. The dedicated registers are as follows.
Program counter (PC)
Accumulator (A)
: A 16-bit register for indicating the instruction storage positions.
: A 16-bit register that provides temporary storage for arithmetic operations and
similar. Instructions that operate on 8-bit data use the lower byte.
Temporary accumulator (T) : A 16-bit register used for arithmetic operations with the accumulator. Instructions
that operate on 8-bit data use the lower byte.
Index register (IX)
: A 16-bit register used for index modification.
Extra pointer (EP)
: A 16-bit pointer used for indicating a memory address .
Stack pointer (SP)
: A 16-bit register used for indicating a stack area.
Program status (PS)
: A 16-bit register used to store a register pointer and condition code.
16 bits
Initial value
PC
: Program counter
FFFDH
A
: Accumulator
Undefined
T
: Temporary accumulator
Undefined
IX
: Index register
Undefined
EP
: Extra pointer
Undefined
SP
: Stack pointer
Undefined
RP
CCR
I flag = 0, IL1, IL0 = 11
Other bits are undefined
: Program status
PS
The upper 8 bits of the PS contain the register bank pointer (RP) and the lower 8 bits contain the condition code
register (CCR) . (See the diagram below.)
RP
PS
CCR
bit15 bit14 bit13 bit12 bit11 bit10 bit9
R4
R3 R2 R1 R0
−
−
bit8
−
bit7
H
bit6
I
bit5
IL1
bit4
IL0
bit3
N
bit2
Z
bit1
bit0
V
C
CCR Initial value
X011XXXXB
Half carry flag
Interrupt enable flag
Interrupt level bits
Negative flag
Zero flag
Overflow flag
Carry flag
X : Undefined
21
MB89960 Series
The RP contains the address of the currently used register bank. The conversion diagram below shows the
relationship between the RP value and actual address.
Rules for converting of actual addresses of the general-purpose register area
Lower (op code)
Upper (RP)
"0"
Actual address
"0"
"0"
"0"
"0"
"0"
A15 A14 A13 A12 A11 A10
"0"
A9
"1"
A8
R4
R3
A7
R2
A6
A5
R1
A4
R0
A3
b2
A2
b1
A1
b0
A0
CCR contains bits that indicate the result of an arithmetic operation or information about transfer data and bits
used to control CPU operation when an interrupt occurs.
H-flag
I-flag
IL1, 0
N-flag
Z-flag
V-flag
C-flag
22
: Set to “1” when a carry from bit 3 to bit 4 or a borrow from bit 4 to bit 3 occurs as a result of an
arithmetic operation. Cleared to “0” otherwise. This flag is for decimal adjustment instructions and
should be ignored for operations other than addition and subtraction.
: Interrupts are enabled when this flag is set to “1” and disabled when the flag is set to “0”. Cleared
to “0” by a reset.
: Indicates the level of interrupts currently allowed. The CPU only processes interrupts with a request level higher than the value indicated by these bits.
IL1
IL0
Interrupt Level
0
0
0
1
1
0
2
1
1
3
1
Priority
High
Low = No interrupt
: Set to “1” when the MSB of the result of an arithmetic operation is “1” and cleared to “0” when the
MSB is “0”.
: Set to “1” when the result of an arithmetic operation is zero. Cleared to “0” otherwise
: Set to “1” when a 2’s complement overflow occurs as the result of an arithmetic operation. Cleared
to “0” if no 2’s complement overflow occurs.
: Set to “1” when a carry from bit 7 or a borrow to bit 7 occurs as the result of an arithmetic operation. Cleared to “0” otherwise. Set to the shift-out value in the case of a shift instruction.
MB89960 Series
The following general-purpose registers are provided :
General-purpose registers : 8-bit resisters for storing data
The general-purpose registers are 8-bit registers and are allocated in the register banks of the memory. Each
bank contains 8 registers and all 32 banks can be used on MB89960 series microcontrollers.
The register bank pointer (RP) specifies the bank that is currently in use.
Register bank structure
Address = 0100H + 8 × (RP)
R0
R1
R2
R3
R4
R5
R6
R7
32 banks
Memory area
23
MB89960 Series
■ I/O MAP
Address
Abbreviation
Register Name
Read/Write
Initial Value
00H
PDR0
Port 0 data register
R/W
XXXXXXXXB
01H
DDR0
Port 0 direction register
W
0 0 0 0 0 0 0 0B
02H
PDR1
Port 1 data register
R/W
XXXXXXXXB
03H
DDR1
Port 1 direction register
W
0 0 0 0 0 0 0 0B
04H
PDR2
Port 2 data register
R/W
0 0 0 0 0 0 0 0B
05H
(Unused area)
06H
07H
SYCC
System clock control register
R/W
X - - MM1 0 0B
08H
STBC
Standby control register
R/W
0 0 0 1 0 - - -B
09H
WDTC
Watchdog control register
R/W
0 - - - XXXXB
0AH
TBTC
Timebase timer control register
R/W
0 0 - - - 0 0 0B
0BH
WPCR
Clock prescaler control register
R/W
0 0 - - - 0 0 0B
0CH
PDR3
Port 3 data register
R/W
- - -XXXXXB
0DH
DDR3
Port 3 direction register
R/W
- - 0 0 0 0 0 0B
0EH
PDR4
Port 4 data register
R/W
- - 1 1 1 1 1 1B
0FH
(Unused area)
10H
IBSR
I2C bus status register
R
0 0 0 0 0 0 0 0B
11H
IBCR
I2C bus control register
R/W
0 0 0 1 1 0 0 0B
ICCR
2
R/W
0 0 0XXXXXB
12H
I C clock control register
2
13H
IADR
I C address register
R/W
- XXXXXXXB
14H
IDAR
I2C data register
R/W
XXXXXXXXB
15H
16H
(Unused area)
17H
18H
T2CR
Timer 2 control register
R/W
X0 - - XXX0B
19H
T1CR
Timer 1 control register
R/W
X0 0 0XXX0B
1AH
T2DR
Timer 2 data register
R/W
XXXXXXXXB
1BH
T1DR
Timer 1 data register
R/W
XXXXXXXXB
1CH
SMR
Serial mode register
R/W
0 0 0 0 0 0 0 0B
1DH
SDR
Serial data register
R/W
XXXXXXXXB
1EH
(Unused area)
1FH
20H
ADC1
A/D control register 1
R/W
0 0 0 0 0 0 - 0B
21H
ADC2
A/D control register 2
R/W
- 0 0 0 0 0 0 1B
22H
ADDH
A/D data register H
R/W
- - - - - - XXB
(Continued)
24
MB89960 Series
(Continued)
Address
Abbreviation
Register Name
Read/Write
Initial Value
23H
ADDL
A/D data register L
R/W
XXXXXXXXB
24H
EIC1
External interrupt 1 control register 1
R/W
0 0 0 0 0 0 0 0B
25H
EIC2
External interrupt 1 control register 2
R/W
- - - - 0 0 0 0B
26H to 27H
(Unused area)
28H
PURR1
Pull-up resistor register 1
(MB89965, P965A, and F969A only)
R/W
1 1 1 1 1 1 1 1B
29H
PURR2
Pull-up resistor register 2
(MB89965, P965A, and F969A only)
R/W
1 1 1 1 1 1 1 1B
2AH
PURR3
Pull-up resistor register 3
(MB89965, P965A, nd F969A only)
R/W
XXX1 1 1 1 1B
2BH
PURR4
Pull-up resistor register 4
(MB89965, P965A, and F969A only)
R/W
XXXX1 1 1 1B
2CH to 31H
(Unused area)
32H
EIE2
External interrupt 2 control register
R/W
0 0 0 0 0 0 0 0B
33H
EIF2
External interrupt 2 flag register
R/W
- - - - - - - 0B
34H to 7BH
(Unused area)
7CH
ILR1
Interrupt level setting register 1
W
1 1 1 1 1 1 1 1B
7DH
ILR2
Interrupt level setting register 2
W
1 1 1 1 1 1 1 1B
7EH
ILR3
Interrupt level setting register 3
W
1 1 1 1 1 1 1 1B
7FH
ITR
Interrupt test register
Not available
XXXXXX0 0B
• Read/write notation
R/W : Reading and writing available
R
: Read-only
W
: Write-only
• Initial value notation
0
: Initial value of bit is “0”.
1
: Initial value of bit is “1”.
X
: Initial value of bit is undefined.
M
: Initial value of bit is specified by mask option.
: Bit is not used.
Note : Do not use the “unused areas”.
25
MB89960 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Power supply voltage
(AVSS = VSS = 0.0 V)
Symbol
Rating
Min.
Max.
VCC
AVCC
VSS − 0.3
VSS + 6.0
AVR
VSS − 0.3
VSS + 6.0
VSS − 0.3
VCC + 0.3
VSS − 0.3
VSS + 6.0
VSS − 0.3
VCC + 0.3
VSS − 0.3
VSS + 6.0
Unit
V
V
Input voltage
VI
Output voltage
VO
“L” level maximum
output current
IOL
15
mA
“L” level average
output current
IOLAV
4
mA
“L” level total maximum
output current
ΣIOL
100
mA
ΣIOLAV
40
mA
IOH
−15
mA
“H” level average
output current
IOHAV
−4
mA
“H” level total maximum
output current
ΣIOH
−50
mA
ΣIOHAV
−20
mA
300
450
“L” level total average
output current
“H” level maximum
output current
“H” level total average
output current
V
Power consumption
PD
Operating temperature
TA
−40
+85
°C
Tstg
−55
+150
°C
Storage temperature
mW
Remarks
*
Pins other than P44 and P55
Pins P44 and P45
Pins other than P44 and P55
Pins P44 and P45
Average value (operating current × operating ratio)
Average value (operating current × operating ratio)
Average value (operating current × operating ratio)
Average value (operating current × operating ratio)
MB89F969A only
* : Set AVCC to the same potential as VCC.
Also ensure that AVCC does not exceed VCC at power on.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
26
MB89960 Series
2. Recommended Operating Conditions
Parameter
Value
Symbol
VCC
AVCC
Power supply voltage
Unit
Remarks
5.5*
V
Normal operation guaranteed range
(MB89965/P965A/F969A)
3.0
5.5
V
To maintain RAM state in stop mode
(MB89965/P965A/F969A)
2.7*
5.5*
V
Normal operation guaranteed range
(MB89PV960)
1.5
5.5
V
To maintain RAM state in stop mode
(MB89PV960)
3.5
AVCC
V
−40
+85
°C
Min.
Max.
3.5*
AVR
Operating temperature
(AVSS = VSS = 0.0 V)
TA
* : Differs depending on the operating frequency and analog guaranteed range. See the figure below and
“5. Electrical Characteristics for the A/D Converter”.
Operating Voltage − Operating frequency
Analog accuracy guaranteed range : VCC = AVCC = 3.5 V to 5.5 V
6
Operating Voltage (V)
5
Operation guaranteed range
4
3.5
3
2.7
: MB89PV960
2
: MB89965, MB89P965A, and MB89F969A
1
2
3
4
5
6
7
8
9
10
Operating Frequency (MHz)
The figure above shows the frequency of the external oscillator when the instruction cycle setting is 4/FC. As the
operating voltage depends on the instruction cycle, change to the new instruction cycle value if using the gear
function to change the operating speed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
27
MB89960 Series
3. DC Characteristics
Parameter
Symbol
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Pin Name
Condition
Max.
Unit
Remarks
0.7 VCC
VCC + 0.3
V
VIHS
RST, INT20 to
INT27, INT10 to
INT12, SI, SCK,
EC, TEST
0.8 VCC
VCC + 0.3
V
VIHM
MOD0/1/2
VCC − 0.3
VCC + 0.3
V
MOD pin
input
VSS + 1.4
VSS + 5.5
V
When SMB
selected
0.7 VCC
VSS + 5.5
V
When I2C
selected
SCL, SDA
VIHI2C
VIL
P00 to P07,
P10 to P17,
P30 to P34
VSS − 0.3
0.3 VCC
V
VILS
RST, INT20 to
INT27, INT10 to
INT12, SI, SCK,
EC, TEST
VSS − 0.3
0.2 VCC
V
VILM
MOD0/1/2
VSS − 0.3
VSS + 0.3
V
MOD pin
input
VSS − 0.3
VSS + 0.6
V
When SMB
selected
VSS − 0.3
0.3 VCC
V
When I2C
selected
“L” level input
voltage
VILSMB
SCL, SDA
VILI2C
“L” level output
voltage
Typ.
P00 to P07,
P10 to P17,
P30 to P34
VIHSMB
“H” level output
voltage
Min.
VIH
“H” level input
voltage
Voltage applied to
open drain output
pins
Value
VD
P40 to P45
VSS − 0.3
VCC + 0.3
V
VOH
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P34
IOH = −2.0 mA
4.0
V
VOL
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P34,
P40 to P45, RST
IOL = 4.0 mA
0.4
V
(Continued)
28
MB89960 Series
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Input leak
current
Symbol
ILI
Pin Name
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P34,
P40 to P45
Condition
Pull-up
resistance
Typ.
Max.
−5
+5
−10
+10
Unit
Remarks
µA
Without pullup resistor
option
ILIOD
P40 to P45
0 V < VI < VSS + 5.5 V
+5
µA
RPULL
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P34,
P40 to P45,
RST
VI = 0.0 V
25
50
100
Ω
10
20
4
7
5
8
MB89F969A
3
8
MB89PV960
1
3
mA MB89965
MB89P965A
MB89F969A
3
8
MB89PV960
2
4
mA MB89965
MB89P965A
MB89F969A
FCH = 10.0 MHz
tINST*2 = 0.4 µs
main run mode
ICC1
Power supply
current*1
Min.
0 V < VI < VCC
MOD0/1/2,
TEST
Open-drain
output leak
current
Value
ICC2
ICCS1
VCC
(when using
an external
clock)
FCH = 10.0 MHz
tINST*2 = 6.4 µs
main run mode
FCH = 10.0 MHz
tINST*2 = 0.4 µs
main sleep mode
With pull-up
resistor
option
MB89PV960
mA
MB89965
MB89P965A
(Continued)
29
MB89960 Series
(Continued)
Parameter
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Symbol
Pin Name
ICCLS
VCC
(when using
an external
clock)
ICCT
ICCH
Input
capacitance
CIN
Except AVCC,
AVSS, VCC,
and AVSS
Max.
1
3
mA
70
150
20
100
µA
0.3
1
mA
FCH = 32.768 kHz
sub sleep mode
10
50
µA
FCH = 32.768 kHz
• clock mode, main stop
mode
5
15
µA
1
10
TA = +25 °C
• sub stop mode
5
10
f = 1 MHz
10
*1 : The power supply current values are for an external clock.
*2 : See “ (4) Instruction Cycle” in “4. AC Characteristics”.
30
Unit
Typ.
FCH = 32.768 kHz
sub run mode
ICCL
Value
Min.
FCH = 10.0 MHz
tINST*2 = 6.4 µs
main sleep mode
ICCS2
Power supply
current*1
Condition
Remarks
MB89PV960
MB89965
MB89P965A
MB89F969A
MB89PV960
µA
pF
MB89965
MB89P965A
MB89F969A
MB89960 Series
4. AC Characteristics
(1) Reset Timing
Parameter
RST “L” pulse width
(VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Symbol
Condition
tZLZH
Value
Min.
Max.
48 tHCYL*
Unit
Remarks
ns
* : tHCYL is the period (1/FC) of the oscillation input to X0.
tZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-On Reset
(AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Condition
Power supply rising time
tR
Power supply cutoff time
tOFF
Value
Unit
Min.
Max.
0.5
50
ms
1
ns
Remarks
For repeated operation
Note : Ensure that the power supply rising time is less than the selected oscillation stabilization delay time.
For example, if the main clock frequency FC = 10 MHz and 214/FC is selected as the oscillation stabilization
delay time, the resulting oscillation stabilization delay time is 1.6 ms. As rapid changes in the power supply
voltage may cause a power-on reset, if you need to change the power supply voltage while the device is
operating, ensure that the power supply voltage changes smoothly.
tR
tOFF
2.0 V
VCC
0.2 V
0.2 V
0.2 V
31
MB89960 Series
(3) Clock Timings
(AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Value
Symbol Pin Name
Clock frequency
Clock cycle time
Input clock pulse width
Input clock rising/falling time
Min.
Typ.
Max.
Remarks
FCH
X0, X1
1
10
MHz
Main clock
FCL
X0A, X1A
32.768
kHz
Sub clock
tHCYL
X0, X1
100
1000
ns
Main clock
tLCYL
X0A, X1A
30.5
µs
Sub clock
PWH
PWL
X0
20
ns
External clock
PWHL
PWLL
X0A
15.2
µs
External clock
tCR
tCF
X0
10
ns
External clock
• X0 and X1 clock timing and input conditions
tHCYL
PWH
tCR
PWL
tCF
X0
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
• Clock configurations
When using
a crystal oscillator
or ceramic oscillator
X0
X1
C1
When using
an external clock
X0
FCH
32
Unit
C2
X1
Open circuit
FCH
MB89960 Series
• X0A and X1A clock timing conditions
tLCYL
PWHL
PWLL
tCR
X0A
tCF
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
• Sub clock configuration
When using
a crystal oscillator
or ceramic oscillator
X0A
When using
an external clock
X1A
X0A
Open circuit
FCL
C1
FCL
C2
(4) Instruction Cycle
Parameter
Instruction cycle
(Minimum instruction
execution time)
X1A
(AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Symbol
Value
Unit
4/FCH, 8/FCH, 16/FCH, 64/FCH
µs
tINST
2/FCL
Remarks
FCH = 10 MHz (4/FCH) operation
time
tINST = 0.4 µs
FCL = 32.768 kHz operation
time
tINST = 61.036 µs
33
MB89960 Series
(5) Serial I/O Timings
(VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Symbol
Pin Name
Serial clock cycle time
tSCYC
SCK
SCK ↓ → SO delay time
tSLOV
SCK, SO
Valid SI → SCK ↑
tIVSH
SCK, SI
SCK ↑ → valid SI hold time
tSHIX
Serial clock “H” pulse width
Parameter
Value
Condition
Max.
2 tINST*
µs
−200
200
ns
200
ns
SCK, SI
200
ns
tSHSL
SCK
tINST*
µs
Serial clock “L” pulse width
tSLSH
SCK
tINST*
µs
SCK ↓ → SO delay time
tSLOV
SCK, SO
0
200
ns
Valid SI → SCK
tIVSH
SCK, SI
200
µs
SCK ↑ → valid SI hold time
tSHIX
SCK, SI
200
µs
Internal
clock
operation
External
clock
operation
* : See “ (4) Instruction cycle” for a definition of tINST.
• Internal shift clock mode
tSCYC
0.8 VCC
SCK
0.2 VCC
0.2 VCC
tSLOV
0.8 VCC
SO
0.2 VCC
tIVSH
tSHIX
0.8 VCC 0.8 VCC
SI
0.2 VCC 0.2 VCC
• External shift clock mode
tSLSH
tSHSL
0.8 VCC
SCK
0.2 VCC
0.2 VCC
tSLOV
SO
0.8 VCC
0.2 VCC
tIVSH
SI
tSHIX
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
34
Unit
Min.
0.8 VCC
Remarks
MB89960 Series
(6) Peripheral Input Timings
(VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Pin Name
Peripheral input “H” pulse width
tILIH
Peripheral input “L” pulse width
tIHIL
INT10 to INT12,
INT20 to INT27, EC
Value
Unit
Min.
Max.
2 tINST*
µs
2 tINST*
µs
Remarks
* : See “ (4) Instruction cycle” for a definition of tINST.
tILIH
INT10 ∼ INT12,
INT20 ∼ INT27, EC
tIHIL
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
35
MB89960 Series
j
(7) I2C Timings
(VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Sym
bol
Pin
Start condition
output
tSTA
SCL
SDA
Stop condition
output
tSTO
SCL 1/4tINST*1 × (m*2 × n*3 + 8)
SDA
− 20
Start condition
detect
tSTA
SCL
SDA
Stop condition
detect
tSTO
SCL
SDA
Parameter
Unit
Remarks
1/4tINST*1 × m*2 × n*3 + 20
ns
Master mode
1/4tINST*1 × (m*2 × n*3 + 8) +
20
ns
Master mode
1/4tINST*1 × 6 + 40
ns
1/4tINST*1 × 6 + 40
ns
1/4tINST*1 × (m*2 × n*3 + 8) +
20
ns
1/4tINST*1 × 4+40
ns
1/4tINST*1 × m*2 × n*3 − 20
1/4tINST*1 × m*2 × n*3 + 20
Min.
Max.
1/4tINST*1 × m* × n*3 − 20
Restart condition outSCL 1/4tINST*1 × (m*2 × n*3 + 8)
tSTASU
put
SDA
− 20
Restart condition deSCL
tSTASU
tect
SDA
SCL output “L” width
tLOW
SCL
* × (m* × n* + 8)
− 20
INST 1
1/4t
2
3
* × (m* × n* + 8) +
20
INST 1
1/4t
2
Master mode
ns
Master mode
SCL
SDA output delay
SDA
1/4tINST*1 × 4 − 20
1/4tINST*1 × 4 + 20
ns
SDA output setup
time after interrupt
tDOSU SDA
1/4tINST*1 × 4 − 20
ns
SCL input “L” pulse
width
tLOW
SCL
1/4tINST*1 × 6 + 40
ns
SCL input “H” pulse
width
tHIGH
SCL
1/4tINST*1 × 2 + 40
ns
SDA input setup time
tSU
SDA
40
ns
SDA hold time
tHO
SDA
0
ns
*1: See “ (4) Instruction cycle” for a definition of tINST.
*2: m is the value set in the ICCR : CS4 and CS3 bits (bits 4 to 3) .
*3: n is the value set in the ICCR : CS2 to CS0 bits (bits 2 to 0) .
• Data transmit (master/slave)
tDO
tDO
tSU
SDA
tLOW
SCL
tDOSU
tHO
1
9
• Data receive (master/slave)
tSU
tDO
tHO
SDA
tDO
tDOSU
ACK
tHIGH
SCL
tHO
ACK
tSTASU tSTA
36
ns
3
SCL output “H” width tHIGH
tDO
6
7
tLOW
tSTO
8
9
Master mode
MB89960 Series
5. Electrical Characteristics for the A/D Converter
(AVcc = 3.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Sym
Pin
bol
Condition
Resolution
Total error
Non-linearity error
Differential
linearity error
AVR = AVCC
Zero transition voltage VOT
Full-scale transition
voltage
Variation between
channels
A/D mode conversion
time*2
VFST
A/D sampling time
Analog input current
IAIN
Analog input voltage
range
VAIN
IA
Power supply current
IAH
Reference voltage
Reference voltage
supply current
IR
IRH
AN0
to
AN3
A/D operation
AVCC TA = + 25 °C
A/D stop
AVR A/D operation
A/D stop
Value
Unit
Remarks
Min.
Typ.
Max.
10
bit
−5.0
+5.0
LSB
−2.5
+2.5
LSB
−1.9
+1.9
LSB
AVR − 3.5
LSB
AVR + 0.5
LSB
AVR + 4.5
LSB
mV
VCC − 6.5
LSB
VCC − 1.5
LSB
VCC + 1.5
LSB
mV
4
LSB
60 tINST*1
µs
MB89965
MB89P965A
MB89F969A
38 tINST*1
µs
MB89PV960
INST 1
µs
16 t
*
10
µA
AVSS
AVR
V
1.5
3
mA
1
5
µA
AVSS + 3.5
AVCC
V
400
µA
5
µA
*1 : See “ (4) Instruction cycle” for a definition of tINST.
*2 : Includes sampling time.
37
MB89960 Series
6. A/D Converter Glossary
• Resolution
The change in analog voltage that can be recognized by the A/D converter.
• Linearity error (unit : LSB)
The deviation between the actual conversion characteristics and the line linking the zero transition point (“00
0000 0000B” ←→ “00 0000 0001B”) and the full scale transition point (“11 1111 1110B” ←→ “11 1111 1111B”) .
• Differential linearity error (unit : LSB)
The variation from the ideal input voltage required to change the output code by 1 LSB.
• Total error (unit : LSB)
The total error is the difference between the actual value and the theoretical value.
Total Error
Theoretical I/O Characteristics
3FFH
VFST
3FFH
3FEH
1.5 LSB
3FDH
004H
003H
3FDH
Digital output
Digital Output
3FEH
VOT
{1 LSB × N + 0.5 LSB}
004H
VNT
Actual conversion
characteristic
003H
1 LSB
002H
Actual conversion
characteristic
002H
001H
001H
Theoretical characteristic
0.5 LSB
AVSS
AVR
1 LSB =
38
VFST − VOT
1022
AVSS
AVR
Analog input
Analog Input
(V)
Total error for digital output N =
VNT − {1 LSB × N + 0.5 LSB}
1 LSB
MB89960 Series
Full Scale Transition Error
Zero Transition Error
Theoretical characteristic
004H
3FFH
003H
002H
Actual conversion
characteristic
Digital Output
Digital Output
Actual conversion
characteristic
Actual conversion
characteristic
3FEH
VFST
(Actual
measured value)
3FDH
001H
Actual conversion
characteristic
3FCH
VOT
(Actual measured value)
AVR
AVSS
Analog Input
Analog Input
Linearity Error
3FFH
Actual conversion
characteristic
Theoretical characteristic
N+1
{1 LSB × N + VOT}
3FDH
VFST
(Actual
measured
VNT value)
Actual conversion
characteristic
004H
003H
002H
001H
Digital output
Digital output
3FEH
Differential Linearity Error
Actual conversion
characteristic
V (N + 1) T
N
N−1
Theoretical characteristic
N−2
VNT
Actual conversion
characteristic
VOT (Actual measured value)
AVSS
AVR
Analog input
Linearity error of digital output N =
AVSS
AVR
Analog Input
VNT − {1 LSB × N + VOT}
1 LSB
Differential linearity error of digital output N =
V (N + 1) T − VNT
1 LSB
−1
39
MB89960 Series
7. Notes for A/D Conversion
• Analog input pins and input impedance
The A/D converter incorporates a sample & hold circuit as shown below. When an A/D conversion starts, the
voltage at the analog input pin is captured by the sample & hold capacitor for a period of 16 instruction cycles.
Accordingly, if the output impedance of the external circuit connected to the analog input is high, the analog
input voltage may not stabilize within the period of the analog input sampling time. Therefore, ensure that the
output impedance of the external circuit is sufficiently low (10 kΩ or less) . If it is not possible to reduce the output
impedance of the external circuit, connecting an external capacitor of approximately 0.1 µF is recommended.
Equivalent circuit of analog input
MB89960 series
Sample & hold circuit
R
AN0 to AN3
Comparator
controller
C
Closed for approximately 16 instruction cycles
after initiating A/D conversion.
MB89965
MB89P965A
MB89F969A
R = 3.2 kΩ, C = 30 pF approx
MB89PV960
R = 1.4 kΩ, C = 64 pF approx.
Analog channel selector
• Error
The relative error increases as |AVR − AVSS| becomes smaller.
40
MB89960 Series
8. Electrical Characteristics of Flash Memory
• Programming and erasing characteristics
Parameter
Power supply current*1
Sector erasing
time
Programming
time
Fixed time
per sector
regardless of
size
per byte
Successful
completion
time
Unsuccessful completion time
Successful
completion
time
Unsuccessful completion time
Sym
Pin
bol Name
Condition
IFWE
VCC = 5.0 V
VCC
Value
Min. Typ. Max.
Unit Remarks
40
mA
1
15
s
*2
8
3600
µs
650 3600
µs
*1 : Automatic algorithm executing
*2 : If a fault occurs during sector erasing, detection via DQ5 may not be available (DQ5 = 1 may not occur) .
Accordingly, a fault must be assumed after 15 s, even if DQ5 does not go to “1”.
41
MB89960 Series
■ MASK OPTIONS
Part No.
MB89965
MB89P965A/
MB89F969A
MB89PV960
Specifying procedure
Specify when
ordering mask
Not available
Not available
Initial value* selection for main
clock oscillation stabilization
delay time (FCH = 10 MHz)
• 01 : 212/FCH (0.4 ms approx.)
• 10 : 216/FCH (6.6 ms approx.)
• 11 : 218/FCH (26.2 ms approx.)
Selectable
218/FCH
(26.2 ms approx.)
218/FCH
(26.2 ms approx.)
NO
1
FCH : Frequency of main clock oscillation
* : This specifies the initial value after a reset of the oscillation stabilization delay time setting bits in the system
clock control register (SYCC : WT1, WT0)
■ ORDERING INFOMATION
Part Number
Package
Remarks
MB89965PFV1
MB89P965APFV1
MB89965CPFV1
Plastic LQFP, 48-pin
(FPT-48P-M05)
The MB89965PFV1 does not have an I2C
function.
MB89965PFM
MB89P965APFM
MB89965CPFM
Plastic QFP, 48-pin
(FPT-48P-M13)
The MB89965PFM does not have an I2C
function.
MB89965PF
MB89P965APF
MB89965CPF
Plastic QFP, 48-pin
(FPT-48P-M16)
The MB89965PF does not have an I2C
function.
MB89F969APFM
Plastic LQFP, 64-pin
(FPT-64P-M09)
MB89PV960CF
42
Ceramic MQFP, 48-pin
(MQP-48C-P01)
MB89960 Series
■ PACKAGE DIMENSIONS
(These package dimensions are provisional. Please obtain the actual dimensions of the final product separately.)
Plastic LQFP, 48-pin
Note : The pin width and thickness includes plating.
(FPT-48P-M05)
9.00±0.20(.354±.008)SQ
7.00±0.10(.276±.004)SQ
36
0.145±0.055
(.006±.002)
25
24
37
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
.059 –.004
INDEX
13
48
"A"
0°~8°
LEAD No.
1
0.50(.020)
C
(Mounting height)
0.10±0.10
(.004±.004)
(Stand off)
12
0.20±0.05
(.008±.002)
0.08(.003)
M
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
2000 FUJITSU LIMITED F48013S-c-4-8
Dimensions in mm (inches).
43
MB89960 Series
Plastic QFP, 48-pin
(FPT-48P-M13)
13.10±0.40 SQ
(.516±.016)
10.00±0.20 SQ
(.394±.008)
36
2.35(.093)MAX
(Mounting height)
0(0)MIN
(STAND OFF)
25
37
Details of "A" part
24
0.15(.006)
8.80
(.346)
REF
INDEX
11.50±0.30
(.453±.012)
0.20(.008)
0.18(.007)MAX
0.53(.021)MAX
"A"
48
13
Details of "B" part
LEAD No.
1
0.80(.0315)TYP
12
0.30±0.10
(.012±.004)
0.16(.006)
M
0.15±0.05
(.006±.002)
0~10°
"B"
0.80±0.30
(.031±.012)
0.10(.004)
C
2000 FUJITSU LIMITED F48023S-1C-2
Dimensions in mm (inches).
44
MB89960 Series
Plastic QFP, 48-pin
(FPT-48P-M16)
17.20±0.40 SQ
(.677±.016)
+0.30
12.00 –0.10 SQ
2.70(.106)MAX
(Mounting height)
0.05(.002)MIN
(STAND OFF)
+.012
36
.472 –.004
25
37
Details of "A" part
24
0.15(.006)
8.80
(.346)
REF
13.60±0.40
(.535±.016)
0.20(.008)
0.15(.006)MAX
INDEX
0.50(.020)MAX
48
13
"A"
Details of "B" part
LEAD No.
1
0.80(.0315)TYP
12
+0.05
0.15 –0.01
0.30±0.06
(.012±.002)
0.16(.006)
"B"
+.002
M
.006 –.0004
0~10°
1.80±0.30
(.071±.012)
0.15(.006)
C
2000 FUJITSU LIMITED F48026S-1C-2
Dimensions in mm (inches).
45
MB89960 Series
Ceramic MQFP, 48-pin
(MQP-48C-P01)
17.20(.677)TYP
PIN No.1 INDEX
15.00±0.25
(.591±.010)
14.82±0.35
(.583±.014)
1.50(.059)TYP
8.80(.346)REF
1.00(.040)TYP
0.80±0.22
(.0315±.0087)
PIN No.1 INDEX
1.02±0.13
(.040±.005)
+0.13
10.92 –0.0
+.005
.430 –0
7.14(.281) 8.71(.343)
TYP
TYP
PAD No.1 INDEX
0.30(.012)TYP
+0.45
4.50(.177)TYP
1.10 –0.25
+.018
.043 –.010
0.40±0.08
(.016±.003)
0.60(.024)TYP
8.50(.335)MAX
0.15±0.05
(.006±.002)
C
1994 FUJITSU LIMITED M48001SC-4-2
Dimensions in mm (inches).
46
MB89960 Series
Plastic LQFP, 64-pin
(FPT-64P-M09)
14.00±0.20(.551±.008)SQ
48
33
12.00±0.10(.472±.004)SQ
+0.20
1.50 –0.10
+.008
.059 –.004
49
(Mounting height)
32
9.75
(.384)
REF
13.00
(.512)
NOM
1 PIN INDEX
64
LEAD No.
17
1
0.65(.0256)TYP
Details of "A" part
16
0.30±0.10
(.012±.004)
"A"
0.13(.005)
M
+0.05
0.127 –0.02
0.10±0.10 (STAND OFF)
(.004±.004)
+.002
.005 –.001
0.10(.004)
0
C
10°
0.50±0.20
(.020±.008)
2000 FUJITSU LIMITED F64018S-1C-3
Dimensions in mm (inches).
47
MB89960 Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0104
FUJITSU LIMITED Printed in Japan