Ordering number : EN5680 CMOS IC LC7455A, 7455M Closed Caption Signal Extraction IC Overview Package Dimensions The LC7455A/M extracts the closed caption signal superimposed on a video signal during the vertical return period and, under the control of a clock signal provided by the decoder IC, transfers that signal to the IC (usually a microcontroller) that decodes the closed caption data. The LC7455A/M supports four operating modes. Modes 1 and 2 can be used for XDS. In these modes, the LC7455A/M, in combination with the decoder IC (microcontroller), extracts the caption signal superimposed on field 2 and uses it for NTSC VCR functions such as the automatic time and date setting function. In modes 3 and 4, the LC7455A/M, in combination with the decoder IC (microcontroller), extracts the caption signal superimposed on fields 1 and 2 and uses it for NTSC TV applications (mode 3) or PAL TV applications (mode 4). unit: mm 3006B-DIP16 [LC7455A] SANYO: DIP16 Functions • Low power dissipation achieved by fabrication in a CMOS process. • Stable caption signal extraction achieved by a built-in peak hold circuit and the use of digital technology. • Operating supply voltage: 5 V ±10% • Package LC7455A: 16-pin DIP LC7455M: 18-pin MFP unit: mm 3095-MFP18 [LC7455M] SANYO: MFP18 SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN D3097HA(OT) No. 5680-1/13 LC7455A, 7455M Pin Assignments Top view Pin Functions Pin No. Pin Pin function DIP16 MFP18 Mode 1 Mode2 VSS1 1 1 Ground Mode3 TEST 2 2 Test pin. Must be left open during normal operation. LN21 3 3 Line 21H pulse output (even field) Line 21H pulse output (both fields) O/E/CFOUT 4 4 Field discrimination pulse output Ceramic oscillator output Field discrimination pulse output HS/CFIN 5 5 Sync separator Hsync pulse output Ceramic oscillator input Hsync pulse input CPDT 6 6 Caption data output (n-channel open-drain output) SCKIN 7 7 Caption data transfer clock input CE 8 8 Chip select input VDD1 9 11 Power supply MOD0 10 12 Leave open CVIN 11 13 Composite video input VCOR 12 14 Connection for an external resistor to control the built-in VCO oscillator frequency MOD1 13 15 Leave open VDD2 14 16 Power supply VSS2 15 17 Ground CP 16 18 Connection for the filter used by the built-in PLL Short to the power supply Leave open Mode4 Line 22H pulse output (both fields) Short to the power supply Short to the power supply Note: VDD1 and VSS1 are the power supply for the digital block, and VDD2 and VSS2 are the power supply for the analog block. Use a circuit similar to the one shown below to minimize mutual interference due to noise from these blocks. Power supply No. 5680-2/13 LC7455A, 7455M System Block Diagram Pedestal clamp PLL reference clock mode 2 mode 3, 4 mode 1 Data peak hold (Data slice) Hsync peak hold (Hsync slice) Output control Data output buffer Divided-by32 circuit (Modes 1, 3, 4) Oscillator circuit (Mode 2) (Mode 2) Operation in the Different Modes Pin Mode Application equipment Operation MOD1 MOD0 Open Open Mode 1 VCR · Even field line 21 data extraction The internal PLL is operated with the horizontal synchronizing signal separated from the composite video signal as the reference. Open VDD Mode 2 VCR · Even field line 21 data extraction An external 508 kHz ceramic oscillator is used, and the internal PLL is operated with that oscillator output divided by 32 as the reference. VDD Open Mode 3 NTSC-TV VDD VDD Mode 4 PAL-TV · Odd and even field line 21 data extraction The internal PLL is operated with the Hsync signal applied from fly back as the reference. · Odd and even field line 22 data extraction The internal PLL is operated with the Hsync signal applied from the fly back circuit as the reference. Note: The data extraction operations in modes 1 and 2 are identical. However, while mode 1 can operate without problem for normal "on air" signals, it may be difficult for the PLL to lock with signals such as scrambled CATV signals. No. 5680-3/13 LC7455A, 7455M Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Maximum supply voltage Symbol VDD max Conditions Ratings VDD1, VDD2: VDD1 = VDD2 Unit –0.3 to +7.0 V V Input voltage VI HS/CFIN, CVIN, SCKIN, CE –0.3 to VDD +0.3 Output voltage VO LN21, CPDT, O/E/CFOUT, HS/CFIN –0.3 to VDD +0.3 LC7455A Allowable power dissipation Pd max LC7455M V 300 mW 150 mW Operating temperature Topr –30 to +70 °C Storage temperature Tstg –55 to +150 °C Note: VSS1 and VSS2 must be at the same potential. VDD1 and VDD2 must be at the same potential. Allowable Operating Ranges at Ta = –30 to +70°C, VSS = 0 V Parameter Operating supply voltage Input high-level voltage Input low-level voltage CVIN input amplitude HS input frequency range Symbol Conditions Ratings min typ Unit max VDD VDD1, VDD2 : VDD1 = VDD2 4.5 5.5 V VIH HS/CFIN, SCKIN, CE; VDD = 4.5 to 5.5 V 0.75 VDD VDD V VIL HS/CFIN, SCKIN, CE; VDD = 4.5 to 5.5 V VSS 0.25VDD V V CVIN : SYNC-WHITE = 1.0 V; CVSYNC VDD = 4.5 to 5.5 V fH HS/CFIN : VDD = 4.5 V For mode 3 For mode 4 Oscillator frequency range*1 FmCF HS/CFIN, O/E/CFOUT; For mode 2, see Figure 1. VDD = 4.5 to 5.5 V Oscillator stabilization time*2 tmsCF HS/CFIN, O/E/CFOUT; For mode 2, see Figure 2. VDD = 4.5 to 5.5 V 1Vp-p – 3dB 1Vp-p 1Vp-p + 3 dB 15.23 15.13 15.73 15.63 16.23 16.13 kHz kHz 503 508 513 kHz 0.5 5 ms Note: 1. See Table 1 for more information on the oscillator frequency. 2. The oscillator stabilization time is the time required until the oscillator is stable after the power-supply voltage is applied. See figure 2. Electrical Characteristics at Ta = –30 to +70°C, VSS = 0 V. Parameter Symbol Conditions Input high-level current IIH HS/CFIN, SCKIN, CE : VIN = VDD; VDD = 4.5 to 5.5 V Input low-level current IIL HS/CFIN, SCKIN, CE : VIN = VSS; VDD = 4.5 to 5.5 V Output high-level voltage VOH LN21, O/E/CFOUT, HS/CFIN; IOH = –4 mA ; VDD = 4.5 to 5.5 V Output low-level voltage VOL LN21, CPDT, O/E/CFOUT, HS/CFIN : IOL = 10 mA; VDD = 4.5 to 5.5 V Ratings min typ Unit max 1 µA –1 µA VDD – 1.2 V 1 V Input clamping voltage VCLMP 2.3 2.5 2.7 V Input clamping current IIC CVIN : CVIN = 3 V ; VDD = 5.0 V 5 10 18 µA Output clamping current IOC CVIN : CVIN = 2 V ; VDD = 5.0 V –120 –70 –30 µA Current drain IDD VDD1, VDD2 ; VDD = 4.5 to 5.5 V 6 15 mA CVIN ; VDD = 5.0 V Serial Output Characteristics at Ta = –30 to +70°C, VSS = 0 V, VDD = 4.5 to 5.5 V Parameter Symbol Conditions Ratings min typ max Unit [Serial clock] tCKCY SCKIN : See Figure 3. 1 µs Input clock low-level pulse width Input clock period tCKL SCKIN : See Figure 3. 0.5 µs Input clock high-level pulse width tCKH SCKIN : See Figure 3. 0.5 µs tICK SCKIN : Stipulated with respect to the falling edge of CE. 1 µs tCKO Stipulated with respect to the falling edge of SCKIN. A 1-kΩ external pull-up resistor is connected. See Figure 3. Setup time [Serial output] Output delay time 0.5 µs No. 5680-4/13 LC7455A, 7455M Table 1 Ceramic Oscillator Guaranteed Constants Oscillator type Manufacturer Oscillator element C1 C2 508-kHz ceramic oscillator Murata Mfg. Co., Ltd. CSB 508E 150 pF 150 pF Note: Capacitors with K tolerance (±10%) and SL characteristics must be used for C1 and C2. · Since this circuit is influenced by the length of the circuit pattern, components related to oscillator functioning must be mounted as close together as possible so that pattern lines do not become longer than is absolutely necessary. · The characteristics are not guaranteed if an oscillator element other than the one listed above is used. Figure 1 Ceramic Oscillator Power supply Operating VDD lower limit Figure 2 Oscillator Stabilization Time <AC timing measurement point> <Timing> <Test load> Note: CPDT goes to the high-impedance state while CE is high. Figure 3 Serial Output Test Conditions No. 5680-5/13 O/E and LN21 Output Timing (Modes 1, 2, and 3) Odd field Line no. (modes 1, 3) Even field Line no. (modes 1, 3) This pulse is only output in modes 1, 2, and 3. No. 5680-6/13 Notes: O/E is output in modes 1 and 3. In mode 2 it functions as the ceramic oscillator output pin. LN21 is output for even fields in modes 1 and 2, and for both fields in mode 3. LC7455A, 7455M This pulse is only output in mode 3. O/E and LN21 Output Timing (Mode 4) First field Line no. Line no. LC7455A, 7455M Second field No. 5680-7/13 Caption Data Transfer from the LC7455A/M to the Decoder IC (microcontroller): Method 1 (This is the basic technique.) (Caption data is transferred to the data output buffer.) (The decoder IC (microprocessor) sets CE from high to low after detecting a falling edge on LN21.) High impedance The previous data is output. (Sixteen bits of caption data is output LSB first in synchronization with falling edges on SCKIN.) No. 5680-8/13 Notes: Applications that extract closed caption text data in mode 3 (NTSC TV) or mode 4 (PAL TV) must check the level of the O/E/CFOUT pin when an LN21 falling edge is detected to determine whether odd field or even field data is being acquired. LC7455A, 7455M ) ( In modes 1 and 2, pulses are output on line 21 of even fields. In mode 3, pulses are output on line 21 of both fields. In mode 4, pulses are output on line 22 of both fields. Caption Data Transfer from the LC7455A/M to the Decoder IC (microcontroller): Method 2 (For applications that cannot provide an input port on the decoder IC (microcontroller) to detect LN21 falling edges.) Within a single frame (modes 1 and 2) 16 bits of data all of which are zeros. In modes 1 and 2, since data is output to the output buffer once every frame (in the even field), the decoder IC (microcontroller) must perform a transfer control operation at least twice every frame (about 32 ms). When the second control operation is performed in a given frame, the CPDT output for that second operation will be 16 bits of zeros. This allows the microprocessor to recognize that the data for the next frame has not yet been transferred to the output buffer. Notes: When CE remains low, the hardware will not transfer the data to the output buffer. Thus applications must restore CE from low to high after each data transfer to the decoder IC (microcontroller) operation has completed. This transfer technique (method 2) cannot be used in modes 3 and 4. LC7455A, 7455M 16 bits transfered No. 5680-9/13 LC7455A, 7455M Sample Application Circuits (mode 1) MFP18 DIP16 No. 5680-10/13 LC7455A, 7455M Sample Application Circuits (mode 2) MFP18 DIP16 No. 5680-11/13 LC7455A, 7455M Sample Application Circuits (mode 3) MFP18 Hsync signal DIP16 Hsync signal No. 5680-12/13 LC7455A, 7455M Sample Application Circuits (mode 4) MFP18 Hsync signal DIP16 Hsync signal ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1997. Specifications and information herein are subject to change without notice. No. 5680-13/13