Ordering number : EN5520A CMOS LSI LC74785, LC74785M On-Screen Display Controller LSI Overview Package Dimensions The LC74785 and LC74785M are on-chip EDS CMOS LSIs for on-screen display, a function that displays characters and patterns on a TV screen under microprocessor control. These LSIs support 12 × 18 dot characters and can display 12 lines by 24 characters of text. unit: mm 3067-DIP24S [LC74785] Features • Display format: 24 characters by 12 rows (Up to 288 characters) • Character format: 12 (horizontal) × 18 (vertical) dots • Character sizes: Three sizes each in the horizontal and vertical directions • Characters in font: 128 • Initial display positions: 64 horizontal positions and 64 vertical positions • Blinking: Specifiable in character units • Blinking types: Two periods supported: About 1.0 second and about 0.5 second • Blanking: Over the whole font (12 × 18 dots) • Background color — Background coloring: 8 colors (internal synchronization mode): 4fsc — Background coloring: 6 colors (internal synchronization mode): 2fsc • Line background color — Can be set for 3 lines — Line background coloring: 8 colors (internal synchronization mode): 4fsc — Line background coloring: 6 colors (internal synchronization mode): 2fsc • External control input: 8-bit serial input format • On-chip sync separator circuit • EDS support • Video output — NTSC-format composite output • Package 24-pin plastic DIP (300 mil) 24-pin plastic SOP (375 mil) SANYO: DIP24S unit: mm 3045B-MFP24 [LC74785M] SANYO: MFP24 SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 63097HA (OT) No. 5520-1/24 LC74785, LC74785M Pin Assignment Pin Functions Pin No. Pin Function 1 VSS1 Ground 2 Xtal IN 3 4 5 Notes Ground connection (digital system ground) Crystal oscillator (MUTE input) These pins are used either to connect the crystal and capacitor used to form an external crystal oscillator used to generate the internal synchronizing signals, or to input an external clock signal (2fsc or 4fsc). As a mask option, the Xtalout pin can be set to function as the MUTE input pin. When this pin is set low, the video output is held at the pedestal level. (A pull-up resistor is built in and the input has hysteresis characteristics.) (CHABLK) Crystal oscillator input switching (CHABLK output) Switches the mode between external clock input and crystal oscillator operation. A low level selects crystal oscillator operation and a high level selects external clock input. As a mask option, the CTRL1 input pin can be set to function as the CHABLK (character border) output. This is a 3-value output. LN21 Data output Line 21H pulse output (Even fields when MOD1 is low, both fields when MOD1 is high) LC oscillator Connections for the coil and capacitor that form the character output dot clock generation oscillator. Xtal OUT (MUTE) CTRL1 6 OSC IN 7 OSC OUT Outputs the state of the external synchronizing signal presence/absence judgment. Outputs a high level when synchronizing signals are present. Outputs a field discrimination pulse (O/E pulse) when SEL2 is high.(HLFTON: Valid when 0) HLFTON: A signal in the range specified by LNA*, LNB*, and LNC* is output when HLFTON is high.) Outputs the dot clock (LC oscillator) when CS1 is high and RST is low. (This signal is not output on command resets.) Outputs the crystal oscillator clock when CS1 is low and RST is low. (This signal is not output on command resets.) 8 SYNC JDG External synchronizing signal judgment output 9 CS1 Enable input Enable input pin for the OSD serial data input function. Serial data input is enabled when this pin is low. A pull-up resistor is built in. (The input has hysteresis characteristics.) 10 SCLK Clock input Input for the serial data input clock. A pull-up resistor is built in. (The input has hysteresis characteristics.) 11 SIN Data input Serial data input. A pull-up resistor is built in. (The input has hysteresis characteristics.) 12 VDD2 Power supply 13 CVOUT Video signal output 14 VSS2 Ground Composite video signal level adjustment power supply (analog system power supply) Composite video signal output Ground connection (analog system ground) Continued on next page. No. 5520-2/24 LC74785, LC74785M Continued from preceding page. Pin No. Pin Function 15 CV IN Video signal input Notes Composite video signal input 16 VDD1 Power supply 17 SYNIN Sync separator circuit input 18 CDLR Background color phase adjustment Background color phase adjustment. Connect to ground through a resistor and a capacitor. 19 SEPOUT Composite synchronizing signal output Video signal output for the built-in sync separator circuit. Can be switched to function as an output for signal (high or ST. pulse) due to MOD0 by setting SEL0 high. Vertical synchronizing signal input Inputs the vertical synchronizing signal created by integrating the SEPOUT pin output signal. An integration circuit must be connected to the SEPOUT pin. This pin must be tied to VDD1 if unused. This pin can be switched to function as the frame signal input mode by setting SEL1 high. (This is valid when CTL3 is set to 1.) 20 SEP IN Power supply (+5 V: digital system power supply) Video signal input for the built-in sync separator circuit 21 CS2 Enable input EDS data output enable input. EDS data output is enabled when this pin is low. A pull-up resistor is built in. (The input has hysteresis characteristics.) 22 CPDT Data output EDS data output (This pin can be either an n-channel open-drain output or a CMOS output.) 23 RST Reset input System reset input A pull-up resistor is built in. (The input has hysteresis characteristics.) 24 VDD1 Power supply (+5 V) Power supply (+5 V: digital system power supply) Note: Both VDD1 pins must be connected to the power supply. Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Symbol Conditions Ratings Unit Supply voltage VDD VDD1 and VDD2 VSS–0.3 to VSS+7.0 V Input voltage VIN All input pins VSS–0.3 to VDD+0.3 V LN21, CPDT, SEPOUT, and SYNCJDG VSS–0.3 to VDD+0.3 Output voltage VOUT Allowable power dissipation Pd max Ta = 25°C V 350 mW Operating temperature Topr –30 to +70 °C Storage temperature Tstg –40 to +125 °C Allowable Operating Ranges at Ta = –30 to +70°C Parameter Supply voltage Input high-level voltage Input low-level voltage Pull-up resistance Composite video signal input voltage Input voltage Oscillator frequency Symbol Conditions Ratings min typ Unit max VDD1 VDD1 4.5 5.0 5.5 V VDD2 VDD2 4.5 5.0 1.27VDD1 V VIH1 RST, CS1, CS2, SIN, SCLK, SEPIN, and MUTE 0.8VDD1 VDD1 + 0.3 V VIH2 CTRL1 0.7VDD1 VDD1 + 0.3 V VIL1 RST, CS1, CS2, SIN, SCLK, SEPIN, and MUTE VSS – 0.3 0.2VDD1 V VIL2 CTRL1 VSS – 0.3 0.3VDD1 V RPU Applies to pins set for the RST, CS1, CS2, SIN, SCLK, and MUTE pin options. VIN1 CVIN; VDD1 = 5 V VIN2 SYNIN; VDD1 = 5 V VIN3 XtalIN (When external clock input is used) fin = 2 fsc or 4 fsc ; VDD1 = 5 V 25 50 90 2.0 1.5 2.0 0.10 kΩ Vp-p 2.5 Vp-p 5.0 Vp-p FOSC1 The XtalIN and XtalOUT oscillator pins (2 fsc: NTSC) 7.159 MHz FOSC1 The XtalIN and XtalOUT oscillator pins (4 fsc: NTSC) 14.318 MHz FOSC2 The OSCIN and OSCOUT oscillator pins (LC oscillator) 5 10 MHz Note: When the XtalIN pin is used in clock input mode, extreme care must be taken to prevent noise from entering the input signal. No. 5520-3/24 LC74785, LC74785M Electrical Characteristics at Ta = –30 to +70°C, VDD1 = 5 V unless otherwise specified. Parameter Symbol Ratings Conditions min typ Unit max Input off leakage current Ileak1 CVIN 1 µA Output off leakage current Ileak2 CVOUT 1 µA Output high-level voltage VOH1 LN21, SYNCJDG, CPDT, and SEPOUT; VDD1 = 4.5 V, IOH = –1.0 mA Output low-level voltage VOL1 LN21, SYNCJDG, CPDT, and SEPOUT; VDD1 = 4.5 V, IOL = 1.0 mA CHABLK; VDD1 = 5.0 V Three-value output voltage Input current Operating mode current drain VO 3.5 V 1.0 V H 3.3 5.0 V M 1.8 2.3 V L 0 0.8 V 1 µA IIH RST, CS1, CS2, SIN, SCLK, CTRL1, SEPIN, and MUTE; VIN = VDD1 IIL CTRL1 and OSCIN; VIN = VSS1 IDD1 VDD1; All outputs open, Xtal: 7.159 MHz, LC: 8 MHz IDD2 VDD2: VDD2 = 5 V –1 µA 30 mA 20 mA SYNC level VSN CVOUT; VDD1 = 5.0 V, VDD2 = 5.0 V *1 *2 *3 Pedestal level VPD CVOUT; VDD1 = 5.0 V, VDD2 = 5.0 V *1 *2 *3 1.32 1.52 1.81 1.44 1.64 1.93 1.56 1.76 2.05 V V V Color burst low level VCBL CVOUT; VDD1 = 5.0 V, VDD2 = 5.0 V *1 *2 *3 0.98 1.17 1.46 1.10 1.29 1.58 1.22 1.41 1.70 V V V Color burst high level VCBH CVOUT; VDD1 = 5.0 V, VDD2 = 5.0 V *1 *2 *3 1.63 1.83 2.11 1.75 1.95 2.23 1.87 2.07 2.35 V V V Background color other than blue low level VRSL0 CVOUT; VDD1 = 5.0 V, VDD2 = 5.0 V *1 *2 *3 1.17 1.36 1.65 1.29 1.48 1.77 1.41 1.60 1.89 V V V Background color other than blue high level VRSH0 CVOUT; VDD1 = 5.0 V, VDD2 = 5.0 V *1 *2 *3 2.33 2.52 2.81 2.45 2.64 2.93 2.57 2.76 3.05 V V V Blue background color 1low level VRSL1 CVOUT; VDD1 = 5.0 V, VDD2 = 5.0 V *1 *2 *3 1.08 1.27 1.56 1.20 1.39 1.68 1.32 1.51 1.80 V V V Blue background color 2 low level VRSL2 CVOUT; VDD1 = 5.0 V, VDD2 = 5.0 V *1 *2 *3 1.49 1.68 1.97 1.61 1.80 2.09 1.83 1.92 2.21 V V V Blue background color 1, 2 high level VRSH1 VRSH2 CVOUT; VDD1 = 5.0 V, VDD2 = 5.0 V *1 *2 *3 1.97 2.17 2.46 2.09 2.29 2.58 2.21 2.41 2.70 V V V Frame level 0 VBK0 CVOUT; VDD1 = 5.0 V, VDD2 = 5.0 V *1 *2 *3 1.40 1.60 1.89 1.52 1.72 2.01 1.64 1.84 2.13 V V V Frame level 1 VBK1 CVOUT; VDD1 = 5.0 V, VDD2 = 5.0 V *1 *2 *3 1.97 2.17 2.46 2.09 2.29 2.58 2.21 2.41 2.70 V V V Character level VCHA CVOUT; VDD1 = 5.0 V, VDD2 = 5.0 V *1 *2 *3 2.55 2.75 3.04 2.67 2.87 3.16 2.79 2.99 3.28 V V V Note: 1. 2. 3. 0.70 0.89 1.18 0.82 1.01 1.30 0.94 1.13 1.42 V V V When the sync level is 0.8 V When the sync level is 1.0 V When the sync level is 1.3 V No. 5520-4/24 LC74785, LC74785M Timing Characteristics at Ta = –30 to +70°C, VDD1 = 5 ±0.5 V OSD write (See Figure 1.) Parameter Minimum input pulse width Data setup time Data hold time One word write time Symbol Ratings Conditions min tW(SCLK) SCLK tW(CS1) CS1 (The period when CS1 is high) tSU(CS1) tSU(SIN) typ max Unit 200 ns 1 µs CS1 200 ns SIN 200 ns th(CS1) CS1 2 µs th(SIN) SIN 200 ns tword The time to write 8 bits of data 4.2 µs 1 µs The RAM data write time twt EDS read (For the n-channel open-drain circuit, see Figure 2.) Parameter Symbol Ratings Conditions min typ max Unit tCKCY SCLK 2 µs tCKL SCLK 1 µs tCKH SCLK 1 µs Setup time tICK SCLK 10 µs Output delay time tCKO CPDT Minimum input pulse width 0.5 µs Note: The CMOS output circuit follows the OSD timing. First byte Second byte Figure 1 OSD Serial Data Input Timing Note: CPDT goes to the high-impedance state when CS2 is high. Figure 2 EDS Serial Output Test Conditions (For the n-channel open-drain circuit.) No. 5520-5/24 (Line number) (Line number) Note: The O/E signal is output from the SYNCJDG pin when SEL2 is high. LN21 is output for even fields when MOD1 is low and for both fields when MOD1 is high. Even field Odd field Pulse output when MOD1 is low or high Pulse output when MOD1 is high LC74785, LC74785M Figure 3 O/E and LN21 Output Timing No. 5520-6/24 The previous data is output. The 16 bits of caption data is output LSB first in synchronization with SCLK falling edges. High-impedance Note: When extracting closed caption character data when MOD1 is high (NTSC-TV), applications must determine whether the current field is odd or even by checking the signal level output from the SYNCJDG pin (with SEL2 set high) when a falling edge is detected on LN21. High-impedance CS2 is switched from high to low after the decoder LSI (microcontroller) detects a falling edge on LN21. Caption data is transferred to the data output buffer. A pulse is output at line 21 in even fields when MOD1 is low. A pulse is output at line 21 in both fields when MOD1 is High. LC74785, LC74785M Figure 4 Transferring caption data from the LC74785/M to the decoder LSI (microcontroller): Method 1 (Basic LC74785/M usage) No. 5520-7/24 LC74785, LC74785M The timing of the transfer of caption data to the data output buffer is synchronized with the falling edge of the pulse output from LN21. Therefore, the software processing shown below is required if the decoder LSI (microcontroller) does not detect LN21 falling edges. Activity within a given frame (MOD1: low) Transfer of 16 data bits Data in which all 16 bits are zero Figure 5 Transferring caption data from the LC74785/M to the decoder LSI (microcontroller): Method 2 (When it is not possible to allocate a port on the decoder LSI (microcontroller) to detect falling edges on LN21.) Since data is output to the output buffer once (during the even field) when MOD1 is low, the data transfer control operation from the decoder LSI (microcontroller) must be performed at least twice in a single frame (about 32 ms). If a transfer control operation is performed twice in the same frame, the CPDT output on the second operation will be 16 bits of zero data. This allows the decoder LSI to determine that the data for the next frame has not been transferred yet. Note: If CS2 remains low, the hardware will not be able to transfer the data to the output buffer. Therefore, the decoder LSI (microcontroller) must reset CS2 to high from low after it completes a data transfer control operation. Transfer method 2 cannot be used if MOD1 is high (NTSC-TV). No. 5520-8/24 Pedestal clamp Data peak hold (data slice) Data output buffer 8-bit latch + command decode Character output dot clock generator HSYNC peak hold (HSYNC slice) Data slicer Output control Serial to parallel converter Composite sync signal separation control Synchronization determination Vertical size counter Vertical character size register Timing generator Horizontal size counter Horizontal character size register Vertical display position detector Line control counter Horizontal display position detector Character control counter Synchronizing signal generator Vertical dot counter Vertical display position register Horizontal dot counter Horizontal display position detector Display control register Character output control Background control Video output control Blinking and reverse video control circuit Blinking and reverse video control register RAM write address counter Shift register Font ROM Decoder Display RAM LC74785, LC74785M System Block Diagram Decoder No. 5520-9/24 LC74785, LC74785M Display Control Commands Display control commands have an 8-bit format and are transferred using the serial input function. Commands consist of a command identification code in the first byte and command data in the following bytes. The following commands are supported. 1 COMMAND0: 2 COMMAND1: 3 COMMAND2: 4 COMMAND3: 5 COMMAND4: 6 COMMAND5: 7 COMMAND6: 8 COMMAND7: 9 COMMAND8: 10 COMMAND9: 11 COMMAND10: Display memory (VRAM) write address setup command Display character data write command Vertical display start position and vertical character size setup command Horizontal display start position and horizontal character size setup command Display control setup command Display control setup command Synchronizing signal detection setup command Display control setup command Display control setup command Display control setup command Display control setup command Display Control Command Table First byte Command Second byte Command identification code Data Data 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 COMMAND0 Write address setup 1 0 0 0 V3 V2 V1 V0 0 0 0 H4 H3 H2 H1 H0 COMMAND1 Character write 1 0 0 1 0 0 0 0 at c6 c5 c4 c3 c2 c1 c0 COMMAND2 Vertical character size and vertical display start position 1 0 1 0 VS 21 VS 20 VS 11 VS 10 0 FS VP 5 VP 4 VP 3 VP 2 VP 1 VP 0 COMMAND3 Horizontal character size and horizontal display start position 1 0 1 1 HS 21 HS 20 HS 11 HS 10 0 LC HP 5 HP 4 HP 3 HP 2 HP 1 HP 0 COMMAND4 Display control 1 1 0 0 OSC STP SYS RST 0 BLK 2 BLK 1 BLK 0 BK 1 BK 0 RV DSP ON COMMAND5 Display control 1 1 0 1 0 HLF TON NON INT 0 0 0 BCL CB PH 2 PH 1 PH 0 COMMAND6 Synchronizing signal detection 1 1 1 0 SEL 0 MOD 0 DIS LIN MUT 0 RN 2 RN 1 RN 0 SN 3 SN 2 SN 1 SN 0 COMMAND7 Display control 1 1 1 1 0 0 SEL 1 CTL 3 0 0 0 VNP SEL VSP SEL MSK ERS MSK SEL EGL COMMAND8 Display control 1 1 1 1 0 1 SEL 2 MOD 1 0 LNA 3 LNA 2 LNA 1 LNA 0 LPA 2 LPA 1 LPA 0 COMMAND9 Display control 1 1 1 1 1 0 LNB SEL MOD 2 0 LNB 3 LNB 2 LNB 1 LNB 0 LPB 2 LPB 1 LPB 0 COMMAND10 Display control 1 1 1 1 1 1 LNC SEL MOD 3 0 LNC 3 LNC 2 LNC 1 LNC 0 LPC 2 LPC 1 LPC 0 TST RAM MOD ERS Once written, the command identification code in the first byte is stored until the next first byte is written. However, when the display character data write command (COMMAND1) is written, the LC74785/M locks into the display character data write mode, and another first byte cannot be written. When the CS1 pin is set high, the LC74785/M is set to the COMMAND0 (display memory write address setup mode) state. No. 5520-10/24 LC74785, LC74785M COMMAND0 (Display memory write address setup command) First byte Contents DA 0 to 7 Register 7 — 1 6 — 0 5 — 0 4 — 0 3 V3 2 V2 1 V1 0 V0 State Function Notes Command 0 identification code Sets the display memory write address. 0 1 0 1 Display memory line address (0 to B hexadecimal) 0 1 0 1 Second byte Contents DA 0 to 7 Register 7 — 0 6 — 0 5 — 0 4 H4 3 H3 2 H2 1 H1 0 H0 State Function Notes Second byte identification code 0 1 0 1 0 1 Display memory column address (0 to 17 hexadecimal) 0 1 0 1 Note: All registers are set to 0 when the LC74785/M is reset by the RST pin. COMMAND1 (Display character data write setup command) First byte Contents DA 0 to 7 Register 7 — 1 6 — 0 5 — 0 4 — 1 3 — 0 2 — 0 1 — 0 0 — 0 State Function Command 1 identification code Sets up display character data write mode. Notes When this command is input, the LC74785/M locks in the display character data write mode until the CS1 pin goes high. No. 5520-11/24 LC74785, LC74785M Second byte DA 0 to 7 Register 7 at 6 c6 5 c5 4 c4 3 c3 2 c2 1 c1 0 c0 Contents State Notes Function 0 Character attribute off 1 Character attribute on 0 1 0 1 0 1 0 Character code (00 to 7F hexadecimal) 1 0 1 0 1 0 1 Note: All registers are set to 0 when the LC74785/M is reset by the RST pin. COMMAND2 Vertical display start position and vertical character size setup command First byte Contents DA 0 to 7 Register 7 — 1 6 — 0 5 — 1 4 — 3 2 1 0 VS21 VS20 VS11 VS10 State Notes Function Command 2 identification code Sets the vertical display start position and the vertical character size 0 0 VS20 0 1 0 0 1H/dot 2H/dot 1 1 3H/dot 1H/dot 1 VS21 0 VS10 0 1 0 0 1H/dot 2H/dot 1 1 3H/dot 1H/dot 1 VS11 Second line vertical character size First line vertical character size Second byte DA 0 to 7 Register 7 — 6 5 4 FS VP5 (MSB) VP4 3 VP3 2 VP2 1 0 VP1 VP0 (LSB) Contents State 0 Second byte identification bit 0 Crystal oscillator frequency: 2fsc 1 Crystal oscillator frequency: 4fsc 0 If VS is the vertical display start position then: 5 VS = H × (2 Σ 2n VPn) n=0 H: the horizontal synchronization pulse period 1 0 1 Notes Function 0 The vertical display start position is set by the 6 bits VP0 to VP5. The weight of bit 1 is 2H. 1 0 1 0 1 0 Character display area 1 Note: All registers are set to 0 when the LC74785/M is reset by the RST pin. No. 5520-12/24 LC74785, LC74785M COMMAND3 (Horizontal display start position and horizontal size setup command) First byte Contents DA 0 to 7 Register 7 — 1 6 — 0 5 — 1 4 — 1 3 HS21 2 HS20 1 HS11 0 HS10 State Notes Function Command 3 identification code Sets the horizontal display start position and the horizontal character size. 0 HS20 0 1 0 0 1Tc/dot 2Tc/dot 1 1 3Tc/dot 1Tc/dot 1 HS21 0 HS10 0 1 0 0 1Tc/dot 2Tc/dot 1 1 3Tc/dot 1Tc/dot 1 HS11 Second line horizontal character size First line horizontal character size Second byte DA 0 to 7 Register 7 — 6 LC 5 HP5 (MSB) 4 HP4 3 HP3 2 HP2 1 HP1 0 HP0 (LSB) Contents State Function 0 Second byte identification bit 0 Use the LC oscillator for the dot clock 1 Use the crystal oscillator for the dot clock 0 If HS is the horizontal start position then: 5 HS = Tc × (2 Σ 2n HPn) n=0 Tc: Period of the oscillator connected to OSCIN/OSCOUT in operating mode. 1 0 1 0 1 0 Notes Selects the dot clock used for character display in the horizontal direction. The horizontal display start position is set by the 6 bits HP0 to HP5. The weight of bit 1 is 2Tc. 1 0 1 0 1 Note: All registers are set to 0 when the LC74785/M is reset by the RST pin. No. 5520-13/24 LC74785, LC74785M COMMAND4 (Display control setup command) First byte Contents DA 0 to 7 Register 7 — 1 6 — 1 5 — 0 4 — 0 3 TSTMOD 2 RAMERS 1 OSCSTP 0 SYSRST State Notes Function Command 4 identification code Display control setup 0 Normal operating mode 1 Test mode This bit must be set to 0. 0 Erasing RAM takes about 500 µs. (This operation must be executed in the DSPOFF state.) 1 Erase display RAM. (Set the RAM data to 7F hexadecimal.) 0 Do not stop the crystal and LC oscillators. 1 Stop the crystal and LC oscillators. Valid in external synchronization mode when character display is off. Reset all registers and turn display off. The registers are reset when the CS1 pin is low, and the reset state is cleared when CS1 is set high, 0 1 Second byte DA 0 to 7 Register 7 — 6 BLK2 5 BLK1 4 BLK0 3 BK1 2 1 0 BK0 RV DSPON Contents State Notes Function 0 Second byte identification bit 0 Character display area 1 Video display area Specifies the size for complete fill in 0 BLK0 0 1 0 0 Blanking off Character size 1 1 Border size Full character size BLK1 1 0 Changes the blanking size Blinking period: About 0.5 s 1 Blinking period: About 1.0 s 0 Blinking off 1 Blinking on 0 Reverse (character reversing) off 1 Reverse (character reversing) on 0 Character display off 1 Character display on Switches the blinking period Blinking in reverse video mode switches the display between normal character display and reverse video display. Note: All registers are set to 0 when the LC74785/M is reset by the RST pin. No. 5520-14/24 LC74785, LC74785M COMMAND5 (Display control setup command) First byte Contents DA 0 to 7 Register 7 — 1 6 — 1 5 — 0 4 — 1 3 — 0 2 HLFTON 1 NON 0 INT State Notes Function Command 5 identification code Display control setup 0 External synchronizing signal judgment output signal 1 A signal in the range specified by LNA*, LNB*, and LNC* is output. 0 Interlaced 1 Noninterlaced 0 External synchronization 1 Internal synchronization Switches the SYNCJDG (pin 8) output. Switches between interlaced and noninterlaced video. Switches between external and internal synchronization Second byte Contents DA 0 to 7 Register 7 — 0 6 — 0 5 — 4 BCL 3 CB 2 PH2 State 0 Background coloring on 1 No background coloring (Only the background level is set) 0 Color burst signal output. 1 Color burst signal output stopped. 1 0 PH1 1 0 0 Second byte identification bit 0 0 1 Notes Function PH0 1 Only valid in internal synchronization mode. Only valid when BCL is high. PH2 PH1 PH0 0 0 0 Background color (phase) Cyan 0 0 1 Yellow * 0 1 0 Red * * 0 1 1 Blue 1 0 0 Cyan - blue 1 0 1 Green 1 1 0 Orange 1 1 1 Magenta * Background color specification * * *: When 2 fsc is used. Note: All registers are set to 0 when the LC74785/M is reset by the RST pin. No. 5520-15/24 LC74785, LC74785M COMMAND6 (Synchronizing signal detection setup command) First byte Contents DA 0 to 7 Register 7 — 1 6 — 1 5 — 1 4 — 3 SEL0 2 MOD0 1 DISLIN 0 MUT State Notes Function Command 6 identification code Sets up synchronizing signal control. 0 0 Sync separator signal 1 Output signal set by MOD0 0 High-level output 1 ST pulse signal 0 12 lines 1 10 lines 0 Normal output 1 CVIN is cut and CVOUT is held at the pedestal level. Switches the SEPOUT (pin 19) output. Only valid when SEL0 is high. Switches the number of lines displayed. CVOUT switching Second byte DA 0 to 7 Register 7 — 6 5 4 3 2 RN2 RN1 RN0 SN3 SN2 1 SN1 0 SN0 Contents State 0 0 1 0 1 0 1 Notes Function Second byte identification bit RN2 RN1 RN0 Number of times HSYNC detected 0 0 0 0 times 0 0 1 4 times 0 1 0 8 times 1 0 0 16 times External synchronizing signal detection control Signal absent → signal present transition detection Sets the sampling period in which SYNC can be detected continuously in the horizontal synchronizing signal period (1H). 0 1 SN3 SN2 SN1 SN0 Number of times HSYNC detected 0 0 0 0 0 Not detected 32 times 1 0 0 0 1 0 0 0 1 0 64 times 1 0 1 0 0 128 times 0 1 0 0 0 256 times External synchronizing signal detection control Signal present → signal absent transition detection Sets the sampling period in which SYNC cannot be detected continuously in the horizontal synchronizing signal period (1H). 1 Note: All registers are set to 0 when the LC74785/M is reset by the RST pin. No. 5520-16/24 LC74785, LC74785M COMMAND7 (Display control setup command) First byte Contents DA 0 to 7 Register 7 — 1 6 — 1 5 — 1 4 — 1 3 — 0 2 — 0 1 SEL1 0 CTL3 State Function Notes Command 7 identification code Display control setup Extended command 0 identification code 0 Vertical synchronizing signal (external V separation) input 1 Frame signal input 0 Use internal V separation. 1 Do not use internal V separation. Switches the SEPIN (pin 20) input. Only valid when CTL3 is high. Switches V separation. Second byte Contents DA 0 to 7 Register 7 — 0 6 — 0 5 — 4 VNPSEL 3 VSPSEL 2 MSKERS 1 MSKSEL 0 EGL State Function Notes Second byte identification bit 0 0 V falling edge detection 1 V rising edge detection 0 VSEP: about 8.9 µs 1 VSEP: about 17.8 µs 0 Mask valid 1 Mask invalid 0 3H 1 20H 0 Border level 0 only (VBK0) 1 Two-stage border level (VBK0 and VBK1) Switches the V acquisition polarity in external mode when internal V separation is used. Switches the internal V separation period. Clears the HSYNC and VSYNK masks. Switches the VSYNC mask. Switches the border level. (Only valid when BLK0 is 0 and BLK1 is 1.) Note: All registers are set to 0 when the LC74785/M is reset by the RST pin. No. 5520-17/24 LC74785, LC74785M COMMAND8 (Display control setup command) First byte Contents DA 0 to 7 Register 7 — 1 6 — 1 5 — 1 4 — 1 3 — 0 2 — 1 1 SEL2 0 MOD1 State Notes Function Command 8 identification code Display control setup Extended command 1 identification code 0 External synchronizing signal judgment output signal 1 O/E signal 0 Even field line 21 data extraction (VCR) 1 Line 21 data extraction on both odd and even fields (NTSC-TV) Switches the SYNCJDG (pin 8) output Valid when HLFTON is low. Switches line 21 data extraction. Second byte DA 0 to 7 Register 7 — 6 LNA3 Contents State 0 0 1 0 5 LNA2 1 0 4 LNA1 1 0 3 LNA0 Notes Function Second byte identification bit LNA3 LNA2 LNA1 LNA0 Specified line 0 0 0 0 Do not change the line background 0 0 0 1 Line 1 0 0 1 0 Line 2 0 0 1 1 Line 3 0 1 0 0 Line 4 0 1 0 1 Line 5 0 1 1 0 Line 6 0 1 1 1 Line 7 1 0 0 0 Line 8 1 0 0 1 Line 9 1 0 1 0 Line 10 1 0 1 1 Line 11 1 1 — — Line 12 Specifies the line whose background is to be changed (If the same line is specified to have different background colors with LNA*, LNB*, and LNC*, then the setting specified by the last command issued will be valid. The previously specification registers (LN* and LP*) will all be reset to 0.) 1 0 2 LPA2 1 0 1 LPA1 1 0 0 LPA0 1 LPA2 LPA1 LPA0 0 0 0 Background color (phase) Cyan 0 0 1 Yellow * 0 1 0 Red * * 0 1 1 Blue 1 0 0 Cyan - blue 1 0 1 Green 1 1 0 Orange 1 1 1 Magenta * Specifies the background color. * * *: When 2 fsc is used. Note: All registers are set to 0 when the LC74785/M is reset by the RST pin. No. 5520-18/24 LC74785, LC74785M COMMAND9 (Display control setup command) First byte Contents DA 0 to 7 Register 7 — 1 6 — 1 5 — 1 4 — 1 3 — 1 2 — 0 1 LNBSEL 0 MOD2 State Notes Function Command 9 identification code Display control setup Extended command 2 identification code 0 Normal line background color operation 1 RV characters have the background color specified by PH* or the RV character background color is white. 0 LNBSEL: 1 setting specification 1 RV characters have the background color specified by PH*, characters are white. Switches the RV mode background color for the line specified by LNB* for characters specified for RV display. Valid when LNBSEL is high Second byte DA 0 to 7 Register 7 — 6 LNB3 Contents State 0 0 1 0 5 LNB2 1 0 4 LNB1 1 0 3 LNB0 Notes Function Second byte identification bit LNB3 LNB2 LNB1 LNB0 Specified line 0 0 0 0 Do not change the line background 0 0 0 1 Line 1 0 0 1 0 Line 2 0 0 1 1 Line 3 0 1 0 0 Line 4 0 1 0 1 Line 5 0 1 1 0 Line 6 0 1 1 1 Line 7 1 0 0 0 Line 8 1 0 0 1 Line 9 1 0 1 0 Line 10 1 0 1 1 Line 11 1 1 — — Line 12 Specifies the line whose background is to be changed (If the same line is specified to have different background colors with LNA*, LNB*, and LNC*, then the setting specified by the last command issued will be valid. The previously specification registers (LN* and LP*) will all be reset to 0.) 1 0 2 LPB2 1 0 1 LPB1 1 0 0 LPB0 1 LPB2 LPB1 LPB0 0 0 0 Background color (phase) Cyan 0 0 1 Yellow * 0 1 0 Red * * 0 1 1 Blue 1 0 0 Cyan - blue 1 0 1 Green 1 1 0 Orange 1 1 1 Magenta * Specifies the background color. * * *: When 2 fsc is used. Note: All registers are set to 0 when the LC74785/M is reset by the RST pin. No. 5520-19/24 LC74785, LC74785M COMMAND10 (Display control setup command) First byte Contents DA 0 to 7 Register 7 — 1 6 — 1 5 — 1 4 — 1 3 — 1 2 — 0 1 LNCSEL 0 MOD3 State Notes Function Command 10 identification code Display control setup Extended command 2 identification code 0 Normal line background color operation 1 RV characters have the background color specified by PH* or the RV character background color is white. 0 LNCSEL: 1 setting specification 1 RV characters have the background color specified by PH*, characters are white. Switches the RV mode background color for the line specified by LNC* for characters specified for RV display. Valid when LNCSEL is high Second byte DA 0 to 7 Register 7 — 6 LNC3 Contents State 0 0 1 0 5 LNC2 1 0 4 LNC1 1 0 3 LNC0 Notes Function Second byte identification bit LNC3 LNC2 LNC1 LNC0 Specified line 0 0 0 0 Do not change the line background 0 0 0 1 Line 1 0 0 1 0 Line 2 0 0 1 1 Line 3 0 1 0 0 Line 4 0 1 0 1 Line 5 0 1 1 0 Line 6 0 1 1 1 Line 7 1 0 0 0 Line 8 1 0 0 1 Line 9 1 0 1 0 Line 10 1 0 1 1 Line 11 1 1 — — Line 12 Specifies the line whose background is to be changed. (If the same line is specified to have different background colors with LNA*, LNB*, and LNC*, then the setting specified by the last command issued will be valid. The previously specification registers (LN* and LP*) will all be reset to 0.) 1 0 2 LPC2 1 0 1 LPC1 1 0 0 LPC0 1 LPC2 LPC1 LPC0 0 0 0 Background color (phase) Cyan 0 0 1 Yellow * 0 1 0 Red * * 0 1 1 Blue 1 0 0 Cyan - blue 1 0 1 Green 1 1 0 Orange 1 1 1 Magenta * Specifies the background color. * * *: When 2 fsc is used. Note: All registers are set to 0 when the LC74785/M is reset by the RST pin. No. 5520-20/24 LC74785, LC74785M Display Screen Structure The display consists of 12 lines of 24 characters. Up to 288 characters can be displayed. The number of characters that can be displayed is reduced when enlarged characters are displayed. Display memory addresses are specified as row (0 to 11 decimal) and column (0 to 23 decimal) addresses. Display Screen Structure (display memory addresses) 24 Characters 12 Rows No. 5520-21/24 LC74785, LC74785M Composite Video Signal Output Levels (internally generated levels) CVOUT output level waveform (VDD2 = 5.00 V) Output level Output voltage (1) [V] Output voltage (2) [V] Output voltage (3) [V] Character 2.67 2.87 3.16 VRSH0: High for background colors other than blue 2.45 2.64 2.93 VRSH1,2 High for blue background colors 1 and 2 2.09 2.29 2.58 VBK1: Border 1 2.09 2.29 2.58 VCBH: High for the color burst signal 1.75 1.95 2.23 1.61 1.80 2.09 VCHA: VRSL2: Low for blue background color 2 VBK0: Border 0 1.52 1.72 2.01 VPD: Pedestal level 1.44 1.64 1.93 1.29 1.48 1.77 VRSL0: Low for background colors other than blue VRSL1 Low for blue background color 1 1.20 1.39 1.68 VCBL: Low for the color burst signal 1.10 1.29 1.58 VSN: Sync 0.82 1.01 1.30 Note: VDD2 = 5.0 V. No. 5520-22/24 LC74785, LC74785M Sample Application Circuit (When the LC74785/M is used in conjunction with a single-chip Y/C circuit.) Microprocessor External system clock input Microprocessor Crystal oscillator Microprocessor External system clock input (when the pin 3 and 4 functions are modified by mask options) Note: When a sync tip level of 1.3 V DC (CVIN input signal: sync tip = 1.3 V) is selected for the internal generated video signals by option settings, the electrolytic capacitor connected to SYNIN must be connected with the correct polarity. When VDD1 is 5.0 V, the SYNIN input video signal pedestal level is clamped at about 2.5 V DC. No. 5520-23/24 LC74785, LC74785M ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of June, 1997. Specifications and information herein are subject to change without notice. No. 5520-24/24