Ordering number : ENN*6526 CMOS IC LC74731W,74732W On-Screen Display Controller Preliminary Package Dimensions [LC74731W,74732W] 12.0 10.0 1.25 0.5 0.18 1.25 0.15 33 48 49 32 1.25 1 1.7max 17 64 16 0.1 • Text structure: 12 lines × 24 characters (Up to 288 characters) • Character format: 16 × 16 dots Character display clock frequency: about 9 MHz • Character sizes: Four sizes each in the horizontal and vertical directions with the size set in line units. • Number of characters supported: LC74731W:256 (internal) LC74732W:512 (internal) Up to 8192 using an external ROM (for Japanese) [Reference] JIS X0298 (1990): 6877 characters JIS level 1 kanji: 2965 characters JIS level 2 kanji: 3388 characters Special characters: 524 characters • Display start positions: 128 positions each in the horizontal and vertical directions • Blinking, reverse video, reversed blinking, and character outlining: May be specified in individual character units. • Blinking types: Two types with periods of about 1.0 and about 0.5 seconds. • Blanking: The whole font area (16 ×16 dots) can be blanked in line units (Four types: no blanking, character size blanking, character plus outlining size blanking, and whole area up to adjacent character blanking) • Line spacing control: Zero to seven scan lines, in line units 0.5 Features 1.25 The LC74731W and LC74732W are on-screen display CMOS ICs that display characters and patterns on a TV screen under the control of a microcontroller. These ICs display 16 × 16-dot characters and up to 12 lines of text with 24 characters per line. • Character color: Eight colors in character units (in internal synchronization mode): 2 fsc and 4 fsc (Black, red, green, yellow, blue, magenta, cyan, and white) • Character background color: Eight colors (in internal synchronization mode): 2 fsc and 4 fsc (Black, red, green, yellow, blue, magenta, cyan, and transparent) • Screen background color: Eight colors (in internal synchronization mode): 2 fsc and 4 fsc (Black, red, green, yellow, blue, magenta, cyan, and white) • External control inputs: Serial interface with an 8-bit data size. • Built-in sync separator circuit • Video outputs: NTSC, PAL, PALM, PALN, NTSC 4.43, and PAL 60 composite video signal outputs • Supports Y/C input 12.0 10.0 Overview 0.5 0.5 SANYO: SQFP64 Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 63000RM (OT) No. 6526-1/38 LC74731W,74732W D0 D1 D2 D3 D4 D5 D6 D7 CE OE A0 A1 A2 A3 A4 A5 Pin Assignment 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VSS1 1 48 A6 XTALin 2 47 A7 XTALout 3 46 A8 CTRL1 4 45 A9 OSCin 5 44 A10 OSCout 6 43 A11 MUTE 7 42 A12 CDLR 8 41 A13 SYNCjdg/Rout 9 40 A14 CHARA/Gout 10 39 A15 BLANK/Bout 11 38 A16 IEOUT/BLKout 12 37 A17 OUTMOD 13 36 VDD1 CS 14 35 RST SIN 15 34 SEPin SCLK 16 33 SEPout (V) SYNin (H) HFTin CVcr CVin -NC- CVout VSS2 Yin -NC- Yout -NC- Cbias Cin -NC- Cout VDD2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 No. 6526-2/38 LC74731W,74732W Pin Functions Pin No. Pin 1 VSS1 2 Xtalin 3 Xtalout 4 CTRL1 5 OSCin 6 OSCout Function Description Ground Ground connection. (Digital system ground) Crystal oscillator connections Connections for the crystal element and capacitors that form the internal sync signal generating crystal oscillator. Xtalin can also be used to input an external clock signal. (2fsc or 4fsc) Switches the crystal oscillator Selects external clock input mode or crystal oscillator mode. Low: crystal oscillator mode, high: input external clock input mode. LC oscillator connections Connections for the coil and capacitor that form the character output dot clock generation oscillator. 7 MUTE Muting control input This is an active-low input with hysteresis characteristics (MORE+). When low, the CVout, Yout, and Cout outputs are set to either, (1) CSYNC, CSYNC, PE, or (2) PE PE, PE. In the initial state, (1) is selected. This setting is switched by commands. 8 CDLR Background color phase adjustment Connection for the resistor used to adjust the background color phase 9 SYNCJDG /Rout 10 CHARA/Gout Character output (Gout output) Character signal output 11 BLANK/Bout Blank output (Bout output) Blank signal output pin 12 Internal/external output IEout/BLKout (BLKout output) Outputs the result of the judgment as to whether or not the external sync signal is present. External sync signal judgment A high level is output when a sync signal is present. output (Rout output) The dot clock (LC oscillator) is output when RST is low. (The IC can be set up to not output this signal during resets by commands.) Internal synchronization (high)/external synchronization (low) state output pin Output switching input Switches between output from pins 9 to 12 and input to pin 32. Low: normal operation, high: RGB output supported CS Enable input Serial data input enable Serial data input is enabled when low. more+ (Hysteresis input characteristics) 15 SIN Data input Serial data input more+ (Hysteresis input characteristics) 16 SCLK Clock input Serial data input clock input more+ (Hysteresis input characteristics) 17 VDD2 Power supply Composite video signal level adjustment power supply. (Analog system power supply) 18 COUT Color signal output 19 NC 13 OUTMOD 14 20 CIN 21 CBIAS 22 NC 23 YOUT 24 NC 25 YIN 26 VSS2 27 CVOUT 28 NC Color (C) signal output This pin must either be left open or connected to ground. Color signal input Color (C) signal input Chrominance bias output Chrominance signal bias level output This pin must be either left open or connected to ground. Luminance signal output Luminance signal (Y) output This pin must be either left open or connected to ground. Luminance signal input Luminance signal (Y) input Ground Ground Video signal output Composite video signal output This pin must either be left open or connected to ground. 29 CVIN Video signal input Composite video signal input 30 CVCR Video signal input SECAM chrominance signal input 31 HFTin Halftone signal input Halftone signal input 32 SYNin Sync separator circuit input Video signal input to the internal sync separator circuit 33 SEPout Composite sync signal output Composite sync signal output from the internal sync separator circuit 34 SEPin 35 36 Vertical sync signal input Vertical sync signal input MORE+ (Hysteresis input characteristics) RST Reset input System reset input A built-in pull-up resistor can be included in this pin’s input circuit. (Hysteresis input characteristics) VDD1 Power supply (+5 V) Power supply (+5 V: digital system power supply) Continued on next page. No. 6526-3/38 LC74731W,74732W Continued from preceding page. Pin No. Pin Function 37 A17 Address output 17 ROM address output 17 Description 38 A16 Address output 16 ROM address output 16 39 A15 Address output 15 ROM address output 15 40 A14 Address output 14 ROM address output 14 41 A13 Address output 13 ROM address output 13 42 A12 Address output 12 ROM address output 12 43 A11 Address output 11 ROM address output 11 44 A10 Address output 10 ROM address output 10 45 A9 Address output 9 ROM address output 9 46 A8 Address output 8 ROM address output 8 47 A7 Address output 7 ROM address output 7 48 A6 Address output 6 ROM address output 6 49 A5 Address output 5 ROM address output 5 50 A4 Address output 4 ROM address output 4 51 A3 Address output 3 ROM address output 3 52 A2 Address output 2 ROM address output 2 53 A1 Address output 1 ROM address output 1 54 A0 Address output 0 ROM address output 0 55 OE Output enable ROM output enable output. This is an active-low output. 56 CE Chip enable ROM chip enable output. This is an active-low output. 57 D7 Data input 7 ROM data input 7. MORE+ (Hysteresis input characteristics) 58 D6 Data input 6 ROM data input 6. MORE+ (Hysteresis input characteristics) 59 D5 Data input 5 ROM data input 5. MORE+ (Hysteresis input characteristics) 60 D4 Data input 4 ROM data input 4. MORE+ (Hysteresis input characteristics) 61 D3 Data input 3 ROM data input 3. MORE+ (Hysteresis input characteristics) 62 D2 Data input 2 ROM data input 2. MORE+ (Hysteresis input characteristics) 63 D1 Data input 1 ROM data input 1. MORE+ (Hysteresis input characteristics) 64 D0 Data input 0 ROM data input 0. MORE+ (Hysteresis input characteristics) No. 6526-4/38 LC74731W,74732W Specifications Maximum Ratings at Ta = 25°C Parameter Symbol Ratings Conditions min Unit max Supply voltage VDD VDD1 and VDD2 VSS – 0.3 VSS + 6.5 V Input voltage VIN All input pins VSS – 0.3 VDD1 + 0.3 V SYNCJDG, BLANK, CHARA, SEPOUT, A0 to A17, CE, and OE VSS – 0.3 VDD1 + 0.3 V Output voltage Allowable power dissipation VOUT — 275 mW Operating temperature Pdmax Topr –30 +70 °C Storage temperature Tstg –40 +125 °C Recommended Operating Conditions Parameter Supply voltage Supply voltage [Only for RGB output] High-level input voltage Symbol Ratings Conditions min typ Unit max VDD1 VDD1 4.5 5.0 5.5 V VDD2 VDD2 4.5 5.0 6.5 V VDD1 VDD1 2.7 5.0 5.5 V VDD2 VDD2 2.7 5.0 6.5 V VIH1 CS, SIN, SCLK, SEPIN, and MUTE 0.8 VDD1 — 5.5 V VIH2 RST 0.8 VDD1 — VDD1 + 0.3 V VIH3 CTRL1 and OUTMOD 0.7 VDD1 — VDD1 + 0.3 V VIH4 D0 to D7 0.8 VDD1 — 5.5 V VIL1 RST, CS, SIN, SCLK, SEPIN, and MUTE VSS – 0.3 — 0.2 VDD1 V VIL2 CTRL1 and OUTMOD VSS – 0.3 — 0.3 VDD1 V VIL3 D0 to D7 VSS – 0.3 — 0.2 VDD1 V Pull-up resistor RPU RST, CS, SIN, SCLK, and MUTE (when the pull-up resistor option is specified) 25 50 90 kΩ Composite video signal input voltage VIN1 CVIN and CVCR VDD1 = 5 V — 2.0 — Vp-p VIN2 SYNIN VDD1 = 5 V 1.5 2.0 2.5 Vp-p VIN3 XtalIN (when an external clock input is used) fin = 2 fsc, 4 fsc VDD1 = 5 V — — 5.0 Vp-p Low-level input voltage Input voltage Oscillator frequency FOSC1 FOSC2 The XtalIN and XtalOUT oscillator pins (2 fsc: NTSC) 7.159 The XtalIN and XtalOUT oscillator pins (4 fsc: NTSC) 14.318 MHz MHz The XtalIN and XtalOUT oscillator pins (2 fsc: PAL) — 8.867 — MHz The XtalIN and XtalOUT oscillator pins (4 fsc: PAL) — 17.734 — MHz The OSCin and OSCout oscillator pins (LC oscillator) — 10 — MHz Note: If the Xtalin pin is used in clock input mode, applications must take adequate input noise prevention and reduction measures. No. 6526-5/38 LC74731W,74732W Electrical Characteristics at Ta = –30 to +70°C, VDD1 = 5 V unless otherwise specified. Parameter Symbol Pin Conditions Ratings min typ Unit max Input off leakage current Ileak1 CVIN, CVCR, CIN, and YIN — — 1 µA Output off leakage current Ileak2 CVOUT, COUT, and YOUT — — 1 µA VOH11 SYNCJDG, SETPOUT, BLANK, CHARA, and IEOUT VDD1 = 5.5 to 4.5 V IOH = –1.0 mA 0.9 VDD1 — — V VOH12 SYNCJDG, SETPOUT, BLANK, CHARA, and IEOUT VDD1 = 4.4 to 2.7 V IOH = –0.5 mA 0.9 VDD1 — — V VOH21 A0 to A17, OE, and CE VDD1 = 5.5 to 4.5 V IOH = –1.0 mA 0.9 VDD1 — — V VOH22 A0 to A17, OE, and CE VDD1 = 4.4 to 2.7 V IOH = –0.5 mA 0.9 VDD1 — — V VOL11 SYNCJDG, SEPOUT, BLANK, CHARA, and IEOUT VDD1 = 5.5 to 4.5 V IOL = 1.0 mA — — 0.1 VDD1 V VOL12 SYNCJDG, SEPOUT, BLANK, CHARA, and IEOUT VDD1 = 4.4 to 2.7 V IOL = 0.5 mA — — 0.1 VDD1 V VOL21 A0 to A17, OE, and CE VDD1 = 5.5 to 4.5 V IOL = 1.0 mA — — 0.1 VDD1 V VOL22 A0 to A17, OE, and CE VDD1 = 4.4 to 2.7 V IOL = 0.5 mA — — 0.1 VDD1 V IIH RST, CS, SIN, SCLK, CTRL1, MUTE, and OUTMOD VIN = VDD1 — — 1 µA IIL CS, SIN, SCLK, CTRL1, and OUTMOD VIN = VSS1 –1 — — µA IDD1 VDD1 All outputs: open Xtal: 17.734 MHz LC: 10 MHz — — 40 mA IDD2 VDD2 VDD2 = 5 V 20 mA High-level output voltage Low-level output voltage Input current Operating current drain Continued on next page. No. 6526-6/38 LC74731W,74732W Continued from preceding page. Parameter SYNC level Pedestal level Color burst low level Color burst high level Background color 1 low level Background color 1 high level Background color 2 low level Background color 2 high level Outlining level 1 Outlining level 2 Outlining level 3 Character level 1 Character level 3 Symbol Pin VSN VPD VCBL VCBH VRSL1 VRSH1 VRSL2 VRSH2 VBK1 VBK2 VBK3 VCHA1 VCHA3 Ratings Conditions min typ (1) 0.80 (2) 1.00 (3) 1.40 (1) 1.37 (2) 1.57 (3) 1.97 (1) 1.07 (2) 1.27 (3) 1.67 (1) 1.67 (2) 1.87 (3) 1.27 CVOUT (1) 1.23 (1): When SYNC – LEVEL = 0.8 V VDD1 = 5.0 V (2) 1.43 (2): When SYNC – LEVEL = 1.0 V VDD2 = 5.0 V (3) 1.83 (3): When SYNC – LEVEL = 1.4 V (1) 2.37 (2) 2.57 (3) 2.97 (1) 1.52 (2) 1.72 (3) 2.12 (1) 2.01 (2) 2.21 (3) 2.61 (1) 1.50 (2) 1.70 (3) 2.10 (1) 1.80 (2) 2.00 (3) 2.40 (1) 2.08 (2) 2.28 (3) 2.68 (1) 2.65 (2) 2.85 (3) 3.25 (1) 2.23 (2) 2.43 (3) 2.83 max Unit V V V V V V V V V V V V V No. 6526-7/38 LC74731W,74732W OSD Write (See figure 1.) at Ta = –30 to +70°C, VDD1 = 5 ± 0.5 V Parameter Symbol tw (sclk) Minimum input pulse width Data setup time Ratings Conditions min SCLK typ max Unit 200 — — 1 — — µs CS 200 — — ns tsu (sin) SIN 200 — — ns th (cs) CS 2 — — µs SIN 200 — — ns The time to write 8 bits of data 4.2 — — µs 1 — — µs tw (cs) CS (the period when CS is high) tsu (cs) Data hold time th (sin) tword One word write time twt RAM data write time ns Supplementary Materials tw(cs) CS tsu(cs) tw(sclk) tw(sclk) tsu(sin) th(sin) th(cs) SCLK SIN CS tword twt SCLK 0 1 5 6 7 0 1 4 5 6 7 Figure 1 OSD Serial Data Input Timing No. 6526-8/38 VSS1, VSS2 VDD1, VDD2 SEP IN SEP C SYN IN OSC OUT OSC IN SEP OUT SYNC JDG IEOUT BLANK CHARA OUTMOD MUTE RST SCLK SIN Sync separator circuit Character output dot clock oscillator Serial to parallel converter Composite sync separator control Synchronous judgment 8-bit latch and command decoder Vertical size counter Vertical character size register Timing generator Horizontal size counter Horizontal character size register Line control counter Vertical display position detection Vertical dot counter Vertical display position register CTRL1 Xtal IN Xtal OUT Sync signal generator Character control counter Horizontal display position detection Horizontal dot counter Horizontal display position register CVCR Blinking and reverse video control circuit Display control register CDLR Yin Yout D0 to D7 A0 to A17, OE, CE Display RAM CIN Cbias Cout Shift register Font ROM Decoder RAM write address counter CV IN CV OUT Character output control Background control Video output control Blinking and reverse video control register Decoder CS LC74731W,74732W System Block Diagram No. 6526-9/38 LC74731W,74732W Display Control Commands Display control commands have an 8-bit format and are transferred using the serial input function. Commands consist of a command identification code in the first byte and command data in the following bytes. Display Control Commands First byte Command Second byte Command identification code Data Data 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 COMMAND0 (Write address setup) 1 0 0 0 V3 V2 V1 V0 0 0 0 H4 H3 H2 H1 H0 at2 at1 CB2 CB1 CB0 CC2 CC1 CC0 COMMAND1 (Character write) 1 0 0 1 IR SD2 SD1 SD0 0 0 0 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 0 VP6 VP5 VP4 VP3 VP2 VP1 VP0 COMMAND20 (Vertical display start position) 1 0 1 0 0 0 COMMAND21 (Horizontal display start position) 1 0 1 0 0 1 0 0 0 HP6 HP5 HP4 HP3 HP2 HP1 HP0 COMMAND22 (Character size) 1 0 1 0 1 0 0 SRM 0 0 0 0 VS1 VS0 HS1 HS0 COMMAND23 (Character size - in line units) 1 0 1 0 1 1 0 LSZUD 0 0 COMMAND3 (Display control) 1 0 1 1 TSTMOD RAMERS OSCSTP SYSRST 0 LCSOFF XN53S BLKSEL LC FS BK DSPON COMMAND4 (Display control) 1 1 0 0 NP2 NP1 NP0 I/N 0 HLFINT BCL1 BCL0 CB PH2 PH1 PH0 COMMAND50 (Sync signal detection 1) 1 1 0 1 0 0 DISLIN I/E 0 RN2 SN3 SN2 SN1 SN0 COMMAND51 (Sync signal detection 2) 1 1 0 1 0 1 MUT1 MUT0 0 O COMMAND52 (Display control) 1 1 0 1 1 0 EVEBSS LSPSS 0 CINSEL CINCTL VNPSEL COMMAND53 (Display control) 1 1 0 1 1 1 RSLG1 RSLG0 0 0 CTL3 SPOSEL PALAL4 COMMAND60 (Outlining setting) 1 1 1 0 0 0 0 BRM 0 COOMAND61 (Outlining setting - in line units) 1 1 1 0 0 1 0 LFCUD 0 0 LFCB5 LFCA4 LFC93 COMMAND62 (Line spacing) 1 1 1 0 1 0 0 GRM 0 O BXC1 GS1 COMMAND63 (Line spacing - in line units) 1 1 1 0 1 1 0 LGYUD 0 0 LGYB5 COMMAND70 (Display level) 1 1 1 1 0 0 0 LRM 0 0 BKLC1 BKLC0 CHLC1 CHLC0 RSLC1 RSLC0 COMMAND71 (Display level - in line units) 1 1 1 1 0 1 0 LCLUD 0 0 LCLB5 COMMAND72 (Halftone - in line units) 1 1 1 1 1 0 LHTDAT LHTUD 0 0 LHTB5 LHTA4 LHT93 LHT82 LHT71 LHT60 COMMAND73 (RGB control) 1 1 1 1 1 1 0 DASSS RRM1 RRM0 0 0 LSZB5 LSZA4 LSZ93 LSZ82 LSZ71 LSZ60 RN1 RN0 RNE0 SJN3 SJN2 SJN1 SJC1 SJC0 VSPSEL MSKERS MSKSEL EGLSEL IHSEL VSSEL HSSEL BLK1 BLK0 LFC82 LFC71 LFC60 GS0 GY2 GY1 GY0 LGY93 LGY82 LGY71 LGY60 BXBLV1 BXBLV0 BXWLV1 BXWLV0 ATSEL LGYA4 LCLA4 LCL93 LCL82 GBSEL OUTSEL HSPSW XONSS LCL71 BLK01 LCL60 BLK00 Note that when the display character data write command (COMMAND1) is written, tthese ICs lock into the display character data write mode, and another first byte cannot be written. When the CS pin is set high, the these ICs are set to the COMMAND0 (display memory write address setup mode) state. No. 6526-10/38 LC74731W,74732W COMMAND0 (Display memory write address setup command) • First byte Content DA0 to 7 Register 7 — 1 Command 0 identification code 6 — 0 Display memory write address setup 5 — 0 4 — 0 3 V3 2 V2 1 V1 0 V0 State 0 Function Notes Display memory line address (0 to B (hexadecimal)) 1 0 1 0 1 0 1 • Second byte Content DA0 to 7 Register 7 — 0 6 — 0 5 — 0 4 H4 3 H3 2 H2 1 H1 0 H0 State 0 Function Notes Second byte identification code Display memory line address (0 to 17 (hexadecimal)) 1 0 1 0 1 0 1 0 1 Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-11/38 LC74731W,74732W COMMAND1 (Display character data write setup command) • First byte Content DA0 to 7 Register 7 — 1 6 — 0 Command 1 identification code 5 — 0 Display character data write settings Note that when this command is input, the LC74731W/74732W lock into the display character data write mode until the CS pin is set high. 4 — 1 3 IR 0 Internal ROM Switching between internal and external ROM 1 External ROM 2 SD2 0 White-on-black (convex) display 1 Black-on-white (concave) display 1 SD1 0 Character frame start: off 1 Character frame start: on 0 Character frame stop: off 1 Character frame stop: on 0 SD0 State Notes Function Character frame specification • Second byte (1) DA0 to 7 Register Content State 0 7 at2 1 0 6 at1 1 5 cb2 4 cb1 3 cb0 2 cc2 1 cc1 0 cc0 0 Character attribute 2: off Blinking specification (Character frame upper side: off) Selected by COM60 second byte and ATSEL. Character attribute 2: on (Character frame upper side: on) Character attribute 1: off Reverse video specification (Character frame lower side: off) Selected by COM60 second byte and ATSEL. Character attribute 1: on (Character frame lower side: on) cb2 cb1 cb0 Character background color 1 ( B G R ) 0 0 0 0 Black 1 0 0 1 Red 0 0 1 0 Green 0 1 1 Yellow 1 0 0 Blue 1 0 1 Magenta 1 1 0 Cyan 1 1 1 cc2 cc1 cc0 1 0 Character background color specification Transparent Character color 1 ( B G R ) 0 0 0 0 Black 1 0 0 1 Red 0 0 1 0 Green 0 1 1 Yellow 1 0 0 Blue 1 0 1 Magenta 1 1 0 Cyan 1 1 1 White 1 Notes Function Character color specification No. 6526-12/38 LC74731W,74732W • Second byte (2) Content DA0 to 7 Register 7 — 0 6 — 0 5 — 0 4 c12 3 c11 2 c10 1 c09 0 c08 State 0 Notes Function Character code (00xx to 1Fxx (hexadecimal)) External ROM upper address 1 0 1 0 1 0 1 0 1 Note that all registers are set to 0 when these ICs are reset by the RST pin. • Second byte (3) DA0 to 7 Register 7 c07 6 c06 5 c05 4 c04 3 c03 2 c02 1 c01 0 c00 Content State Notes Function 0 Character code (00 to FF (hexadecimal)) External ROM lower address 1 FE (hexadecimal): Space character Internal ROM address 0 FF (hexadecimal): Transparent space character 1 0 1 0 1 0 1 0 1 0 1 0 1 Note that all registers are set to 0 when these ICs are reset by the RST pin. Continuous mode (cleared by setting CS high) operates as follows according to IR. When internal ROM is specified: 1-1 1-2-1 1-2-2 1-2-3 1-2-3 1-2-3 1-2-3 When external ROM is specified: 1-1 1-2-1 1-2-2 1-2-3 1-2-2 1-2-3 1-2-2 1-2-3 No. 6526-13/38 LC74731W,74732W COMMAND20 (Vertical display start position setup command) • First byte Content DA0 to 7 Register 7 — 1 Command 2 identification code 6 — 0 Vertical display position and vertical direction character size 5 — 1 settings 4 — 0 3 — 0 2 — 0 1 RRM1 0 RRM0 State Notes Function Extended command 0 identification code 0 RRM1 RRM0 1 0 0 Initial value (depends on IR) 0 0 1 1-2-1 1-2-2 1-2-3 Fixed 1 0 1-2-2 1-2-3 Fixed 1 1 1-2-3 Fixed 1 Continuous RAM write mode specification • Second byte Content DA0 to 7 Register 7 — 0 Second byte identification bit VP6 (MSB) 0 If VS is the vertical display start position then: 5 VP5 4 VP4 3 VP3 2 VP2 1 VP1 0 VP0 (LSB) 1 Notes Function 6 0 VS = α + H × ( 2 ∑ 2 n V P n ) 1 H: the horizontal synchronization pulse period 0 α = 20H (525H systems) 1 = 25H (625H systems) 0 The vertical display start position is set by the 7 bits VP0 to VP6. The weight of bit 1 is 2H. n=0 HSYNC 1 0 1 0 1 VS VSYNC 6 State HS Character display area 0 1 No. 6526-14/38 LC74731W,74732W COMMAND21 (Horizontal display start position setup command) • First byte Content DA0 to 7 Register 7 — 1 Command 2 identification code 6 — 0 Horizontal display position setup and horizontal direction 5 — 1 character size settings 4 — 0 3 — 0 2 — 1 1 — 0 0 — 0 State Notes Function Extended command 1 identification code • Second byte Content DA0 to 7 Register 7 — 0 Second byte identification bit 6 HP6 (MSB) 0 If HS is the horizontal start position then: 5 HP5 4 HP4 State Notes Function 1 The horizontal display start position is set by the 7 bits HP0 to HP6. 6 3 HP3 2 HP2 1 HP1 0 HP0 (LSB) 0 HS =Tc × ( 2 ∑ 2 n H P n ) The weight of bit 1 is 2Tc. n=0 1 0 1 Tc: Period of the oscillator connected to OSCIN/OSCOUT in operating mode. 0 1 0 1 0 1 0 1 Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-15/38 LC74731W,74732W COMMAND22 (Character size setting command) • First byte Content DA0 to 7 Register 7 — 1 Command 2 identification code 6 — 0 Horizontal display position setup and horizontal direction 5 — 1 character size settings 4 — 0 3 — 1 2 — 0 1 — 0 0 SRM State Function Notes Extended command 2 identification code 0 Continuous mode: off 1 Continuous mode: on Character size continuous mode specification • Second byte Content DA0 to 7 Register 7 — 0 6 — 0 5 — 0 4 — 0 3 VS1 2 VS0 1 HS1 0 HS0 State Function Second byte identification bit 0 VS1 VS0 Character size 1 0 0 1× 0 0 1 2× 1 0 3× 1 1 4× 0 HS1 HS0 Character size 1 0 0 1× 0 0 1 2× 1 0 3× 1 1 4× 1 1 Notes Vertical direction character size, in line units Horizontal direction character size, in line units Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-16/38 LC74731W,74732W COMMAND23 (Character size and line setup command) • First byte Content DA0 to 7 Register 7 — 1 Command 2 identification code 6 — 0 Horizontal display position setup and horizontal direction 5 — 1 character size settings 4 — 0 3 — 1 2 — 1 1 — 0 0 LSZUD State Function Notes Extended command 3 identification code 0 Lower lines: 0 to 5 (hexadecimal) 1 Upper lines: 6 to B (hexadecimal) Upper/lower line specification • Second byte Content DA0 to 7 Register 7 — 0 6 — 0 5 LSZB5 4 LSZA4 3 2 1 0 LSZ93 LSZ82 LSZ71 LSZ60 State Function Notes Second byte identification bit 0 Line 6 (line 12) specification: off 1 Line 6 (line 12) specification: on 0 Line 5 (line 11) specification: off 1 Line 5 (line 11) specification: on 0 Line 4 (line 10) specification: off 1 Line 4 (line 10) specification: on 0 Line 3 (line 9) specification: off 1 Line 3 (line 9) specification: on 0 Line 2 (line 8) specification: off 1 Line 2 (line 8) specification: on 0 Line 1 (line 7) specification: off 1 Line 1 (line 7) specification: on The line shown in parentheses is specified when LSZUD is 1. Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-17/38 LC74731W,74732W COMMAND3 (Display control setup command) • First byte Content DA0 to 7 Register 7 — 1 Command 3 identification code 6 — 0 Display character data write settings 5 — 1 4 — 1 3 TSTMOD 2 RAMERS 1 0 OSCSTP SYSRST State Notes Function 0 Normal operating mode 1 Test mode This bit must always be 0. 0 The RAM erase operation takes about 500 µs. (It 1 Erase display RAM (sets the data to FF (hexadecimal)) must be executed in the DSPOFF state.) 0 Do not stop the crystal and LC oscillator circuits. This setting is valid in external synchronization 1 Stop the crystal and LC oscillator circuits. 0 1 mode when character display is off. The reset occurs when the CS pin is low, and is Reset all registers. This turns the display off. cleared when CS is set high. • Second byte DA0 to 7 Register 7 — 6 LCSOFF 5 XN53S 4 BLKSEL 3 LC 2 FS 1 BK 0 DSPON Content State Notes Function 0 Second byte identification bit 0 Normal operation 1 LC oscillator STOP: Disabled 0 Normal 1 Switching 0 Character display area Specifies the character size that fills the whole 1 Video display area character area. 0 The LC oscillator is used as the dot clock. Selects the dot clock used for character display in 1 The crystal oscillator is used as the dot clock. the horizontal direction. 0 Crystal oscillator frequency: 2 fsc Sets the crystal oscillator frequency. 1 Crystal oscillator frequency: 4 fsc 0 Blinking period: 0.5 s 1 Blinking period: 1 s 0 Character display: off 1 Character display: on Switches the LC oscillator STOP control Switches the crystal oscillator capability Switches the blinking period. Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-18/38 LC74731W,74732W COMMAND4 (Display control setup command) • First byte Content DA0 to 7 Register 7 — 1 Command 4 identification code 6 — 1 Display control settings 5 — 0 4 — 0 3 NP2 2 NP1 1 0 NP0 I/N State Function 0 NP2 NP1 NP0 1 0 0 0 NTSC 0 0 0 1 PAL-M 1 0 1 0 PAL 0 0 1 1 PAL-N 1 1 0 0 NTSC4.43 1 0 1 PAL60 0 Interlaced 1 Noninterlaced Signal format Notes Switches the signal format Switches between interlaced and noninterlaced • Second byte DA0 to 7 Register 7 — 6 HLFINT 5 BCL1 4 BCL0 3 CB 2 PH2 1 PH1 0 PH0 Content State Function 0 Second byte identification bit 0 Normal mode 1 Semi-internal synchronization mode 0 BCL1 BCL0 1 0 0 Background color shown 0 0 1 No background color (RSL1) 1 0 No background color (CBH) 1 1 No background color (RSH1) 1 Only valid in internal synchronization mode. 0 The color burst signal is output. 1 Color burst signal output is stopped. 0 PH2 PH1 PH0 1 B G R 0 0 0 0 Black (RSLx) 1 0 0 1 Red 0 0 1 0 Green 0 1 1 Yellow 1 0 0 Blue 1 0 1 Magenta 1 1 0 Cyan 1 1 1 White (RSHx) 1 Notes Background color Only valid when BCL is high. Background color specification Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-19/38 LC74731W,74732W COMMAND50 (Sync signal detection 1 setup command) • First byte Content DA0 to 7 Register 7 — 1 Command 5 identification code 6 — 1 Sync signal control settings 5 — 0 4 — 1 3 — 0 2 — 0 1 DISLIN 0 I/E State Function Notes Extended command 0 identification code 0 12 lines 1 10 lines Switches the number of lines displayed. 0 External synchronization 1 Internal synchronization Switches between internal and external synchronization • Second byte DA0 to 7 Register 7 — 6 RN2 5 RN1 4 RN0 3 SN3 2 SN2 1 0 SN1 SN0 Content State 0 Function Second byte identification bit 0 RN2 RN1 RN0 1 0 0 0 0 times (32 times) 0 0 0 1 4 times (64 times) 1 0 1 0 8 times (128 times) 0 1 0 0 Number of times HSYNC detected 16 times (256 times) 1 0 Notes SN3 SN2 SN1 SN0 Number of times HSYNC detected 1 0 0 0 0 Not detected 0 0 0 0 1 32 times 1 0 0 1 0 64 times 0 0 1 0 0 128 times 1 1 0 0 0 256 times External sync signal detection control Recognition of the transition from the no signal state to the signal present state. Sets the sampling period in which the sync signal can be detected continuously in the horizontal sync signal period (1H). The values in parentheses apply when RNE0 (COM51) is 1. External sync signal detection control Recognition of the transition from the signal present state to the no signal state. Sets the sampling period time in which the sync signal cannot be detected continuously in the horizontal sync signal period (1H). 0 1 Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-20/38 LC74731W,74732W COMMAND51 (Sync signal detection 2 setup command) • First byte Content DA0 to 7 Register 7 — 1 Command 5 identification code 6 — 1 Display control settings 5 — 0 4 — 1 3 — 0 2 — 1 1 MUT1 0 MUT0 State 0 Notes Function Extended command 1 identification code MUT1 MUT0 0 Output Video signal output muting function selection CSYNC Valid when the MUTE pin is low. 1 0 0 0 1 PE 1 1 0 A0-17 “Z” • Second byte Content DA0 to 7 Register 7 — 0 6 — 0 5 SJNS3 3 SJNS2 1 0 SJNS1 SJCS1 SJCS0 Notes Function Second byte identification bit 0 Sync signal no signal to signal present discrimination - Normal values 1 Sync signal no signal to signal present discrimination - Values shown in parentheses 0 SJNS3 SJNS2 SJNS1 RNE0 4 2 State Times 1 0 0 0 None 0 0 0 1 4 1 0 1 0 8 0 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 256 1 0 SJCS1 SJCS0 PAL Changes the judgment criterion values for sync signal recognition for the no signal to signal present transition. (COM50) Noise ignoring circuit setting for sync signal recognition for the no signal to signal present transition If more than the number of horizontal signals shown at the left are input during a 1H period, the circuit recognizes a no signal state. NTSC Synchronization discrimination 1 0 0 677 ns (1/3) 558 ns (1/2) Selects the clock used to delimit the HSYNI signal. 0 0 1 903 ns (1/4) 838 ns (1/3) 1 1 0 450 ns (1/2) 1117 ns (1/4) Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-21/38 LC74731W,74732W COMMAND52 (Display control setup command) • First byte Content DA0 to 7 Register 7 — 1 Command 5 identification code 6 — 1 Display control settings 5 — 0 4 — 1 3 — 1 2 — 0 1 EVEBSS 0 LSPSS State Notes Function Extended command 2 identification code 0 Normal 1 Always high 0 Normal 1 HT12 “on” HT34 “off” Switches the ENBVI signal LCSTOP control signal • Second byte DA0 to 7 Register 7 — 6 CINSEL 5 CINCTL 4 VNPSEL 3 VSPSEL 2 MSKERS 1 MSKSEL 0 EGL Content State Notes Function 0 Second byte identification bit 0 Blank area (the logical OR of the character and outlining signals) 1 Video signal display area 0 CVCR: off 1 CVCR: on 0 V signal falling edges detected 1 V signal rising edges detected Switches the V signal acquisition polarity when external mode/internal V separation is used 0 VSEP: About 8.9 µs (NTSC) Switches the internal vertical separation time 1 VSEP: About 17.8 µs (NTSC) 0 Mask enabled 1 Mask disabled 0 3H (NTSC) 1 20H (NTSC) 0 Outlining level 0 only (VBK0) Switches the outlining level (Only valid when BLK0 1 Two-stage outlining level (VBK0, VBK1) is 0 and BLK1 is 1.) Switches the CVCR on state signal CVCR on/off switching Clears the HSYNC and VSYNC masks Switches the VSYNC mask Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-22/38 LC74731W,74732W COMMAND53 (Display control setup command) • First byte Content DA0 to 7 Register 7 — 1 Command 5 identification code 6 — 1 Display control settings 5 — 0 4 — 1 3 — 1 2 — 1 1 RSLG1 0 RDLG0 State 0 Notes Function Extended command 3 identification code RSLG1 RSLG0 Switches the screen background color level 1 0 0 NO1 RS1 0 0 1 NO2 RS2 1 1 0 NO3 RS3 • Second byte Content DA0 to 7 Register 7 — 0 6 — 0 5 CTL3 4 SP0SEL 3 PALAL4 2 IHSEL 1 VSSEL 0 HSSEL State Notes Function Second byte identification bit 0 Internal vertical separation circuit 1 External input Switches the VSYNC signal input 0 CSYNC (sync separator output) 1 Halftone output 0 Normal 1 Always use 4 fsc timing (PAL) 0 SYNin pin input signal 1 SEPin pin input signal Switches the internal vertical separation input signal 0 Negative polarity Switches the SEPin input polarity 1 Positive polarity 0 Negative polarity 1 Positive polarity Switches the SEPout pin output Switches the SYNin input polarity (Invalid for CVIDEO input) Note that all registers are set to 0 when these ICs are reset by the RST pin. SYnin: CVIDEO (Built-in sync separator circuit) SEPin: None (internal vertical separation) or :VSYNC SYNin: HD SEPin: CSYNC (internal vertical separation) SYNin: HSYNC SEPin: VSYNC SYNin: CSYNC (internal vertical separation) SEPin: None No. 6526-23/38 LC74731W,74732W COMMAND60 (Outlining control setup command) • First byte Content DA0 to 7 Register 7 — 1 Command 6 identification code 6 — 1 Display control settings 5 — 1 4 — 0 3 — 0 2 — 0 1 — 0 0 BRM State Notes Function Extended command 0 identification code 0 Normal mode 1 Continuous mode Specifies continuous mode • Second byte DA0 to 7 Register 7 — 6 BXBLV1 5 BXBLV0 4 BXWLV1 3 BXWLV0 2 ATSEL 1 BLK1 0 BLK0 Content State 0 Second byte identification bit 0 BXBLV1 BXBLV0 Character frame - black level specification 1 0 0 NO1 BK1 0 0 1 NO2 BK2 1 1 0 NO3 BK3 0 Notes Function BXWLV1 BXWLV0 In line units Character frame - white level specification 1 0 0 NO1 CHA1 0 0 1 NO2 CHA2 1 1 0 NO3 CHA3 In line units 0 Reverse video, blinking Setup for the at1 and at2 function 1 Character frame specified In line units 0 BLK1 Mode Outlining mode specification 1 0 0 Normal In line units 0 0 1 Character size 1 0 Outlining size 1 1 Full area size 1 BLK0 Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-24/38 LC74731W,74732W COMMAND61 (Outlining control and line specification setup command) • First byte Content DA0 to 7 Register 7 — 1 Command 6 identification code 6 — 1 Display control settings 5 — 1 4 — 0 3 — 0 2 — 1 1 — 0 0 LFCUD State Notes Function Extended command 1 identification code 0 Lower lines (0 to 5 (hexadecimal)) 1 Upper lines (6 to B (hexadecimal)) Outlining control line specification • Second byte Content DA0 to 7 Register 7 — 0 6 — 0 5 LFCB5 4 3 2 1 0 LFCA4 LFC93 LFC82 LFC71 LFC60 State Notes Function Second byte identification bit 0 Line 6 (line 12) setting: off Outlining line setting 1 Line 6 (line 12) setting: on The values in parentheses apply when LFCUD is 1. 0 Line 5 (line 11) setting: off 1 Line 5 (line 11) setting: on 0 Line 4 (line 10) setting: off 1 Line 4 (line 10) setting: on 0 Line 3 (line 9) setting: off 1 Line 3 (line 9) setting: on 0 Line 2 (line 8) setting: off 1 Line 2 (line 8) setting: on 0 Line 1 (line 7) setting: off 1 Line 1 (line 7) setting: on Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-25/38 LC74731W,74732W COMMAND62 (Line spacing control setup command) • First byte Content DA0 to 7 Register 7 — 1 Command 6 identification code 6 — 1 Display control settings 5 — 1 4 — 0 3 — 1 2 — 0 1 — 0 0 GRM State Notes Function Extended command 2 identification code 0 Normal mode 1 Continuous mode Continuous mode specification • Second byte Content DA0 to 7 Register 7 — 0 6 — 0 5 BXC1 4 3 GS1 GS0 2 GY2 1 GY1 0 GY0 State Second byte identification bit 0 Display outside the character area 1 Forces display within the character area 0 GS1 GS0 1 0 0 Normal (character background color) 0 0 1 Full area and reverse invalid (other than ±1) 1 0 Transparent 1 (all) 1 1 0 GY2 GY1 GY0 1 0 0 0 0 0 0 0 1 ±1 1 0 1 0 2 0 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 1 1 Notes Function Mode Box left/right display specification In line units In line units Transparent 2 (other than ±1) Line spacing In line units Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-26/38 LC74731W,74732W COMMAND63 (Line spacing control - line specification setup command) • First byte Content DA0 to 7 Register 7 — 1 Command 6 identification code 6 — 1 Display control settings 5 — 1 4 — 0 3 — 1 2 — 1 1 — 0 0 LGYUD State Function Notes Extended command 3 identification code 0 Lower lines (0 to 5 (hexadecimal)) 1 Upper lines (6 to B (hexadecimal)) Line spacing control - line specification • Second byte Content DA0 to 7 Register 7 — 0 6 — 0 5 LGYB5 4 3 2 1 0 LGYA4 LGY93 LGY82 LGY71 LGY60 State Function Notes Second byte identification bit 0 Line 6 (line 12) setting: off Line setting for line spacing control 1 Line 6 (line 12) setting: on The values in parentheses apply when LGYUD is 1. 0 Line 5 (line 11) setting: off 1 Line 5 (line 11) setting: on 0 Line 4 (line 10) setting: off 1 Line 4 (line 10) setting: on 0 Line 3 (line 9) setting: off 1 Line 3 (line 9) setting: on 0 Line 2 (line 8) setting: off 1 Line 2 (line 8) setting: on 0 Line 1 (line 7) setting: off 1 Line 1 (line 7) setting: on Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-27/38 LC74731W,74732W COMMAND70 (Display control setup command) • First byte Content DA0 to 7 Register 7 — 1 Command 7 identification code 6 — 1 Display control settings 5 — 1 4 — 1 3 — 0 2 — 0 1 — 0 0 LRM State Function Notes Extended command 0 identification code 0 Normal mode 1 Continuous mode Continuous mode specification • Second byte Content DA0 to 7 Register 7 — 0 6 — 0 5 BKLC1 4 BKLC0 3 CHLC1 2 CHLC0 1 RSLC2 0 RSLC1 State Function Notes Second byte identification bit 0 BKLC1 BKLC0 1 0 0 NO1 BK1 0 0 1 NO2 BK2 1 1 0 NO3 BK3 0 CHLC1 CHLC0 1 0 0 NO1 CHA1 0 0 1 NO2 CHA2 1 1 0 NO3 CHA3 0 RSLC1 RSLC0 1 0 0 NO1 RS1 0 0 1 NO2 RS2 1 1 0 NO3 RS3 Character color and character background color: black level specification In line units Character color and character background color: white level specification In line units Character color and character background color: color level specification In line units Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-28/38 LC74731W,74732W COMMAND71 (Display levels - line specification setup command) • First byte Content DA0 to 7 Register 7 — 1 Command 7 identification code 6 — 1 Display control settings 5 — 1 4 — 1 3 — 0 2 — 1 1 — 0 0 LCLUD State Function Notes Extended command 1 identification code 0 Lower lines (0 to 5 (hexadecimal)) 1 Upper lines (6 to B (hexadecimal)) Display levels - line specification • Second byte Content DA0 to 7 Register 7 — 0 6 — 0 5 LCLB5 4 3 2 1 0 LCLA4 LCL93 LCL82 LCL71 LCL60 State Function Notes Second byte identification bit 0 Line 6 (line 12) setting: off Display level line setting 1 Line 6 (line 12) setting: on The values in parentheses apply when LCLUD is 1. 0 Line 5 (line 11) setting: off 1 Line 5 (line 11) setting: on 0 Line 4 (line 10) setting: off 1 Line 4 (line 10) setting: on 0 Line 3 (line 9) setting: off 1 Line 3 (line 9) setting: on 0 Line 2 (line 8) setting: off 1 Line 2 (line 8) setting: on 0 Line 1 (line 7) setting: off 1 Line 1 (line 7) setting: on Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-29/38 LC74731W,74732W COMMAND72 (Halftone - line specification setup command) • First byte Content DA0 to 7 Register 7 — 1 Command 7 identification code 6 — 1 Display control setup 5 — 1 4 — 1 3 — 1 2 — 0 1 LHTDAT 0 LHTUD State Notes Function Extended command 2 identification code 0 Halftone: off 1 Halftone: on Halftone control 0 Lower lines (0 to 5 (hexadecimal)) 1 Upper lines (6 to B (hexadecimal)) Halftone line specification • Second byte Content DA0 to 7 Register 7 — 0 6 — 0 5 LHTB5 4 LHTA4 3 2 1 0 LHT93 LHT82 LHT71 LHT60 State Function Notes Second byte identification bit 0 Line 6 (line 12) setting: off 1 Line 6 (line 12) setting: on 0 Line 5 (line 11) setting: off 1 Line 5 (line 11) setting: on 0 Line 4 (line 10) setting: off 1 Line 4 (line 10) setting: on 0 Line 3 (line 9) setting: off 1 Line 3 (line 9) setting: on 0 Line 2 (line 8) setting: off 1 Line 2 (line 8) setting: on 0 Line 1 (line 7) setting: off 1 Line 1 (line 7) setting: on Halftone line setting The values in parentheses apply when LHTUD is 1. Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-30/38 LC74731W,74732W COMMAND73 (RGB control setup command) • First byte Content DA0 to 7 Register 7 — 1 Command 7 identification code 6 — 1 Display control setup 5 — 1 4 — 1 3 — 1 2 — 1 1 — 0 0 — 0 State Notes Function Extended command 3 identification code • Second byte DA0 to 7 Register 7 — 6 DASSS 5 GBSEL 4 OUTSEL 3 2 HSPSW XONSS 1 BLK02 0 BLK01 Content State Notes Function 0 Second byte identification bit 0 Normal 1 CLKD = CLKX Only valid when RGB output is specified. 0 Background color: off Switches the background color in RGB output mode 1 Background color: on The background color is specified by COM4 second byte. Switches the XTALIN amplifier input 0 Switches the P9 to P12 outputs 1 RGB output switching The logical OR with the OUTMOD input. 0 Internal Sync separator used Switches the SYNin input 1 Internal Sync separator not used The logical OR with the OUTMOD input. 0 Operation depends on the CTRL1 pin 1 Feedback resistor disconnected Enables or disables the feedback resistor for the XTALIN clock. 0 BLK01 BLK00 1 0 0 CHA + BK + CHAB Box is always on. 0 0 1 CHA +BK only Always on when GBSEL = 1. 1 0 CHA only 1 1 BK only 1 Switches the BLKout output No. 6526-31/38 LC74731W,74732W Display Screen Structure The display consists of 12 lines of 24 characters. Up to 288 characters can be displayed. The number of characters that can be displayed is less than the 288 maximum when enlarged characters are displayed. Display memory addresses are specified as row (0 to 11 decimal) and column (0 to 23 decimal) addresses. Display Screen Structure (display memory addresses) 24 Characters 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 00 0 01 1 02 2 03 3 04 4 05 5 06 6 07 7 08 8 09 9 10 A 12 Rows 11 B HEX 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 HEX No. 6526-32/38 LC74731W,74732W Composite Video Signal Output Levels (internally generated levels) • CVOUT Output Level Waveform (VDD2 = 5.00 V) ① ② ③ [V] 2.80 3.00 3.30 VCHA1 2.65 2.85 3.15 VRSH3 VRSH2 2.37 2.57 2.87 VCHA2 VCHA3 VBK3 2.08 2.28 2.58 2.01 2.21 2.51 VRSH1 VBK2 1.67 1.87 2.17 VRSL3 VCBH 1.52 1.72 2.02 1.50 1.70 2.00 1.37 1.57 1.87 VBK1 VPD 1.23 1.43 1.73 VRSL2 1.07 1.27 1.67 0.80 1.00 1.40 VRSL1 VCBL VSN 1H Output voltage (1) [V] Output voltage (2) [V] Output voltage (3) [V] VCHA1: Character 1 Output level 2.65 2.85 3.25 VRSH2: Background color 2: high 2.37 2.57 2.97 VCHA3: Character 3 2.23 2.43 2.83 2.68 VBK3: Outlining: 3 2.08 2.28 VRSH1: Background color 1: high 2.01 2.21 2.61 VBK2: Outlining: 2 1.80 2.00 2.40 VCBH: Color burst: high 1.67 1.87 2.27 VRSL1: Background color 1: low 1.52 1.72 2.12 VBK1: Outlining: 1 1.50 1.70 2.10 VPD: Pedestal 1.37 1.57 1.97 VRSL2: Background color 2: low 1.23 1.43 1.83 VCBL: Color burst: low 1.07 1.27 1.67 VSN: Sync 0.80 1.00 1.40 BCOL01: RSL1 BCOL0: CBH BCOL11:RSH1 No. 6526-33/38 LC74731W,74732W YOUT Output Level Waveform (VDD2 = 5.00 V) ① ② ③ [V] 2.80 3.00 3.30 YCHA1 2.65 2.85 3.15 YCHA2 YCHA3 YRS3 YBK3 2.08 2.28 2.58 YRS2 YBK2 YRS1 1.50 1.70 2.00 YCB 1.37 1.57 1.87 0.80 1.00 1.40 YBK1 YPD YSN 1H Output voltage (1) [V] Output voltage (2) [V] Output voltage (3) [V] YCHA1: Character 1 Output level 2.65 2.85 3.25 YCHA2: Character 2 2.37 2.57 2.97 YCHA3: Character 3 2.23 2.43 2.83 YBK3: Outlining: 3 2.08 2.28 2.68 YRS3: Background color 3 2.02 2.22 2.62 YRS2: Background color 2 1.80 2.00 2.40 YRS1: Background color 1 1.76 1.96 2.36 YBK1: Outlining: 1 1.50 1.70 2.10 YCB: Color burst 1.37 1.57 1.97 YPD: Pedestal 1.37 1.57 1.97 YSN: Sync 0.80 1.00 1.40 BCOL01: YBK1 BCOL10: YRS1 BCOL11: YRS3 No. 6526-34/38 LC74731W,74732W • COUT Output Level Waveform (VDD2 = 5.00 V) CRSH2 CCBH CRSH1 2.50 V CBIAS CRSL1 CCBL CRSL3 CRSL2 Output voltage (1) [V] Output voltage (2) [V] CRSH2: Background color 2: high Output level 3.07 3.07 Output voltage (3) [V] 3.07 CCBH: Color burst: high 2.80 2.80 2.80 CRSH1: Background color 1: low 2.74 2.74 2.74 CBIAS: Bias 2.50 2.50 2.50 CRSL1: Background color 2: low 2.25 2.25 2.25 CCBL: Color burst: low 2.20 2.20 2.20 CRSL2: Background color 2: low 1.93 1.93 1.93 BCOL01, 10, 11: CBIAS No. 6526-35/38 LC74731W,74732W Sample Application Circuit • Cvideo, Y/C A5 A4 A3 A2 A1 A0 OE CE 49 D7 D6 D5 D4 D2 D1 D0 1 D3 From external ROM 64 48 VSS1 A6 XtalIN A7 XtalOUT A8 CTRL1 A9 OSCIN A10 OSCOUT A11 MUTE A12 CDLR A13 SYNCJDG/ROUT A14 CHARA/GOUT A15 BLANK/BOUT A16 IBOUT/BLKOUT A17 OUTMOD VDD1 CS RST SIN SEPIN 33 SYNIN CVCR CVIN NC CVOUT VSS2 YIN NC YOUT NC CBIAS CIN NC COUT VDD2 17 HFTIN SEPOUT SCLK 16 To external ROM 32 +5 V Buffer Buffer Clamp Buffer Clamp Clamp No. 6526-36/38 LC74731W,74732W • RGB A5 A4 A3 A2 A1 A0 OE 49 CE D7 D6 D5 D4 D2 D1 D0 1 D3 From external ROM 64 48 VSS1 A6 XtalIN A7 XtalOUT A8 CTRL1 A9 OSCIN A10 OSCOUT A11 MUTE A12 CDLR A13 SYNCJDG/ROUT A14 CHARA/GOUT A15 BLANK/BOUT A16 IBOUT/BLKOUT A17 OUTMOD VDD1 CS RST SIN SEPIN 33 SYNIN CVCR CVIN NC CVOUT VSS2 YIN NC YOUT NC CBIAS CIN NC COUT VDD2 HFTIN SEPOUT SCLK 16 To external ROM 17 vsync 32 +5 V hsync No. 6526-37/38 LC74731W,74732W Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of June, 2000. Specifications and information herein are subject to change without notice. PS No. 6526-38/38