Ordering number : EN*5919
CMOS IC
LC74775, 74775M
On-Screen Display Controller IC
Preliminary
Overview
Package Dimensions
The LC74775/M is an on-screen display controller CMOS
IC that displays characters and patterns on the TV screen
under microprocessor control. This IC includes a built-in
PDC/VPS/UDT interface circuit.
unit: mm
3196-DIP30SD
[LC74775]
Functions
• Display format: 24 characters by 12 rows (Up to 288
characters)
• Character format: 12 (horizontal) × 18 (vertical) dots
• Character sizes: Three sizes each in the horizontal and
vertical directions
• Characters in font: 128 (Of the 128 characters, one is a
space character (7E hexadecimal)
and one is a transparent space
character (7F hexadecimal))
• Initial display positions: 64 horizontal positions and 64
vertical positions
• Blinking: Specifiable in character units
• Blinking types: Two periods supported:
1.0 second and 0.5 second
• Blanking: Over the whole font (12 × 18 dots)
• Background color: 8 colors (internal synchronization
mode): 4fSC and 2fSC
Blue background only: NTSC
• Line background color: Three lines can be set up.
8 line background colors (in
internal synchronization mode):
4fSC and 2fSC
• External control input: 8-bit serial input format
• On-chip sync separator circuit
• Video outputs: PAL and NTSC format composite video
outputs
• On-chip PDC/VPS/UDT interface circuit supporting I2C
• Package: DIP30SD
MFP30S
SANYO: DIP30SD
unit: mm
3216A-MFP30S
[LC74775M]
SANYO: MFP30S
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
N1198RM(OT) No. 5919-1/35
LC74775, 74775M
Pin Assignment
No. 5919-2/35
LC74775, 74775M
Pin Functions
Pin no.
Pin
1
VSS1
2
XtalIN
3
XtalOUT
Function
Ground connection (digital system ground)
Crystal oscillator
(MUTE input)
These pins are used either to connect the crystal and capacitors used to form an external
crystal oscillator circuit to generate the internal synchronizing signals, or to input an external
clock signal (2fsc or 4fsc). As a mask option, the XtalOUT pin can be set to function as
the MUTE input pin. When this pin is set low, the video output is held at the pedestal level.
(A pull-up resistor is built in and the input has hysteresis characteristics.)
Crystal oscillator input
switching
(CHABLK)
Switches the mode between external clock input and crystal oscillator operation. A low level
selects crystal oscillator operation and a high level selects external clock input. As a mask
option, the CTRL1 input pin can be set to function as the CHABLK (character . frame)
output. This is a 3-value output.
I2C clock input
Clock input for the PDC/VPS data output. I2C bus.
LC oscillator
connections
Connection for the external coil and capacitor for the oscillator used to generate
the character output dot clock
External synchronizing
signal judgment output
Outputs the state of the external synchronizing signal presence/absence judgment. Outputs
a high level when synchronizing signals are present.
Outputs either the crystal oscillator clock if CS and RST are low, or the VCO clock if CS
and RST are high.
(This signal is not output after a command reset.)
Enable input
Enable input for the OSD serial data input.
Serial data input is enabled when this pin is low.
A pull-up resistor is built in and the input has hysteresis characteristics.
(MUTE)
4
CTRL1
(CHABLK)
5
SCL
6
OSCIN
7
OSCOUT
Notes
Ground
8
SYNCJDC
9
CS
10
SCLK
Clock input
Serial data input enable pin.
A pull-up resistor is built in and the input has hysteresis characteristics.
11
SIN
Data input
Serial data input.
A pull-up resistor is built in and the input has hysteresis characteristics.
Power supply
Composite video signal level adjustment power supply (analog system power supply)
12
VDD2
13
CPOUT
Charge pump output
Charge pump output. Connect a low-pass filter to this pin.
14
VCOIN
Oscillator control voltage input
VCO oscillator control voltage input. (For data slicing)
15
VSS3
Ground
Ground (VCO ground)
16
VCOR
Oscillator range adjustment
VCO oscillator range adjustment resistor connection
17
NC
18
VDD3
Power supply (+5 V)
Power supply (+5 V: VCO power supply)
This pin must either be connected to ground or left open
19
CVOUT
Video signal output
Composite video signal output
20
VSS2
Ground
Ground (analog system ground)
21
CVIN
Video signal input
Composite video signal input
22
CVCR
Video signal input
SECAM chrominance signal input
23
VDD1
Power supply (+5 V)
Power supply (+5 V: digital system power supply)
24
SYNIN
Sync separator circuit input
Video signal input to the internal sync separator circuit
25
SEPC
Slice level output
Slice level verification pin
Composite synchronizing
signal output
Internal sync separator circuit composite synchronizing signal output. The signal actually
output can be switched by MOD0 and SEL0. The DAV signal is output in the initial state.
I2C bus data I/O
PDC/VPS data I/O.
The I2C bus write address is [0111 1100].
The I2C bus read address is [0111 1101].
Background color phase
adjustment
Background color phase adjustment resistor connection
26
SEPOUT
27
SDA
28
CDLR
29
RST
Reset input
System reset input.
A pull-up resistor is built in and the input has hysteresis characteristics.
30
VDD1
Power supply (+5 V)
Power supply (+5 V: digital system power supply)
Note: *Both VDD1 pins must be connected to power.
No. 5919-3/35
LC74775, 74775M
Absolute Maximum Ratings
Paremeter
Symbol
Conditions
Ratings
Unit
VSS – 0.3 to VSS + 6.5
V
All input pins
VSS – 0.3 to VDD1 + 0.3
V
SDA, SYNCJDG, and SEPOUT
VSS – 0.3 to VDD1 + 0.3
Maximum supply voltage
VDDmax
VDD1, VDD2, and VDD3
Maximum input voltage
VINmax
Maximum output voltage
Allowable power dissipation
VOUTmax
Pd max
Ta = 25°C
V
350
mW
Operating temperature
Topr
–30 to + 70
°C
Storage temperature
Tstg
–40 to + 125
°C
Allowable Operating Ranges
Ratings
Paremeter
Symbol
Conditions
min
typ
Unit
max
VDD1
VDD1, VDD3
4.5
5.0
5.5
V
VDD2
VDD2
4.5
5.0
6.5
V
VIH1
CS, SIN, SCLK, SDA, SCL,
0.8VDD1
5.5
V
VIH2
RST, MUTE
0.8VDD1
VDD1 + 0.3
V
VIH3
CTRL1
0.7VDD1
VDD1 + 0.3
V
VIL1
RST, CS, SIN, SCLK, SDA, SCL,
MUTE
VSS – 0.3
0.2VDD1
V
VIL2
CTRL1
VSS – 0.3
0.3VDD1
V
Pull-up resistance
RPU
RST, CS, SIN, SCLK, MUTE
Applies to pins set up by options.
90
kΩ
Composite video signal
input voltage
VIN1
CVIN, CVCR: VDD1 = 5V
VIN2
SYNIN: VDD1 = 5V
VIN3
XtalIN (when used for external clock input)
fIN = 2fsc or 4fsc: VDD1= 5V
fOSC1
XtalIN and XtalOUT oscillator pins (2fsc: PAL)
8.867
MHz
fOSC2
XtalIN and XtalOUT oscillator pins (4fsc: PAL)
17.734
MHz
fOSC3
OSCIN and OSCOUT oscillator pins (LC oscillator)
Supply voltage
Input high-level voltage
Input low-level voltage
Input voltage
Oscillator frequencies
25
50
2.0
1.5
2.0
0.10
5
Vp-p
2.5
Vp-p
5.0
Vp-p
10
MHz
Note: Applications must be especially cautious about noise when using the XtalIN input pin in clock input mode.
Electrical Characteristics at Ta = –30 to +70°C, VDD1 = 5 V unless otherwise specified
Ratings
Paremeter
Symbol
Conditions
min
typ
Unit
max
Input off leakage current
Ileak1
CVIN, CVCR
1
µA
Output off leakage current
Ileak2
CVOUT, SDA
1
µA
Output high-level voltage
VOH1
SEPOUT, CPOUT, SYNCJDG
VDD1 = 4.5V, IOH = –1.0 mA
VOL1
SEPOUT, CPOUT, SYNCJDG
VDD1 = 4.5 V, IOL = 1.0 mA
VOL2
SDA: VDD1 = 5.0V, IOL = 3.0 mA
Output low-level voltage
Three-value output voltage
VO
CHABLK: VDD1 = 5.0 V
IIH
RST, CS, SIN, SCLK, SDA, SCL, CTRL1,
MUTE, VCOIN: VIN = VDD1
IIL
CTRL1, SDA, SCL, VCOIN
VIN = VSS1
3.5
V
1.0
V
0.4
V
H
3.3
5.0
V
M
1.8
2.3
V
L
0
0.8
V
1
µA
Input current
Operating mode current drain
SYNC level
Pedestal level
IDD1
VDD1 and VDD3: With all outputs open
Xtal: 17.734 MHz, LC: 8 MHz
IDD2
VDD2: VDD2 = 5 V
VSN
VPD
CVOUT: VDD1 = 5.0 V,
VDD2 = 5.0 V
CVOUT: VDD1 = 5.0 V,
VDD2 = 5.0 V
–1
µA
40
mA
20
mA
(1)
0.80
V
(2)
1.00
V
(3)
1.40
V
(1)
1.37
V
(2)
1.57
V
(3)
1.97
V
Continued on next page.
No. 5919-4/35
LC74775, 74775M
Continued from preceding page.
Paremeter
Color burst low level
Color burst high level
Background color
(other than blue) low level
Background color
(other than blue) high level
Blue background color 1
low level
Blue background color 2
low level
Blue background color 1
and 2 high level
Frame level 0
Frame level 1
Character level
Symbol
VCBL
VCBH
VRSL0
VRSH0
VRSL1
VRSL2
VRSH
VBK0
VBK1
VCHA
Ratings
Conditions
CVOUT: VDD1 = 5.0V,
VDD2 = 5.0V
CVOUT: VDD1 = 5.0V,
VDD2 = 5.0V
CVOUT: VDD1 = 5.0V,
VDD2 = 5.0V
CVOUT: VDD1 = 5.0V,
VDD2 = 5.0V
CVOUT: VDD1 = 5.0V,
VDD2 = 5.0V
CVOUT: VDD1 = 5.0V,
VDD2 = 5.0V
CVOUT: VDD1 = 5.0V,
VDD2 = 5.0V
CVOUT: VDD1 = 5.0V,
VDD2 = 5.0V
CVOUT: VDD1 = 5.0V,
VDD2 = 5.0V
CVOUT: VDD1 = 5.0V,
VDD2 = 5.0V
min
typ
max
Unit
(1)
1.07
V
(2)
1.27
V
(3)
1.67
V
(1)
1.67
V
(2)
1.87
V
(3)
2.27
V
(1)
1.23
V
(2)
1.43
V
(3)
1.83
V
(1)
2.37
V
(2)
2.57
V
(3)
2.97
V
(1)
1.16
V
(2)
1.36
V
(3)
1.76
V
(1)
1.52
V
(2)
1.72
V
(3)
2.12
V
(1)
2.01
V
(2)
2.21
V
(3)
2.61
V
(1)
1.50
V
(2)
1.70
V
(3)
2.10
V
(1)
2.08
V
(2)
2.28
V
(3)
2.68
V
(1)
2.65
V
(2)
2.85
V
(3)
3.25
V
Notes: (1): When the sync level = 0.8 V
(2): When the sync level = 1.0 V
(3): When the sync level = 1.4 V
The blue background color (1 or 2) is set as an option.
No. 5919-5/35
LC74775, 74775M
Timing Characteristics at Ta = –30 to +70°C, VDD1 = 5 ±0.5 V
• OSD Write (See figure 1.)
Ratings
Paremeter
Minimum input pulse width
Data setup time
Data hold time
One word write time
Symbol
tW (SCLK)
tW (CS)
Conditions
SCLK
min
typ
max
Unit
200
ns
1
µs
CS (The period when CS is high)
tSU (CS)
CS
200
ns
tSU (SIN)
SIN
200
ns
th (CS)
CS
2
µs
th (SIN)
SIN
200
ns
tword
The 8-bit data write time
4.2
µs
twt
The RAM data write time
1
µs
• PDC/VPS Write and Read (I2C timing)
Ratings
Paremeter
Symbol
Conditions
min
typ
max
100
Unit
kHz
SCL frequency
fSCL
Bus release time
tBUF
4.7
tHD: STA
4.0
µs
tLOW
4.7
µs
tHIGH
Start/hold
SCL low-level period
SCL high-level period
µs
4.0
µs
Data hold
tHD: DAT
0
µs
Data setup
tSU: DAT
250
ns
Rise time
tR
1000
ns
Fall time
tF
300
ns
Stop/setup
tSU: STO
4.0
µs
No. 5919-6/35
LC74775, 74775M
Figure 1 OSD Serial Data Input Timing
S: Start condition
P: Stop condition
Figure 2 PDC/VPS Serial Timing (I2C bus)
No. 5919-7/35
Sync
separator
data
separator
circuit
Character
output dot
clock
generator
AFC
circuit
Output control
Data output
buffer
Composite
sync signal
separation
control
Sync
discrimination
Data
slicer
circuit
8-bit latch
+
command
decoder
Serial to
parallel
converter
Timing generator
Line control
counter
Sync signal generator
Character
control
counter
Vertical display
position
detector
Vertical dot
counter
Horizontal
dot counter
Vertical size
counter
Horizontal
size counter
Horizontal
display position
detector
Vertical
display
position
register
Horizontal
display
position
register
Vertical
character
size register
Horizontal
character
size register
Display
control
register
Character output control
Background control
Video output control
Blinking and
reverse video
control circuit
Blinking and
reverse
video control
register
Decoder
Font ROM
Decoder
Display RAM
Shift register
RAM write
address
counter
LC74775, 74775M
System Block Diagram
No. 5919-8/35
LC74775, 74775M
Display Control Commands
Display control commands have an 8-bit format and are transferred using the serial input function. Commands consist of a
command identification code in the first byte and command data in the following bytes. The following commands are supported.
COMMAND0: Display memory (VRAM) write address setup command
COMMAND1: Display character data write command
COMMAND2: Vertical display start position and vertical character size setup command
COMMAND3: Horizontal display start position and horizontal character size setup command
COMMAND4: Display control setup command
COMMAND5: Display control setup command
COMMAND6: Synchronizing signal detection setup command
COMMAND7 to COMMAND12 and COMMAND18: Display control setup commands
COMMAND13 to COMMAND17: VPS/PDC control commands. These commands can only be written with the I2C bus
(the SCL and SDA pins).
Display Control Command Table
First byte
Command
Second byte
Command identification code
Data
Data
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
COMMAND0
(Write address setup)
1
0
0
0
V3
V2
V1
V0
0
0
0
H4
H3
H2
H1
H0
COMMAND1
(Character write)
1
0
0
1
0
0
0
0
at
c6
c5
c4
c3
c2
c1
c0
COMMAND2 (Vertical character size and
vertical display start position)
1
0
1
0
VS
21
VS
20
VS
11
VS
10
0
FS
VP
5
VP
4
VP
3
VP
2
VP
1
VP
0
COMMAND3 (Horizontal character size and
horizontal display start position)
1
0
1
1
HS
21
HS
20
HS
11
HS
10
0
LC
HP
5
HP
4
HP
3
HP
2
HP
1
HP
0
COMMAND4
(Display control)
1
1
0
0
0
BLK
2
BLK
1
BLK
0
BK
1
BK
0
RV
DSP
ON
COMMAND5
(Display control)
1
1
0
1
NP
1
RSH HLF
LV2 INT
BCL
CB
PH
2
PH
1
PH
0
COMMAND6
(Synchronizing signal detection)
1
1
1
0
SEL MOD
0
0
SN
3
SN
2
SN
1
SN
0
COMMAND7
(Display control)
1
1
1
1
0
COMMAND8
(Display control)
1
1
1
1
COMMAND9
(Display control)
1
1
1
COMMAND10
(Display control)
1
1
COMMAND11
(Display control)
1
COMMAND12
(Display control)
TST RAM OSC SYS
MOD ERS STP RST
NP
0
NON
INT
0
DIS
LIN
MUT
0
RN
2
RN
1
RN
0
0
0
0
0
CIN
SEL
CIN
CTL
VNP
SEL
VSP MSK MSK EGL
SEL ERS SEL
0
0
0
1
0
LNA
3
LNA
2
LNA
1
LNA LPA
0
2
LPA
1
LPA
0
1
0
0
1
0
0
LNB
3
LNB
2
LNB
1
LNB LPB
0
2
LPB
1
LPB
0
1
1
0
0
1
1
0
LNC LNC
3
2
LNC
1
LNC LPC
0
2
LPC
1
LPC
0
1
1
1
0
1
0
0
0
0
VSP
DCK
VSP
SLC
LNC MOD LNB MOD
SEL
3
SEL
2
1
1
1
1
0
1
0
1
0
0
OTD
S1
OTD
S0
HLF
INT
SEL
2
OTH
IND
COMMAND18
(Display control)
1
1
1
1
1
0
1
1
0
0
RNE
0
SJN
3
SJN
2
SJN
1
SJC
1
SJC
0
COMMAND13
(VPS/PDC control)
1
1
1
1
0
1
0
1
0
CPA CPA
2
1
CPA
0
VPM VPM VPM VPM
3
2
1
0
COMMAND14
(VPS/PDC control)
1
1
1
1
0
1
1
0
0
VMW VMW HBS
SE2 SEL
2
HBS BMS EMS DCE
1
COMMAND15
(VPS/PDC control)
1
1
1
1
0
1
1
1
0
COMMAND16
(VPS/PDC control)
1
1
1
1
1
0
0
0
0
COMMAND17
(VPS/PDC control)
1
1
1
1
1
0
0
1
0
0
ECV
15
ECV
14
ECV ECV
13
12
ECV ECV
11
5
ECP ECP
19
18
ECP
17
ECP ECP
16
15
ECP ECP
14
13
ECP
24
ECP ECP
23
22
ECP ECP
21
20
0
ECP
25
Once written, a first byte command identification code is stored until the next first byte is written. However, when the
display character data write command (COMMAND1) is written, the LC74775/M locks into the display character data
write mode, and another first byte cannot be written.
When the CS pin is set high, the LC74775/M is set to the COMMAND0 (display memory write address setup mode) state.
No. 5919-9/35
LC74775, 74775M
COMMAND0 (Display memory write address setup command)
• First byte
Contents
DA 0 to 7
Register
7
–
1
6
–
0
Command 0 identification code.
5
–
0
Display memory write address setup.
4
–
0
3
V3
State
Function
Notes
0
1
2
V2
0
1
1
V1
Display memory line address (0 to B hexadecimal)
0
1
0
V0
0
1
• Second byte
Contents
DA 0 to 7
Register
7
–
0
6
–
0
5
–
0
4
H4
3
H3
2
H2
1
H1
0
H0
State
Function
Notes
Second byte identification bit
0
1
0
1
0
Display memory column address (0 to 17 hexadecimal)
1
0
1
0
1
Note: All registers are set to 0 when the LC74775/M is reset by the RST pin.
COMMAND1 (Display character data write setup command)
• First byte
Contents
DA 0 to 7
Register
7
–
1
6
–
0
Command 1 identification code.
5
–
0
Display character data write mode setup.
4
–
1
3
–
0
2
–
0
1
–
0
0
–
0
State
Function
Notes
When this command is input, the LC74775/M
locks in the display character data write mode
until the CS pin goes high.
No. 5919-10/35
LC74775, 74775M
• Second byte
DA 0 to 7
Register
7
at
6
c6
Contents
State
Notes
Function
0
Character attribute off
1
Character attribute on
0
1
5
c5
0
1
4
c4
0
1
3
c3
Character code (00 to 7F hexadecimal)
0
1
2
1
c2
c1
0
(7EHEX: Space character)
1
(7FHEX: Transparent space character)
0
1
0
c0
0
1
Note: All registers are set to 0 when the LC74775/M is reset by the RST pin.
COMMAND2: Vertical display start position and vertical character size setup command
• First byte
Contents
DA 0 to 7
Register
7
–
6
–
0
5
–
1
4
–
3
VS21
State
1
1
VS20
VS11
0
VS10
VS20
VS21
0
1
0
0
1H/dot
2H/dot
1
1
3H/dot
1H/dot
0
1
0
1
0
Command 2 identification code.
Vertical display start position and the vertical character
size setup.
0
1
2
Notes
Function
Second line vertical character size
VS10
VS11
0
0
1H/dot
2H/dot
1
1
3H/dot
1H/dot
First line vertical character size
• Second byte
DA 0 to 7
Register
7
–
6
FS
Contents
State
0
Second byte identification bit
0
Crystal oscillator frequency: 2fsc
1
5
4
0
If VS is the vertical display start position then:
(MSB)
1
n
VS = α +H × 2 ∑ 2 VPn
0
H: The horizontal synchronization pulse period
α = 20H (525H systems)
α = 25H (625H systems)
1
3
2
Crystal oscillator frequency: 4fsc
VP5
VP4
VP3
VP2
0
Notes
Function
5
n=0
The vertical display start position is set by the
1
6 bits VP0 to VP5.
0
The weight of bit 1 is 2H.
1
1
VP1
0
1
0
VP0
0
(LSB)
1
Character display area
Note: All registers are set to 0 when the LC74775/M is reset by the RST pin.
No. 5919-11/35
LC74775, 74775M
COMMAND3 (Horizontal display start position and horizontal size setup command)
• First byte
Contents
DA 0 to 7
Register
7
–
1
6
–
0
5
–
1
4
–
3
HS21
State
1
HS20
HS11
1
HS10
VS20
VS21
0
1
0
0
1Tc/dot
2Tc/dot
1
1
3Tc/dot
1Tc/dot
0
1
0
1
0
Command 3 identification code.
Horizontal display start position and the horizontal
character size setup.
0
1
2
Notes
Function
VS10
VS11
0
0
1Tc/dot
2Tc/dot
1
1
3Tc/dot
1Tc/dot
Second line horizontal character size
First line horizontal character size
• Second byte
DA 0 to 7
Register
7
–
6
5
4
LC
Contents
State
0
Use the LC oscillator as the dot clock
1
Use the crystal oscillator as the dot clock
HP5
0
If HS is the horizontal start position then:
(MSB)
1
HS = Tc ×
0
Tc: Period of the oscillator connected to OSCIN/OSCOUT
in operating mode.
HP4
HP3
HP2
Selects the dot clock used for character
display in the horizontal direction.
5
2 ∑ 2 n HPn
n=0
0
1
2
Notes
Second byte identification bit
0
1
3
Function
0
The horizontal display start position is set
by the 6 bits HP0 to HP5.
The weight of bit 1 is 2Tc.
1
1
HP1
0
1
0
HP0
0
(LSB)
1
Note: All registers are set to 0 when the LC74775/M is reset by the RST pin.
No. 5919-12/35
LC74775, 74775M
COMMAND4 (Display control setup command)
• First byte
Contents
DA 0 to 7
Register
7
–
1
6
–
1
Command 4 identification code.
5
–
0
Display character data write setup.
4
–
0
3
TSTMOD
2
RAMERS
State
0
Normal operating mode
1
Test mode
OSCSTP
This bit must be set to 0
0
1
1
Notes
Function
Erase display RAM.(The RAM data is set to 7F hexadecimal.)
0
Do not stop the crystal and VCO oscillators
1
Stop the crystal and VCO oscillators
Valid in external synchronization mode when
character display is off
Reset all registers and turn display off
The registers are reset when the CS pin is
low, and the reset state is cleared when CS
is set high.
0
0
SYSRST
Erasing RAM takes about 500 µs. (This operation
must be executed in the DSPOFF state.)
1
• Second byte
DA 0 to 7
Register
7
–
6
5
BLK2
BLK1
Contents
State
0
Second byte identification bit
0
Character display area
1
Video display area
0
1
4
3
2
1
0
BLK0
BK1
BK0
RV
DSPON
Notes
Function
BLK0
Specifies the size for complete fill in
0
BLK1
1
0
0
Blanking off
Character size
1
1
Frame size
Complete fill in size
0
Blinking period: About 0.5 s
1
Blinking period: About 1.0 s
0
Blinking off
1
Blinking on
0
Reverse video off
1
Reverse video on
0
Character display off
1
Character display on
Changes the blanking size
Switches the blinking period
Blinking in character reverse video mode
switches the display between normal
character display and reverse video display
Note: All registers are set to 0 when the LC74775/M is reset by the RST pin.
No. 5919-13/35
LC74775, 74775M
COMMAND5 (Display control setup command)
• First byte
Contents
DA 0 to 7
Register
7
–
1
6
–
1
Command 5 identification code.
5
–
0
Display control setup.
4
–
1
3
NP1
2
1
0
NP0
NON
INT
State
Notes
Function
0
NTSC
1
PAL
0
525 lines
1
625 lines
0
Interlaced
1
Noninterlaced
Switches between NTSC and PAL
Modified by the external input signal V
Switches between interlaced and
noninterlaced video
0
External synchronization
1
Internal synchronization
Switches between external and internal
synchronization
• Second byte
DA 0 to 7
Register
7
–
6
5
4
3
2
RSHLV2
HLFINT
BCL
CB
Contents
State
0
Second byte identification bit
0
Background color level 1. (Level that is different from blue.)
1
Background color level 2. (Level that is identical to the blue level.)
0
Normal mode
1
Partial internal synchronization mode
0
Background color on
1
No background color. (Only the background level is set.)
0
Color burst signal output
1
Color burst signal output stopped
PH2
PH1
PH0
(phase)
1
0
0
0
Cyan
0
0
1
Yellow
PH1
1
0
0
PH0
1
Switches the background color signal level
Only valid in internal synchronization mode
Only valid when BCL is high
0
PH2
0
1
Notes
Function
Background color
0
1
0
Red
0
1
1
Blue
1
0
0
Cyan - blue
1
0
1
Green
1
1
0
Orange
1
1
1
Magenta
Background color specification
Note: All registers are set to 0 when the LC74775/M is reset by the RST pin.
No. 5919-14/35
LC74775, 74775M
COMMAND6 (Synchronizing signal detection setup command)
• First byte
Contents
DA 0 to 7
Register
7
–
1
6
–
1
Command 6 identification code.
5
–
1
Synchronizing signal control setup.
4
–
0
3
SEL0
State
0
1
SEL0
0
0
2
1
0
MOD0
DISLIN
MUT
Notes
Function
1
MOD0
0
SEPOUT
DAV
0
1
Sliced data width
1
0
CSYNC
1
1
ST pulse signal
0
12 lines
1
10 lines
0
Normal output
1
CVIN is cut and CVOUT is held at the pedestal level
Switches the SEPOUT (pin 19) output
Switches the number of lines displayed
CVOUT switching
• Second byte
DA 0 to 7
Register
7
–
6
RN2
Contents
State
0
RN1
0
1
4
RN0
Second byte identification bit
0
1
5
Notes
Function
0
RN2
RN1
RN0
Number of times HSYNC detected
0
0
0
0 (32)
0
0
1
4 (64)
0
1
0
8 (128)
1
0
0
16 (256)
1
3
2
SN3
SN2
0
1
SN3
SN2
SN1
SN0
Number of times HSYNC detected
0
0
0
0
0
Not output
1
1
SN1
0
1
0
SN0
External synchronizing signal detection control.
Signal absent → signal present transition
detection.
Sets the sampling period in which SYNC can
be detected continuously in the horizontal
synchronizing signal period (1H).
Values in parentheses apply when RNE0
(COM18) is 1.
0
0
0
1
32
0
0
1
0
64
0
1
0
0
128
1
0
0
0
256
0
External synchronizing signal detection
control.
Signal present → signal absent transition
detection.
Sets the sampling period in which SYNC
cannot be detected continuously in the
horizontal synchronizing signal period (1H).
1
Note: All registers are set to 0 when the LC74775/M is reset by the RST pin.
No. 5919-15/35
LC74775, 74775M
COMMAND7 (Display control setup command)
• First byte
Contents
DA 0 to 7
Register
7
–
1
6
–
1
Command 7 identification code.
5
–
1
Display control setup.
4
–
1
3
–
0
2
–
0
1
–
0
0
–
0
State
Function
Notes
Extended command 0 identification code
• Second byte
DA 0 to 7
Register
7
6
5
4
3
2
1
0
CINSEL
CINCTL
VNPSEL
VSPSEL
MSKERS
MSKSEL
EGL
Contents
State
Function
0
Second byte identification bit
0
Blank area (The logical OR of the character and frame signals)
1
Video signal display area
0
CVCR: off
1
CVCR: on
0
V falling edge detection
1
V rising edge detection
0
VSEP: about 8.9 µs (NTSC)
1
VSEP: about 17.8 µs (NTSC)
0
Mask valid
1
Mask invalid
0
3H (NTSC)
1
20H (NTSC)
0
Frame level 0 only (VBK0)
1
Two-stage frame level (VBK0 and VBK1)
Notes
CVCR on signal switching
CVCR on/off switching
Switches the V acquisition polarity in external
mode when internal V separation is used.
Switches the internal V separation period
Clears the HSYNC and VSYNK masks
Switches the VSYNC mask
Switches the frame level.
(Only valid when BLK0 is 0 and BLK1 is 1.)
Note: All registers are set to 0 when the LC74775/M is reset by the RST pin.
No. 5919-16/35
LC74775, 74775M
COMMAND8 (Display control setup command)
• First byte
Contents
DA 0 to 7
Register
7
–
1
6
–
1
Command 7 identification code.
5
–
1
Display control setup.
4
–
1
3
–
0
2
–
0
1
–
0
0
–
1
State
Notes
Function
Extended command 1 identification code
• Second byte
DA 0 to 7
Register
7
–
6
LNA3
Contents
State
0
0
1
0
5
LNA2
1
0
4
LNA1
1
0
3
LNA0
1
0
2
LPA2
1
0
1
LPA1
1
0
0
LPA0
1
Notes
Function
Second byte identification bit
LNA3 LNA2 LNA1 LNA0
Specified line
0
0
0
0
Do not change the line background
0
0
0
1
Line 1
0
0
1
0
Line 2
0
0
1
1
Line 3
0
1
0
0
Line 4
0
1
0
1
Line 5
0
1
1
0
Line 6
0
1
1
1
Line 7
1
0
0
0
Line 8
1
0
0
1
Line 9
1
0
1
0
Line 10
1
0
1
1
Line 11
1
1
–
–
Line 12
LPA2
LPA1
LPA0
0
0
0
Cyan
0
0
1
Yellow
0
1
0
Red
0
1
1
Blue
1
0
0
Cyan - blue
1
0
1
Green
1
1
0
Orange
1
1
1
Magenta
Specifies the line whose background is to be
changed.
(When the background color is specified for
the same line with LNA*, LNB*, and LNC*,
the command specified last becomes valid.
The previously specified registers (LN* and
LP*) are all cleared to 0.)
Line background color (phase)
Specifies the background color
Note: All registers are set to 0 when the LC74775/M is reset by the RST pin.
No. 5919-17/35
LC74775, 74775M
COMMAND9 (Display control setup command)
• First byte
Contents
DA 0 to 7
Register
7
–
1
6
–
1
Command 7 identification code.
5
–
1
Display control setup.
4
–
1
3
–
0
2
–
0
1
–
1
0
–
0
State
Notes
Function
Extended command 2 identification code
• Second byte
DA 0 to 7
Register
7
–
6
LNB3
Contents
State
0
0
1
0
5
LNB2
1
0
4
LNB1
1
0
3
LNB0
1
0
2
LPB2
1
0
1
LPB1
1
0
0
LPB0
1
Notes
Function
Second byte identification bit
LNB3 LNB2 LNB1 LNB0
Specified line
0
0
0
0
Do not change the line background
0
0
0
1
Line 1
0
0
1
0
Line 2
0
0
1
1
Line 3
0
1
0
0
Line 4
0
1
0
1
Line 5
0
1
1
0
Line 6
0
1
1
1
Line 7
1
0
0
0
Line 8
1
0
0
1
Line 9
1
0
1
0
Line 10
1
0
1
1
Line 11
1
1
–
–
Line 12
LPC2
LPC1
LPC0
0
0
0
Cyan
0
0
1
Yellow
0
1
0
Red
0
1
1
Blue
1
0
0
Cyan - blue
1
0
1
Green
1
1
0
Orange
1
1
1
Magenta
Specifies the line whose background is to be
changed.
(When the background color is specified for
the same line with LNA*, LNB*, and LNC*,
the command specified last becomes valid.
The previously specified registers (LN* and
LP*) are all cleared to 0.)
Line background color (phase)
Specifies the background color
Note: All registers are set to 0 when the LC74775/M is reset by the RST pin.
No. 5919-18/35
LC74775, 74775M
COMMAND10 (Display control setup command)
• First byte
Contents
DA 0 to 7
Register
7
–
6
–
1
Command 7 identification code.
5
–
1
Display control setup.
4
–
1
3
–
0
2
–
0
1
–
1
0
–
1
State
Notes
Function
1
Extended command 3 identification code
• Second byte
DA 0 to 7
Register
7
–
6
LNC3
Contents
State
0
0
1
0
5
LNC2
1
0
4
LNC1
1
0
3
LNC0
1
0
2
LPC2
1
0
1
LPC1
1
0
0
LPC0
1
Notes
Function
Second byte identification bit
LNB3 LNB2 LNB1 LNB0
Specified line
0
0
0
0
Do not change the line background
0
0
0
1
Line 1
0
0
1
0
Line 2
0
0
1
1
Line 3
0
1
0
0
Line 4
0
1
0
1
Line 5
0
1
1
0
Line 6
0
1
1
1
Line 7
1
0
0
0
Line 8
1
0
0
1
Line 9
1
0
1
0
Line 10
1
0
1
1
Line 11
1
1
–
–
Line 12
LPB2
LPB1
LPB0
Line background color (phase)
0
0
0
Cyan
0
0
1
Yellow
0
1
0
Red
0
1
1
Blue
1
0
0
Cyan - blue
1
0
1
Green
1
1
0
Orange
1
1
1
Magenta
Specifies the line whose background is to be
changed.
(When the background color is specified for
the same line with LNA*, LNB*, and LNC*,
the command specified last becomes valid.
The previously specified registers (LN* and
LP*) are all cleared to 0.)
Specifies the background color
Note: All registers are set to 0 when the LC74775/M is reset by the RST pin.
No. 5919-19/35
LC74775, 74775M
COMMAND11 (Display control setup command)
• First byte
Contents
DA 0 to 7
Register
7
–
1
6
–
1
Command 7 identification code.
5
–
1
Display control setup.
4
–
1
3
–
0
2
–
1
1
–
0
0
–
0
State
Notes
Function
Extended command 4 identification code
• Second byte
Contents
DA 0 to 7
Register
7
–
0
6
–
0
5
VSPDCK
4
VSPSLC
3
LNCSEL
2
MOD3
1
LNBSEL
0
MOD2
State
Notes
Function
Second byte identification bit
0
LC oscillator: operating
1
LC oscillator: stopped
0
VCO: operating
1
VCO: stopped
0
Normal line background color operation
1
RV characters have the background color specified by
PH* and the RV character background color is white
0
The LNCSEL = 1 setting specifications
1
RV characters have the background color specified by PH*
and characters are white
0
Normal line background color operation
1
RV characters have the background color specified by PH*
and the RV character background color is white
0
The LNBSEL = 1 setting specifications
1
RV characters have the background color specified by PH*
and characters are white
LC oscillator control
VCO control
Switches the RV mode background color for RV
specified characters in LNC* specified lines
Valid when LNCSEL is high
Switches the RV mode background color for RV
specified characters in LNB* specified lines
Valid when LNBSEL is high
Note: All registers are set to 0 when the LC74775/M is reset by the RST pin.
No. 5919-20/35
LC74775, 74775M
COMMAND12 (Display control setup command)
• First byte
Contents
DA 0 to 7
Register
7
–
1
6
–
1
Command 7 identification code.
5
–
1
Display control setup.
4
–
1
3
–
0
2
–
1
1
–
0
0
–
1
State
Notes
Function
Extended command 5 identification code
• Second byte
Contents
DA 0 to 7
Register
7
–
0
6
–
0
5
OTDCS1
4
3
OTDCS0
HLFTON
State
1
0
SEL2
OTHS
IND3
Second byte identification bit
0
OTDS1
OTDS0
Dot clock
1
0
0
LC oscillator
0
0
1
Crystal oscillator
1
1
0
VCO
0
SEL2
HLFTON
Output
1
0
0
SYNCJDG
0
2
Notes
Function
1
0
1
1
0
LOCK
1
1
SYNCDET
0
CSYNCB (sync separator)
1
HDB (slicer AFC)
0
LC oscillator
1
Crystal oscillator
Halftone
External synchronization mode dot clock setting
SYNCJDG pin (pin 8) output switching.
The halftone output line specification depends
on background color specification (the logical
OR of the 3-line specification).
External synchronization mode H input switching
Internal synchronization mode dot clock setup
Note: All registers are set to 0 when the LC74775/M is reset by the RST pin.
No. 5919-21/35
LC74775, 74775M
COMMAND18 (Display control setup command)
• First byte
Contents
DA 0 to 7
Register
7
–
1
6
–
1
Command 7 identification code.
5
–
1
Display control setup.
4
–
1
3
–
1
2
–
0
1
–
1
0
–
1
State
Notes
Function
Extended command B identification code
• Second byte
Contents
DA 0 to 7
Register
7
–
0
6
–
0
5
RNE0
4
SJNS3
State
Sync discrimination signal absent → present: normal value
1
Sync discrimination signal absent → present: value shown
in parentheses
1
0
SJNS2
1
0
2
SJNS1
1
1
0
SJCS1
SJCS0
Second byte identification bit
0
0
3
Notes
Function
SJNS3
SJNS2
SJNS1
Number of times
0
0
0
None
0
0
1
4
0
1
0
8
0
1
1
16
1
0
0
32
1
0
1
64
1
1
0
128
1
1
1
256
Changes the discrimination value for the sync
discrimination signal absent → present
transition
Setting for the noise rejection circuit used for
sync discrimination signal absent → present
transition.
The sync signal absent state is recognized
when the number of high-level signals shown
in the table is input during a 1H period.
0
SJCS1
SJCS0
PAL
NTSC
1
0
0
677 ns (1/3)
558 ns (1/2)
Sync discrimination.
0
0
1
903 ns (1/4)
838 ns (1/3)
HSYNI signal extraction clock selection.
1
1
0
450 ns (1/2)
1117 ns (1/4)
Note: All registers are set to 0 when the LC74775/M is reset by the RST pin.
No. 5919-22/35
LC74775, 74775M
COMMAND13 (VPS/PDC control setup command) I2C bus only
• First byte
Contents
DA 0 to 7
Register
7
–
1
6
–
1
Command 7 identification code.
5
–
1
Display control setup.
4
–
1
3
–
0
2
–
1
1
–
0
0
–
1
State
Notes
Function
Extended command 5 identification code
• Second byte
DA 0 to 7
Register
7
–
6
CPA2
Contents
State
0
0
1
5
CPA1
0
1
4
CPA0
0
1
0
3
VPM3
1
0
2
VPM2
1
0
1
VPM1
1
0
0
VPM0
1
Notes
Function
Second byte identification bit
CPA2
0
0
0
0
1
1
1
1
M3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CPA1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
M1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
M0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPA0
0
1
0
1
0
1
0
1
Clock
No. 1
No. 2
No. 3
No. 4
No. 5
No. 6
No. 7
No. 8
Operating mode
VPS
8/30/2 (PDC)
Automatic PDC/VPS discrimination 1
8/30/1 (UDT)
Header time 1
Header time 2
Header time 3
Header time 4
Status display 1
Status display 2
Status display 3
Status display 4
PAL Pulse
Automatic PDC/VPS discrimination 2
Automatic PDC/VPS discrimination 3
Automatic PDC/VPS discrimination 4
Data acquisition clock selection.
Shifts in multiples of 8 clock units with
respect to the data.
Slicer mode selection
Note: All registers are set to 0 when the LC74775/M is reset by the RST pin.
No. 5919-23/35
LC74775, 74775M
COMMAND14 (VPS/PDC control setup command) I2C bus only
• First byte
Contents
DA 0 to 7
Register
7
–
1
6
–
1
Command 7 identification code.
5
–
1
Display control setup.
4
–
1
3
–
0
2
–
1
1
–
1
0
–
0
State
Function
Notes
Extended command 6 identification code
• Second byte
DA 0 to 7
Register
7
–
6
5
4
3
2
VMWSE2
VMWSEL
HBS2
HBS1
Contents
State
0
Second byte identification bit
0
V mask period start - From the retrace period
1
V mask period start - From 10H before the retrace period
0
The V mask period is the retrace period
1
The V mask period is 9H
0
Clock running discrimination 1 (2 times)
1
Clock running discrimination 2 (4 times)
0
Framing code discrimination 1
1
Framing code discrimination 2 (Single bad bits are ignored)
0
Error check valid (Error checking can be turned on or
off on a per-byte basis.)
BMS
1
1
0
EMS
Function
CPOUT pin (pin 13) V mask period switching 2
CPOUT pin (pin 13) V mask period switching
Clock running discrimination count setting
Framing code discrimination selection
When set to 0, if there are no errors in bytes
for which error checking is turned on, those
bytes are written to P-S. When set to 1, all
Error check invalid (Applications can select whether data for
bytes are written to P-S regardless of the error
which an error is detected is held or writing on a per-byte basis.) status.
0
Data hold
1
Data write
(When the error bit is 0 in VPS mode.)
0
Error checking enabled for unused data bytes.
VPS: bytes 3, 4, and 6 to 10, PDC: bytes 7 to 12, header 1:
bytes 14 to 37, header 2: bytes 14 to 29, header 3: bytes 14
to 21, status 1 (3): bytes 7 to 25, status 2 (4): bytes 7 to 35
DCE
1
Notes
Error checking disabled for unused data bytes.
VPS: bytes 3, 4, and 6 to 10, PDC: bytes 7 to 12, header 1:
bytes 14 to 37, header 2: bytes 14 to 29, header 3: bytes 14
to 21, status 1 (3): bytes 7 to 25, status 2 (4): bytes 7 to 35
Specifies handling of bytes for which error
checking is set to off but in which an error
occurred when error checking is turned on
Error checking setting for unused data bytes.
Biphase (VPS), Hamming (PDC), and odd
parity (header)
Note: All registers are set to 0 when the LC74775/M is reset by the RST pin.
No. 5919-24/35
LC74775, 74775M
COMMAND15 (VPS/PDC control setup command) I2C bus only
• First byte
Contents
DA 0 to 7
Register
7
–
1
6
–
1
Command 7 identification code.
5
–
1
Display control setup.
4
–
1
3
–
0
2
–
1
1
–
1
0
–
1
State
Function
Notes
Extended command 7 identification code
• Second byte
Contents
DA 0 to 7
Register
7
–
0
6
–
0
5
ECV15
4
3
2
1
0
ECV14
ECV13
ECV12
ECV11
ECV5
State
Function
Notes
Second byte identification bit
0
Byte 15 biphase error check on (Data hold)
1
Byte 15 biphase error check off (Data write)
0
Byte 14 biphase error check on (Data hold)
1
Byte 14 biphase error check off (Data write)
0
Byte 13 biphase error check on (Data hold)
1
Byte 13 biphase error check off (Data write)
0
Byte 12 biphase error check on (Data hold)
1
Byte 12 biphase error check off (Data write)
0
Byte 11 biphase error check on (Data hold)
1
Byte 11 biphase error check off (Data write)
0
Byte 5 biphase error check on (Data hold)
1
Byte 5 biphase error check off (Data write)
Specification when the VPS data BMS bit is 0.
The item in parentheses is the specification
when the VPS data BMS bit is 1.
Note: All registers are set to 0 when the LC74775/M is reset by the RST pin.
No. 5919-25/35
LC74775, 74775M
COMMAND16 (VPS/PDC control setup command) I2C bus only
• First byte
Contents
DA 0 to 7
Register
7
–
1
6
–
1
Command 7 identification code.
5
–
1
Display control setup.
4
–
1
3
–
1
2
–
0
1
–
0
0
–
0
State
Function
Notes
Extended command 8 identification code
• Second byte
DA 0 to 7
Register
7
–
Contents
State
0
0
6
ECP19
1
0
5
ECP18
1
0
4
ECP17
1
0
3
ECP16
1
0
2
ECP15
1
0
1
ECP14
1
0
0
ECP13
1
Function
Notes
Second byte identification bit
Byte 19 Hamming error check on (Data hold)
{Bytes 44, 28, 36, 20, 32, 42, 32, and 42}
Byte 19 Hamming error check off (Data write)
{Bytes 44, 28, 36, 20, 32, 42, 32, and 42}
Specification when the PDC data BMS bit is 0.
The item in parentheses is the specification
when the BMS bit is 1.
The item in curly braces lists the odd parity
check on/off bytes for header modes 1, 2, 3,
and 4 and status mode 1, 2, 3, and 4.
Byte 18 Hamming error check on (Data hold)
{Bytes 43, 27, 35, 19, 31, 41, 31, and 41}
Byte 18 Hamming error check off (Data write)
{Bytes 43, 27, 35, 19, 31, 41, 31, and 41}
Byte 17 Hamming error check on (Data hold)
{Bytes 42, 26, 34, 18, 30, 40, 30, and 40}
Byte 17 Hamming error check off (Data write)
{Bytes 42, 26, 34, 18, 30, 40, 30, and 40}
Byte 16 Hamming error check on (Data hold)
{Bytes 41, 25, 33, 17, 29, 39, 29, and 39}
Byte 16 Hamming error check off (Data write)
{Bytes 41, 25, 33, 17, 29, 39, 29, and 39}
Byte 15 Hamming error check on (Data hold)
{Bytes 40, 24, 32, 16, 28, 38, 28, and 38}
Byte 15 Hamming error check off (Data write)
{Bytes 40, 24, 32, 16, 28, 38, 28, and 38}
Byte 14 Hamming error check on (Data hold)
{Bytes 39, 23, 31, 15, 27, 37, 27, and 37}
Byte 14 Hamming error check off (Data write)
{Bytes 39, 23, 31, 15, 27, 37, 27, and 37}
Byte 13 Hamming error check on (Data hold)
{Bytes 38, 22, 30, 14, 26, 36, 26, and 36}
Byte 13 Hamming error check off (Data write)
{Bytes 38, 22, 30, 14, 26, 36, 26, and 36}
Note: All registers are set to 0 when the LC74775/M is reset by the RST pin.
No. 5919-26/35
LC74775, 74775M
COMMAND17 (VPS/PDC control setup command) I2C bus only
• First byte
Contents
DA 0 to 7
Register
7
–
1
6
–
1
Command 7 identification code.
5
–
1
Display control setup.
4
–
1
3
–
1
2
–
0
1
–
0
0
–
1
State
Function
Notes
Extended command 9 identification code
• Second byte
Contents
DA 0 to 7
Register
7
–
0
6
–
0
5
4
3
State
Byte 25 Hamming error check on (Data hold)
1
Byte 25 Hamming error check off (Data write)
0
Byte 24 Hamming error check on (Data hold)
1
Byte 24 Hamming error check off (Data write)
0
Byte 23 Hamming error check on (Data hold)
1
Byte 23 Hamming error check off (Data write)
ECP25
ECP23
ECP22
0
ECP21
1
0
0
Specification when the PDC data BMS bit is 0.
The item in parentheses is the specification
when the BMS bit is 1.
The item in curly braces lists the odd parity
check on/off bytes for header modes 1, 2, 3,
and 4 and status mode 1, 2, 3, and 4.
ECP24
1
1
Notes
Second byte identification bit
0
0
2
Function
ECP20
1
Byte 22 Hamming error check on (Data hold)
{Bytes , , , , 35, 45, 35, and 45}
Byte 22 Hamming error check off (Data write)
{Bytes , , , , 35, 45, 35, and 45}
Byte 21 Hamming error check on (Data hold)
{Bytes , , , , 34, 44, 34, and 44}
Byte 21 Hamming error check off (Data write)
{Bytes , , , , 34, 44, 34, and 44}
Byte 20 Hamming error check on (Data hold)
{Bytes 45, 29, 37, 21, 33, 43, 33, and 43}
Byte 20 Hamming error check off (Data write)
{Bytes 45, 29, 37, 21, 33, 43, 33, and 43}
Note: All registers are set to 0 when the LC74775/M is reset by the RST pin.
No. 5919-27/35
LC74775, 74775M
PDC/VPS Output Data Format
Data is output in order starting with bit 7 of byte 1.
PDC 8/30 mode
Output data
Format 1
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Bit 7
byte 15
VPS mode
Header time mode 1 (3)
Header time mode 2 (4)
Format 2
bit 0
byte 16
bit 0
byte 11
bit 0
byte 38
1
5
2
2
2
2
2
4
3
3
3
3
3
3
4
bit 0
4
4
4
2
5
1
5
5
5
1
6
2
6
6
6
0
7
3
7
7
byte 16
bit 0
byte 18
bit 0
byte 12
bit 0
byte 39
7
byte 23
1
1
1
2
2
2
2
2
4
3
3
3
3
3
3
4
bit 0
4
4
4
2
5
1
5
5
5
1
6
2
6
6
6
0
7
3
7
7
byte 17
bit 0
byte 20
bit 0
byte 13
bit 0
byte 40
7
byte 24
1
1
1
2
2
2
2
2
4
3
3
3
3
3
3
4
bit 0
4
4
4
2
5
1
5
5
5
1
6
2
6
6
6
0
7
3
7
7
byte 18
bit 0
byte 22
bit 0
byte 14
bit 0
byte 41
7
byte 25
1
1
1
2
2
2
2
2
4
3
3
3
3
3
3
4
bit 0
4
4
4
2
5
1
5
5
5
1
6
2
6
6
6
0
7
3
7
7
byte 19
bit 0
byte 14
bit 0
byte 5
bit 0
byte 42
7
byte 26
1
1
1
2
2
2
2
2
4
3
3
3
3
3
3
4
bit 0
4
4
4
2
5
1
5
5
5
1
6
2
6
6
6
0
7
3
7
7
byte 20
bit 0
byte 24
bit 0
byte 15
bit 0
byte 43
1
1
7
byte 27
(19)
bit 0
6
1
1
1
5
2
2
2
2
2
4
3
3
3
3
3
3
4
bit 0
4
4
4
2
5
1
5
5
5
1
6
2
6
6
6
0
7
3
7
7
7
byte 25
(35)
bit 0
(18)
bit 0
5
Bit 7
1
1
6
byte 15
(34)
bit 0
(17)
bit 0
5
Bit 7
1
1
6
byte 23
(33)
bit 0
(16)
bit 0
5
Bit 7
1
1
6
byte 21
(32)
bit 0
(15)
bit 0
5
Bit 7
1
1
6
byte19
(31)
bit 0
(14)
bit 0
1
Bit 7
1
byte 22
1
byte17
(30)
bit 0
6
1
Continued on next page.
No. 5919-28/35
LC74775, 74775M
Continued from preceding page.
PDC 8/30 mode
Output data
Format 1
Byte 7
Byte 8
Byte 9
Byte 10
Bit 7
bit 0
1
byte 44
bit 0
byte 28
bit 0
1
1
(36)
1
(20)
1
5
2
2
1
2
2
4
3
3
1
3
3
3
4
1
1
4
4
2
5
1
1
5
5
1
6
1
1
6
6
0
7
1
0
7
Error
byte 11
information
12
7
1
5
2
18
13
2
2
4
3
19
14
3
3
3
4
20
5
4
4
2
5
21
15
5
5
1
6
22
0
6
6
0
7
23
0
7
7
Error
byte 22 (14)
information
23 (15)
bit 0
(37)
1
(21)
1
1
15
2
24
40 (32)
24 (16)
4
3
25
41 (33)
25 (17)
3
4
13
42 (34)
26 (18)
2
5
0
43 (35)
27 (19)
1
6
0
44 (36)
28 (20)
0
7
0
45 (37)
29 (21)
bit 0
6
1
5
2
4
3
3
4
2
5
1
6
7
byte 23
bit 0
6
1
5
2
4
3
3
4
2
5
1
6
Bit 7
7
byte 24
bit 0
6
1
5
2
4
3
3
4
2
5
1
6
Bit 7
14
byte 29
6
Bit 7
Error
information 2
bit 0
5
byte 22
bit 0
byte 45
Error
byte 38 (30)
information
39 (31)
Bit 7
byte 14
bit 0
byte 13
6
0
Byte 13
bit 0
Error
byte 16
information 1
17
Bit 7
byte 13
0
Byte 12
Header time mode 2 (4)
1
0
Byte 11
Header time mode 1 (3)
6
Bit 7
byte 21
VPS mode
Format 2
7
byte 25
bit 0
6
1
5
2
4
3
3
4
2
5
1
6
0
7
Note: A value of 1 is output for section with no output data setting.
No. 5919-29/35
LC74775, 74775M
Data is output in order starting with bit 7 of byte 1.
Status display 1 and 2: 8/30/2 - Status display 1 and 2: 8/30/1
Output data
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Status display mode 1 (3) Status display mode 2 (4)
Bit 7
byte 26
bit 0
6
(26)
1
byte 36
(36)
PAL Puls
bit 0
bit 0
1
1
5
2
2
2
4
3
3
3
3
4
4
4
2
5
5
5
1
6
6
6
0
7
7
7
bit 0
bit 8
Bit 7
byte 27
bit 0
6
(27)
1
byte 37
1
9
5
2
2
10
4
3
3
11
3
4
4
12
2
5
5
13
1
6
6
0
0
7
7
0
Bit 7
byte 28
bit 0
6
(28)
1
(37)
byte 38
(38)
bit 0
1
5
2
2
4
3
3
3
4
4
2
5
5
1
6
6
0
7
Bit 7
byte 29
bit 0
6
(29)
1
7
byte 39
(39)
bit 0
1
5
2
2
4
3
3
3
4
4
2
5
5
1
6
6
0
7
Bit 7
byte 30
bit 0
6
(30)
1
7
byte 39
(40)
bit 0
1
5
2
2
4
3
3
3
4
4
2
5
5
1
6
6
0
7
Bit 7
byte 31
bit 0
6
(31)
1
7
byte 41
(41)
bit 0
1
5
2
2
4
3
3
3
4
4
2
5
5
1
6
6
0
7
Bit 7
byte 32
bit 0
6
(32)
1
7
byte 42
(42)
bit 0
1
5
2
2
4
3
3
3
4
4
2
5
5
1
6
6
0
7
7
Continued on next page.
No. 5919-30/35
LC74775, 74775M
Continued from preceding page.
Output data
Byte 8
Byte 9
Byte 10
Byte 11
Status display mode 1 (3)
Status display mode 2 (4)
Bit 7
byte 33
bit 0
byte 43
bit 0
6
(33)
1
(43)
1
5
2
2
4
3
3
3
4
4
2
5
5
1
6
6
0
7
Byte 12
Byte 13
7
Bit 7
byte 34
bit 0
byte 44
bit 0
6
(34)
1
(44)
1
5
2
2
4
3
3
3
4
4
2
5
5
1
6
6
0
7
7
Bit 7
byte 35
bit 0
byte 45
bit 0
6
(35)
1
(45)
1
5
2
2
4
3
3
3
4
4
2
5
5
1
6
6
0
7
7
Bit 7
Error
byte 26 (26)
information 1
27 (27)
Error
byte 36 (36)
information 1
37 (37)
6
PAL Puls
5
28 (28)
38 (38)
4
29 (29)
39 (39)
3
30 (30)
40 (40)
2
31 (31)
41 (41)
1
32 (32)
42 (42)
0
33 (33)
43 (43)
Bit 7
6
Error
byte 34 (34)
information 2
35 (35)
Error
byte 44 (44)
information 1
45 (45)
5
0
0
4
0
0
3
0
0
2
0
0
1
0
0
0
0
0
Bit 7
6
5
4
3
2
1
0
Note: A value of 1 is output for section with no output data setting.
No. 5919-31/35
LC74775, 74775M
Display Screen Structure
The display consists of 12 lines of 24 characters.
Up to 288 characters can be displayed.
The number of characters that can be displayed is reduced from the 288 maximum when enlarged characters are
displayed.
Display memory addresses are specified as row (0 to 11 decimal) and column (0 to 23 decimal) addresses.
Display Screen Structure (display memory addresses)
12 Rows
24 Characters
No. 5919-32/35
LC74775, 74775M
Composite Video Signal Output Levels (internally generated levels)
CVOUT output level waveform (VDD2 = 5.00 V)
(1)
(2)
(3)
Output level
Output voltage (1) [V]
Output voltage (2) [V]
Output voltage (3) [V]
VCHA
: Character
2.65
2.85
3.25
VRSH0
: Background colors other than blue: high
2.37
2.57
2.97
VRSH1, 2
: Blue background colors 1 and 2: high
2.01
2.21
2.61
VCBH
: Color burst high
1.67
1.87
2.27
VRSL0
: Background colors other than blue: low
1.23
1.43
1.83
VRSL1
: Blue background color 1: low
1.16
1.36
1.76
VRSL2
: Blue background color 2: low
1.52
1.72
2.12
VBK1
: Frame 1
2.08
2.28
2.68
VBK0
: Frame 2
1.50
1.70
2.10
VPD
: Pedestal
1.37
1.57
1.97
VCBL
: Color burst low
1.07
1.27
1.67
VSN
: Sync
0.80
1.00
1.40
No. 5919-33/35
LC74775, 74775M
Application Circuit Examples (When used connected to a single-chip Y/C circuit)
• External system clock input
Microcontroller
• Crystal oscillator
Microcontroller
No. 5919-34/35
LC74775, 74775M
• External system clock input (with pins 3 and 4 modified in the mask options)
Microcontroller
The electrolytic capacitor connected to SYNIN must be connected with the correct polarity when a sync tip level of
1.4 VDC (CVIN input signal: sync tip = 1.4 V) is selected in the options for video signals generated with internal
synchronization.
When VDD1 is 5.0 V, the SYNIN input video signal pedestal level will be clamped to about 2.5 V.
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any and all SANYO products described or contained herein fall under strategic
products (including services) controlled under the Foreign Exchange and Foreign Trade Control Law of
Japan, such products must not be exported without obtaining export license from the Ministry of
International Trade and Industry in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of Nobemver, 1998. Specifications and information herein are
subject to change without notice.
PS No. 5919-35/35