Ordering number : EN*5537A CMOS IC LC78857V Digital Audio D/A Converter IC with On-Chip Digital Filters Preliminaly Overview Package Dimensions The LC78857V is a sigma-delta type D/A converter for use in digital audio systems. It provides both digital and analog filters on chip. unit: mm 3175A-SSOP24 [LC78857V] Features • Built-in 8x oversampling digital filters: 3-stage FIR structure (31st order, 11th order, and 3rd order filters) • Analog low-pass filter • Digital deemphasis (handles Fs = 44.1 kHz operation) • Digital attenuator • Soft muting • Supports a 384fs system clock rate. • 5-V single-voltage power supply • Fabricated in a silicon gate CMOS process. SANYO: SSOP24 Specifications Absolute Maximum Ratings at VSS = 0 V Parameter Maximum supply voltage Symbol Conditions Ratings VDD max Unit –0.3 to +7.0 V VIN –0.3 to VDD +0.3 V Output voltage VOUT –0.3 to VDD +0.3 V Operating temperature Topr –30 to +75 °C Storage temperature Tstg –40 to +125 °C Input voltage Allowable Operating Ranges at Ta = 25°C Parameter Symbol Conditions Ratings min typ max Unit Supply voltage VDD 3.5 5.5 V Input voltage TIN 0 VDD V –30 +75 °C Operating temperature Topr 5.0 SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN D3097HA (OT) No. 5537-1/11 LC78857V DC Characteristics at Ta = –30 to 75°C, VDD = 3.5 to 5.5 V, VSS = 0 V Parameter Symbol Conditions Input high-level voltage (1) VIH1 Pin 15 Input low-level voltage (1) VIL1 Pin 15 Input high-level voltage (2) VIH2 Pins 6, 7, 8, 9, 10, 11, 14, 18, and 19 Input low-level voltage (2) VIL2 Pins 6, 7, 8, 9, 10, 11, 14, 18, and 19 Output high-level voltage VOH IOH = –3 mA, pin 17 Output low-level voltage VOL IOL = 3 mA, pin 17 Ratings min typ max 0.7 VDD V 0.3 VDD Input leakage current IL VI = VSS, VDD: Pins 6, 7, 8, 9, 10, 11, 14, 15, 18, and 19 Allowable power dissipation Pd VDD = 5.0 V Unit 2.2 V V 0.8 2.4 V V –25 135 0.4 V 25 µA 200 mW AC Characteristics at Ta = –30 to 75°C, VDD = 3.5 to 5.5 V, VSS = 0 V Parameter Oscillator frequency Symbol Conditions Ratings min fX typ 169 max Unit 18.5 MHz 3.0 MHz BCLK frequency fBCX BCLK pulse width tWB BCLK rise time tBr 30 BCLK fall time tBf 30 DATA setup time tDS 20 ns DATA hold time tDH 20 ns LRCK setup time tLS 50 ns LRCK hold time tLH 50 ns 100 ns ns ns SH/EMP pulse period tSHIFT 1000 ns SH/EMP pulse width tWS 300 ns SH/EMP rise time tSr 100 SH/EMP fall time tSf 100 LAT/ND pulse width tWL 300 Latch pulse input time tLP 300 LAT/ND rise time tLr 100 ns LAT/ND fall time tLf 100 ns ns ns ns ns Timing Chart No. 5537-2/11 LC78857V Analog Characteristics at Ta = 25°C, VDD = 5.0 V Parameter Total harmonic distortion Signal-to-noise ratio Crosstalk Symbol THD+N Ratings Conditions min 1kHz, 0 dB S/N JIS-A 90 typ max 0.008 0.012 96 CT 1kHz, 0 dB 88 92 Full scale output level VFS 1 kHz, 0dB 2.8 3.0 Dynamic range DR JIS-A 84 87 Output load resistance RL Pins 2 and 23 5 Unit % dB dB 3.2 Vp-p dB kΩ Test Circuit See the application circuit example PG: Pattern generator (signal generator) Filter: Band limiting filter Block Diagram Analog lowpass filter (left channel) Analog lowpass filter (right channel) Noise shaper (left channel) Noise shaper (right channel) 8 × oversampling digital filters Test circuit PWM output circuit (right channel) Mode control circuit PWM output circuit (left channel) Timing generator Interface circuit No. 5537-3/11 LC78857V Pin Assignment Pin Functions Pin No. Symbol Function 1 AVDDL Analog system power supply (left channel) 2 OUTL 3 AGNDL 4 5 6 NC MODE Analog output (left channel) Analog system ground (left channel) No Connection Serial/parallel input mode selection 7 SH/EMP When MODE is low: Control data shift signal (serial mode) When MODE is high: Emphasis on/off switching (parallel mode) 8 LAT/ND When MODE is low: Control data latch signal (serial mode) When MODE is high: normal speed/double speed switching (parallel mode) 9 DAT/MT When MODE is low: Control data input (serial mode) When MODE is high: Soft muting control input (parallel mode) 10 BCLK Bit clock input 11 DATA Digital audio data input 12 DGND Digital system ground 13 DVDD Digital system power supply 14 LRCK LR clock input 15 XIN 16 XOUT 17 CKO Clock output (384fs) 18 INITB Initialization signal input (The IC internal state is initialized on a low input.) 19 TEST Test pin (This pin must be connected to DGND during normal operation.) 20 21 NC 22 AGNDR 23 OUTR 24 AVDDR Crystal oscillator element input Crystal oscillator element output No Connection Analog system ground (right channel) Analog output (right channel) Analog system power supply (right channel) No. 5537-4/11 LC78857V Circuit Operation The LC78857V consists of three main blocks: the digital filter block, the sigma-delta D/A converter block, and the analog filter block. [Digital Filter Block] The LC78857V performs the following calculations. • Normal speed mode: Attenuator Input Deemphas is firstorder IIR filter 31st-order FIR filter 11th-order FIR filter 3rd-order FIR filter To the sigma-delta D/A converter • Double speed mode: This mode is used, for example, when dubbing a CD to cassette tape at double speed. Although the XIN has the same frequency as normal speed mode, BCLK, LRCK, and DATA are input at twice the rate used in normal speed. Input Deemphas is firstorder IIR filter Attenuator 31st-order FIR filter 3rd-order FIR filter To the sigma-delta D/A converter fs* = double speed input = 2 × fs. [Sigma-Delta D/A Converter Block] This circuit accepts 8fs data input and outputs a 384fs 1-bit data sequence. From the digital filters Front-end interpolation 3rd-order noise shaper PWM D/A converter 1-bit output A 1-bit output B [Analog Low-Pass Filter Block] This block consists of an analog low-pass filter that consists of on-chip resistors, capacitors, and operational amplifiers. This block converts the 384fs 1-bit data streams A and B directly to an analog voltage output. 1-bit output A 1-bit output B No. 5537-5/11 LC78857V Input Setup 1. Digital audio data input The digital audio data is a 16-bit serial signal in an MSB-first two’s complement format. The 16-bit serial data is input from the DATA pin to an internal register on the rising edge of the BCLK signal, and is read in on the rising and falling edges of the LRCK signal. Digital Audio Data Input Timing 2. Mode setup The method used to set the speed (normal/double), deemphasis, and digital attenuator settings differs depending on the state of the mode pin (MODE). • When MODE is low: serial input mode In this mode, the speed (normal/double), deemphasis, and digital attenuator settings are set by inputting serial data to the DAT/MT pin. <Data Format> Attenuator data *: The SH/EMP signal may also have the form shown by the dotted line. Notes:DAT/MT and SH/EMP: These pins must be held fixed (low or high) at all times other than the data transfer period (t1 in the figure). LAT/ND: This pin must be held high at all times other than during data acquisition. • A0 (ND): Normal/double speed flag • A1 (EMP): Deemphasis flag A0 (ND) Normal/double speed A1 (EMP) Deemphasis L Normal speed L Off H Double speed H On The deemphasis function supports operation at fs = 44.1 kHz. No. 5537-6/11 LC78857V • Attenuator data The signal can be attenuated by inputting attenuation data (A2 to A9). The attenuation specified by the attenuation data is given by the following formula: 20 • log Attenuation data ———————— (dB) 128 Note: The attenuation is 0 dB when the data value is 7F (hexadecimal). However, if A9 (the MSB) is 1, the A2 to A data is ignored and the prior attenuation setting is retained. Attenuation data MSB LSB Attenuation level (dB) A9 A8 A7 A6 A5 A4 A3 A2 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 –0.137 • • • • • • • • • • • • • • • • • • • • • • • • • • • 0 0 0 0 0 0 0 1 –42.14 0 0 0 0 0 0 0 0 –∞ If the attenuation level is changed from 0 dB to –∞ dB, the IC performs a soft muting operation. The soft muting time is 1/Fs × 1024. Also, the time required to change the attenuation follows the slope of the soft muting function. If new attenuation data is input while the attenuation is changing, the attenuation level starts to change from the current level to the newly specified level at that point. Note: If the IC is initialized when the MODE pin is low, the IC is initialized with serial data values of A0 = A1 = A9 = low, and A2 to A8 = high. However, the LAT/ND must be held high during this initialization. • When MODE is high: parallel input mode In this mode, the speed (normal/double), deemphasis, and soft muting settings are specified with the LAT/ND, SH/EMP, and DAT/MT pins. It is not possible to set the attenuation data in this mode. · Normal speed/double speed setting · Deemphasis setting LAT/ND Normal/double speed SH/EMP Deemphasis L Normal speed L Off H Double speed H On The deemphasis function supports operation at fs = 44.1 kHz. · Soft muting setting The LC78857V uses the digital attenuator to implement a soft muting function. If the input level applied to the DAT/MT pin is changed from low to high, the attenuation changes from 0 dB to –∞ dB. Inversely, if the DAT/MT pin is changed from high to low, the attenuation changes from –∞ dB to 0 dB. The time required for the change is 1/fs × 1024. DAT/MT Soft muting L Off H On No. 5537-7/11 LC78857V 3. Initialization This IC requires initialization when power is first applied and for system operation switching. After the power-supply voltage has stabilized and XIN, BCLK, and LRCK have been supplied, initialization is achieved by holding the INITB pin at the low level for at least one LRCK period as shown in the figure below. When INITB is low, the digital filter outputs and the noise shaper (sigma-delta D/A converter) internal states are all set to 0, and the analog outputs (OUTL and OUTR) go to the zero cross level. Supply voltage At least 1 LRCK period System Clock The LC78857V operates from a 384fs system clock. Crystal Crystal: 16.9344 MHz when fs = 44.1 kHz The 384fs system clock is generated using a crystal oscillator circuit consisting of a crystal element, resistors, and capacitors as shown in the figure. Optimal values for the resistors and capacitances depend on the peripheral circuits and other conditions. The sigma-delta D/A converter is a sensitive circuit, and the analog characteristics are strongly influenced by the quality of the waveform (e.g. its jitter characteristics) of the system clock input to the XIN pin. When an external signal is input as the system clock, adequate care must be taken to assure the quality of this signal's waveform. · CKO: Outputs a clock signal with the same frequency as the signal input to the XIN pin. Attenuation - dB Digital Filter Characteristics 1. Frequency characteristics · Normal speed (deemphasis off) Sampling frequency, fs No. 5537-8/11 LC78857V Attenuation - dB · Double speed (deemphasis off) Sampling frequency, fs—Hz Attenuation - dB 2. Deemphasis on pass band characteristics · Normal speed (deemphasis on) Frequency—Hz Attenuation - dB · Double speed (deemphasis on) Frequency—Hz No. 5537-9/11 LC78857V Sample Application Circuit Second order active low-pass filter Notes: · All DVDD nodes in the circuit diagram must be connected to the digital system power supply, and all AVDD nodes must be connected to the analog system power supply. · Since latchup may occur if there is a discrepancy in the times at which the DVDD and AVDD voltages are applied, applications must be designed so that there is no time difference between the points when these voltages are applied. · If there is a potential difference between the DVDD and AVDD voltages, it must not exceed 0.3 V. · The application circuit example is an actual application circuit. Appropriate band limiting filters, which prevent adverse influence of band noise, are required to acquire the analog characteristics listed in the electrical characteristics. No. 5537-10/11 LC78857V Power Supply Timing • The analog system power supplies (AVDDL and AVDDR) and the digital system power supply (DV DD) must be applied and cut at the same time. • If time lags between these power supplies are unavoidable, the timing must meet one of the following two conditions. (1) The power on (and power off) time lag must be under 3 ms as shown in figure 1. (2) If the time lag must be over 3 ms, then the rise time for the first power supply to be powered on (or powered off) must exceed 5 ms, and furthermore, the time difference must exceed 50 ms as shown in figure 2. Under 3 ms Under 3 ms Figure 1 Over 5 ms Under 50 ms Over 5 ms Under 50 ms Figure 2 ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1997. Specifications and information herein are subject to change without notice. PS No. 5537-11/11