Ordering number : EN*5128A CMOS LSI LC78856M, 78856V Built-in Digital Filter D/A Converters for Digital Audio Preliminaly Overview Package Dimensions The LC78856M and LC78856V are ∑∆-type digital-audio D/A converter circuits with built-in digital filters. unit: mm 3091A-MFP28 Features • • • • • • • • [LC78856M] 8× oversampling digital filter Digital de-emphasis (supports fs = 44.1 kHz) Soft muting Double speed support Support for a 384fs system clock PWM outputs 5 V single-voltage power supply Si-gate CMOS process SANYO: MFP28 unit: mm 3191-SSOP30 [LC78856V] SANYO: SSOP30 Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Symbol Conditions Ratings Unit Maximum supply voltage VDD max –0.3 to +7.0 V Maximum input voltage VIN max –0.3 to VDD + 0.3 V VOUT max Maximum output voltage –0.3 to VDD + 0.3 V Operating temperature Topr –30 to +75 °C Storage temperature Tstg –40 to +125 °C SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 53096HA (OT)/62095HA (OT) No. 5128-1/8 LC78856M, 78856V Allowable Operating Ranges at Ta = –30 to +75°C Parameter Symbol Conditions Ratings min typ Unit max Supply voltage VDD 3.0 5.5 V Input voltage VIN 0 VDD V DC Characteristics at Ta = –30 to +75°C, VDD = 4.5 to 5.5 V, VSS = 0 V Parameter Symbol Conditions Input high-level voltage (1) VIH1 The XIN pin Input low-level voltage (1) VIL1 The XIN pin Input high-level voltage (2) VIH2 Pins other than the XIN pin Input low-level voltage (2) VIL2 Pins other than the XIN pin Output high-level voltage VOH IOH = –1 µA Output low-level voltage VOL IOL = 1 µA Power dissipation Pd VDD = 5.0 V Ratings min typ Unit max 0.7 VDD V 0.3 VDD 2.2 V V 0.8 VDD – 0.1 V V 140 0.1 V 200 mW DC Characteristics at Ta = –30 to +75°C, VDD = 4.5 to 5.5 V, VSS = 0 V Parameter Oscillator frequency Symbol Conditions Ratings min fX typ 16.9 Unit max 18.5 MHz 2.4 MHz BCLK frequency fBCX BCLK pulse width tWB 100 ns Data setup time tDS 20 ns Data hold time tDH 20 ns LRCK setup time tLS 50 ns LRCK hold time tLH 50 ns Timing Chart Analog Characteristics at Ta = 25°C, VDD = 5.0 V Parameter Total harmonic distortion Signal-to-noise ratio Symbol THD + N Conditions f = 1 kHz, 0 dB Ratings min typ max Unit 0.005 % 100 dB f = 1 kHz, 0 dB 98 dB JIS-A 94 dB S/N JIS-A Crosstalk CT Dynamic range DR No. 5128-2/8 LC78856M, 78856V Block Diagram Filter Characteristics Standard Speed (de-emphasis off) Double Speed (de-emphasis off) No. 5128-3/8 LC78856M, 78856V Pin Assignments No. 5128-4/8 LC78856M, 78856V Pin Functions SSOP MFP Symbol 1 1 RSTB Reset input (A low-level input resets the LSI internal circuits.) Function 2 2 CNT1 Emphasis on/off switching input 3 3 CNT2 Standard speed/double speed switching input 4 4 CNT3 Soft mute input 5 5 BCLK Bit clock input 6 6 LRCK LR clock input 7 7 DATA Digital audio data input 10 8 MODE 11 9 CKO 12 10 XVDD 13 11 XIN Input format setting Clock output Oscillator amplifier power supply Oscillator amplifier input 14 12 XOUT Oscillator amplifier output 15 13 XGND Oscillator amplifier ground 16 14 DGND 17 15 MRO Right channel mute signal output 18 16 TEST Test pin (Must be tied low in normal operation.) 19 17 AVDD4 Analog system power supply 20 18 OUTRA Right channel output A Digital system ground 21 19 AGND2 Analog system ground 22 20 OUTRB Right channel output B 23 21 AVDD3 Analog system power supply 24 22 AVDD2 Analog system power supply 25 23 OUTLB Left channel output B 26 24 AGND1 Analog system ground 27 25 OUTLA Left channel output A 28 26 AVDD1 29 27 MLO Left channel mute signal output 30 28 DVDD Digital system power supply Analog system power supply Operating Description The LC78856M and LC78856V internal circuits can be roughly divided into the digital filter block and the 1-bit D/A converter block. [Digital Filter Block] 1. Standard Speed The LC78856M and LC78856V implements 8× oversampling using three FIR filters: a 43rd-order filter, an 11thorder filter, and a 3rd-order filter. A 1st-order IIR filter is used for de-emphasis. 2. Double Speed Double-speed playback is used, for example, for dubbing CDs to audio tape at double speed. Here, the same frequency is used for XIN, but BCLK, LRCK and DATA are input at twice the rates used in standard-speed playback. After de-emphasis is applied with a 1st-order IIR filter, the signal is 4× oversampled using a 43rd-order FIR filter and a 3rd-order FIR filter. No. 5128-5/8 LC78856M, 78856V 3. One-Bit D/A Converter Block The 1-bit D/A converter accepts 8fs data input and outputs a 384fs 1-bit data stream. LC78856M/V Inputs 1. Input Data Format • Format 1 (MODE = high) • Format 2 (MODE = low) 2. Control Signals (CNT1 to CNT3) Symbol CNT1 Function Emphasis switching CNT2 Standard speed/double speed CNT3 Soft mute L H Off On Standard speed Double speed Off On 3. Initialization The LC78856M and LC78856V requires initialization when power is first applied and when settings are changed. The LC78856M and LC78856V is initialized by setting the RSTB pin low. The length of the low-level period must extend 1 µs beyond the point where the XIN input is applied. When RSTB is low, all digital filter and noise shaper internal data is set to 0, and the D/A converter outputs an analog 0. No. 5128-6/8 LC78856M, 78856V LC78856M/V Outputs 1. CKO CKO outputs a clock signal with the same frequency as the signal input to the XIN pin. 2. MLO, MRO These pins output a high level when either the attenuator coefficient has become 0, or when the corresponding channel data has been 0 for 213 or more cycles. 3. OUTLA, OUTLB, OUTRA, OUTRB These four pins produce outputs in synchronization with the XIN clock. High-precision analog signals can be acquired by differentially amplifying the output signals and passing that result through an LPF. The figure below shows a sample circuit structure. Sample Output Circuit Structure No. 5128-7/8 LC78856M, 78856V Sample Application Circuit ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1997. Specifications and information herein are subject to change without notice. No. 5128-8/8