SANYO LC86P5420

Ordering number : ENN*6730
LC86P5420
CMOS IC
LC86P5420
8-Bit Single Chip Microcontroller
with the One-Time Programmable PROM
Preliminary
Overview
The LC86P5420 is a CMOS 8-bit single chip microcontroller with one-time PROM for the LC865500 / LC865400
series.
This microcontroller has the function and the pin description of the LC865500 / LC865400 series mask ROM
version, and the 20K-byte PROM.
Features
(1) Option switching by PROM data
The option function of the LC865400 series can be specified by the PROM data.
The LC86P5420 can be checked the functions of the trial pieces using the mass production board.
(2) Internal one-time PROM capacity
: 20736 bytes
(3) Internal RAM capacity
:
512 bytes
Mask ROM version
LC865520
LC865516
LC865512
LC865508
LC865504
LC865412
LC865408
LC865404
PROM capacity
20480 bytes
16384 bytes
12288 bytes
8192 bytes
4096 bytes
12288 bytes
8192 bytes
4096 bytes
RAM capacity
512 bytes
512 bytes
512 bytes
512 bytes
512 bytes
224 bytes
224 bytes
224 bytes
(4) Operating supply voltage
: 4.5V to 6.0V
(5) Instruction cycle time
: 1.0µs to 366µs
(6) Operating temperature
: -30°C to +70°C
(7) The pin and the package compatible with the LC865400 series mask ROM devices
(8) Applicable mask ROM version
: LC865520 / LC865516 / LC865512 / LC865508 / LC865504
LC865412 / LC865408 / LC865404
(9) Factory shipment
: DIP42S, QFP48E
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft's
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
Ver. 2.00
31395
13001 RM (IM) FS No.6730-1/22
LC86P5420
Notice for use
The LC86P5420 is provided for the first release and small shipping of the LC865500 / LC865400 series.
At using, take notice of the followings.
(1) A point of difference the LC86P5420 and the LC865500 / LC865400 series
Item
Operation after reset
releasing
Operating supply
voltage range (VDD)
Power dissipation
LC86P5420
The option is specified by degrees
until 3ms after going to a 'H' level
to the reset terminal. The program
is executed from 00H of the
program counter.
4.5V to 6.0V
LC865520 / 16 / 12 / 08 / 04 LC865412 / 08 / 04
The program is executed from 00H of the
program counter immediately after going
to a 'H' level to the reset terminal.
2.5V to 6.0V
Refer to 'electrical characteristics' on the semiconductor news.
The LC86P5420 functions same as the followings while resetting ; LC865520 / 16 / 12 / 08 / 04, LC865412
/ 08 / 04.
The LC86P5420 uses 256 bytes that is addressed on 7F00H to 7FFFH in the program memory as the
option configulation data area.
•A kind of the option corresopnding of the LC86P5420
A kind of option
Input / output form of
input / output ports
Pins, Circuits
Port 0
Port 1
*1
Port 3
Contents of the option
1. N-channel open drain output
2. CMOS output
*1
1. Pull-up MOS Tr. provided
2. Pull-up MOS Tr. not provided
*2
1. Input
: Programmable pull-up MOS Tr.
Output
: N-channel open drain
2. Input
: Programmable pull-up MOS Tr.
Output
: CMOS
1. Input
: No Programmable pull-up
MOS Tr.
Output
: N-channel open drain
2. Input
: Programmable pull-up MOS Tr.
Output
: CMOS
*1
*1) Specified in bit
*2) Specified in nibble unit. Pull-up MOS Tr. is not provided in N-channel open drain output port.
(2) Option
The option data is created by the option specified program "SU86K.EXE". The created option data is
linked to the program area by the linkage loader "L86K.EXE".
No.6730-2/22
LC86P5420
(3) ROM space
The LC86P5420 and LC865500 / LC865400 series use 256 bytes that is addressed on 7F00H to
7FFFH in the program memory as the option specified data area. These program memory capacity are
20480 bytes that is addressed on 0000H to 4FFFH.
7FFFH
7F00H
Option Data
area 256 bytes
Option Data Area
Option Data Area
Option Data Area
Option Data Area
Program Area
20K bytes
Program Area
16K bytes
Program Area
12K bytes
Program Area
08K bytes
Program Area
04K bytes
LC865520
LC865516
LC865512
LC865412
LC865508
LC865408
LC865504
LC865404
6FFFH
5FFFH
4FFFH
3FFFH
2FFFH
1FFFH
0FFFH
0000H
(4) Ordering information
1. When ordering the identical mask ROM and PROM devices simultaneously.
Provide an EPROM containing the target memory contents together with the separate order forms for
each of the mask ROM and PROM versions.
2. When ordering a PROM device.
Provide an EPROM containing the target memory contents together with an order form.
How to use
(1) Create a programming data for LC86P5420
Programming data for EPROM of the LC86P5420 is required.
Debugged evaluation file (EVA file) must be converted to an INTEL-HEX formatted file (HEX file) with file
converter program, EVA2HEX.EXE. The HEX file is used as the programming data for the LC86P5420.
(2) How to program for the EPROM
The LC86P5420 can be programmed by the EPROM programmer with attachment ; W86EP5420D,
W86EP5420Q.
• Recommended EPROM programmer
Productor
Advantest
Andou
AVAL
Minato electronics
EPROM programmer
R4945, R4944, R4943
AF-9704
PKW-1100, PKW-3000
MODEL1890A
• "27512 (Vpp=12.5V) Intel high speed programming" mode available. The address must be set to
"0000H to 7FFFH" and a jumper (DASEC) must be set to 'OFF' at programming.
No.6730-3/22
LC86P5420
(3) How to use the data security function
"Data security" is the disabled function to read the data of the EPROM.
The following is the process in order to execute the data security.
1. Set 'ON' the jumper of attachment.
2. Program again. Then the EPROM programmer displays the error. The error means normally
activity of the data security. It is not a trouble of the EPROM programmer or the LSI.
Notes
• Data security is not executed when the data of all address have 'FFH' at the sequence 2 above.
• The programming by a sequential operation "BLANK=>PROGRAM=>VERIFY" cannot be executed
data security at the sequence 2 above.
• Set 'OFF' to the jumper after executing the data security.
Data security
Data security
Not data security
W86EP5420D
Not data security
W86EP5420Q
No.6730-4/22
LC86P5420
Pin Assignment
•DIP42S
P00
P01
P02
1
42
2
41
3
40
P03
P04
P05
P06
P07
P70/INT0
RES
XT1/P74
XT2/P75
VSS
CF1
CF2
VDD
4
39
5
38
6
37
7
36
8
35
9
34
10
33
11
32
12
31
13
30
14
29
15
28
16
27
17
26
18
25
19
24
20
23
21
22
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P17/PWM0
P16/BUZ
P15/SCK1
P14/S11/SB1
P13/SO1
P12/SCK0
P11/SI0/SB0
P10/SO0
P36
P35
P34
P33
P32
P31
P30
P73/INT3/T0IN
P72/INT2/T0IN
P71/INT1
P87/AN7
P86/AN6
P85/AN5
ILC00019
Package Dimension
(unit : mm)
3025B
42
0.25
15.24
13.8
22
1
21
0.51min 4.25
3.8 5.1max
37.9
0.95
0.48
1.78
1.15
SANYO : DIP-42S(600mil)
No.6730-5/22
LC86P5420
Pin Assignment
P33
P32
P31
P30
P73 / INT3 / T0IN
28
27
26
25
P34
31
NC
P35
32
29
P36
33
30
P11 / SI0 / SB0
P10 / SO0
34
P12 / SCK0
35
36
•QFP48E
44
17
P84 / AN4
P02
45
16
P83 / AN3
P03
46
15
P82 / AN2
P04
47
14
P81 / AN1
NC
48
13
P80 / AN0
VDD
CF2
CF1
12
NC
P01
11
18
9
10
43
VSS
P85 / AN5
P00
8
19
XT2 / P75
42
7
P86 / AN6
NC
NC
20
6
41
XT1 / P74
P87 / AN7
P17 / PWM0
5
21
4
40
RES
P71 / INT1
P16 / BUZ
P70 / INT0
22
3
39
P07
P72 / INT2 / T0IN
P15 / SCK1
2
NC
23
1
24
38
P06
37
P05
P13 / SO1
P14 / SI1 / SB1
*NC pin must not connect to anything.
ILC00020
Package Dimension
(unit : mm)
3156
17.2
1.6
14.0
1.5
0.35
1.6
0.15
37
24
1.0
14.0
1.5
1.5
25
36
13
48
12
1
0.8
3.0max
1.5
17.2
1.0
0.1
2.7
15.6
SANYO : QIP-48E
No.6730-6/22
LC86P5420
System Block Diagram
Interrupt Control
IR
Stand-by Control
RC
X'tal
A14--A0
D7--D0
TA
CE
OE
DASEC
EPROM
Control
Clock
Generator
CF
PLA
EPROM(20KB)
Base Timer
Bus Interface
SIO0
Port 1
SIO1
Port 3
Timer 0
Port 7
Timer 1
Port 8
PC
ACC
B Register
C Register
ALU
ADC
INT0 to 3
Noise Filter
PSW
RAR
RAM
Stack Pointer
Port 0
Watchdog Timer
ILC00035
No.6730-7/22
LC86P5420
Pin Description
Pin name I / O
Function description
Option
VSS
Power pin (-)
VDD
Power pin (+)
PORT0
I / O •8-bit input / output port
•Pull-up resistor :
P00 - P07
Input / output in nibble units
Provided / Not provided
•Input for port 0 interrupt
(specify every 4-bit)
•Input for HOLD release
•Output form :
•15V withstand at N-channel open
CMOS / N-channel open drain
drain output
(specify in bit)
PORT1
I / O •8-bit input / output port
•Output form :
P10 - P17
Input / output can be specified
CMOS / N-channel open drain
in bit unit.
(specify in bit)
•Other pin functions
P10 SIO0 data output
P11 SIO0 data input /
bus input / output
P12 SIO0 clock input / output
P13 SIO1 data output
P14 SIO1 data input /
bus input / output
P15 SIO1 clock input / output
P16 Buzzer output
P17 Timer1 (PWM0) output
PORT3
I / O •7-bit input / output port
•Pull-up resistor :
P30 - P36
Input / output in bit unit
Provided / Not provided
•15V withstand at N-channel open •Output form :
drain output
CMOS / N-channel open drain
PORT7
•4-bit input / output port
Input / output in bit unit
•2-bit input port
•Other pin functions
P70 - P73 I / O P70 : INT0 input / HOLD release
input / N-channel Tr. output for
watchdog timer
P74, P75
I P71 : INT1 input / HOLD release input
P72 : INT2 input / timer 0 event input
P73 : INT3 input with noise filter /
timer 0 event input
P74 : Input pin XT1 for 32.768kHz
crystal oscillation
P75 : Output pin XT2 for 32.768kHz
crystal oscillation
•Interrupt received form,
vector address
rising falling rising high
low vector
&
level level
falling
INT0 enable enable disable enable enable 03H
INT1 enable enable disable enable enable 0BH
INT2 enable enable enable disable disable 13H
INT3 enable enable enable disable disable 1BH
PROM mode
Data line
D0 to D7
PROM control
signals
•DASEC (*1)
•OE (*2)
•CE (*3)
No.6730-8/22
LC86P5420
Pin name I / O
Function description
Option
PROM mode
PORT8
P80 - P83
I •4-bit input port
TA (*4)
P84 - P87 I / O •4-bit input / output port
Input / output can be specified in
bit unit
•Other function
AD input port (AN7 to AN0)
I
Reset
pin
RES
XT1 / P74 I •Input pin for the 32.768kHz cyrstal
oscillation
•Other function
XT1 : Input port P74
In case of non use, connect to VDD
XT2 / P75 O •Output pin for the 32.768kHz
crystal oscillation
•Other function
XT2 : Input port P75
In case of non use, connect to VDD
at using as port or unconnect at using
as oscillation.
CF1
I Input pin for the ceramic resonator
oscillation
CF2
O Output pin for the ceramic resonator
oscillation
■ All of port options except the pull-up resistor option of Port 0 can be specified in a bit unit.
*1
*2
*3
*4
Memory select input for data security
Output enable input
Chip enable input
TA---> PROM control signal input
No.6730-9/22
LC86P5420
1. Absolute Maximum Ratings at VSS= 0V and Ta=25°C
Parameter
Supply voltage
Input voltage
Input / output
voltage
High
Level
output
current
Low
Level
output
current
Peak
output
current
Total
output
current
Peak
output
current
Total
output
current
Power
dissipation
(max.)
Operating
temperature
range
Storage
temperature
range
Symbol
Pins
VDDMAX VDD
VI(1)
•Ports 74, 75
•Ports 80, 81, 82, 83
•RES
VIO(1)
•Port 1
•Ports 70, 71, 72, 73
•Ports 84, 85, 86, 87
•Ports 0,3 at CMOS
output option
VIO(2)
Ports 0, 3 at N-ch
open drain output
option
IOPH
•Ports 0, 1, 3
•Ports 71, 72, 73
•Ports 84, 85, 86, 87
∑IOAH(1) Ports 0, 1
Conditions
VDD
CMOS output
At each pins
The total all
pins
∑IOAH(2) Port 3
The total all
pins
∑IOAH(3) •Ports 71, 72, 73
The total all
•Ports 84, 85, 86, 87 pins
IOPL(1)
Ports 0, 1, 3
At each pins
IOPL(2)
•Ports 70, 71, 72, 73 At each pins
•Ports 84, 85, 86, 87
∑IOAL(1) Ports 0, 1, 70
The total all
pins
∑IOAL(2) Port 3
The total all
pins
∑IOAL(3) •Ports 71, 72, 73
The total all
•Ports 84, 85, 86, 87 pins
Pd max (1) DIP42S
Ta=-30 to +70°C
Pd max (2) QFP48E
Ta=-30 to +70°C
VDD [V]
min.
-0.3
-0.3
Ratings
typ.
max.
+7.0
VDD+0.3
-0.3
VDD+0.3
-0.3
15
-10
unit
V
mA
-30
-15
-10
20
15
60
40
20
630
410
mW
°C
Topg
-30
70
Tstg
-65
150
No.6730-10/22
LC86P5420
2. Recommended Operating Range at Ta= -- 30°C to +70°C, VSS=0V
Parameter
Symbol
Pins
Conditions
VDD [V]
min.
4.5
Operating
supply
voltage range
HOLD voltage
VDD
VDD
0.98µs≤ tCYC
tCYC≤400µs
VHD
VDD
Input high
voltage
VIH(1)
Port 0 at CMOS
output
Port 0 at N-ch
open drain output
option.
•Port 1
•Ports 72, 73
•Port 3 at CMOS
output
Port 3 at N-ch
open drain output
option.
•Port 70
Port input /
interrupt
•Port 71
•RES
Port 70
Watchdog timer
•Port 8
•Ports 74, 75
Port 0 at CMOS
output option
Port 0 at N-ch
open drain output
option.
•Ports 1, 3
•Ports 72, 73
•Port 70
Port input /
interrupt
•Port 71
•RES
Port 70
Watchdog timer
•Port 8
•Ports 74, 75
RAMs and
2.0
Registers hold
voltage at HOLD
mode.
Output disable 4.5 to 6.0 0.33VDD
+1.0
Output disable 4.5 to 6.0 0.75VDD
VIH(2)
VIH(3)
VIH(4)
VIH(5)
VIH(6)
VIH(7)
Input low
voltage
VIL(1)
VIL(2)
VIL(3)
VIL(4)
VIL(5)
VIL(6)
Operation
cycle time
tCYC
Ratings
typ.
max.
6.0
unit
V
6.0
VDD
13.5
Output disable 4.5 to 6.0 0.75VDD
VDD
Output disable 4.5 to 6.0 0.75VDD
13.5
Output disable 4.5 to 6.0 0.75VDD
VDD
Output disable
4.5 to 6.0 0.9VDD
VDD
Output disable 4.5 to 6.0 0.75VDD
Using as port
Output disable 4.5 to 6.0 VSS
VDD
0.2VDD
Output disable 4.5 to 6.0
VSS
0.25VDD
Output disable 4.5 to 6.0
VSS
0.25VDD
Output disable 4.5 to 6.0
VSS
0.25VDD
Output disable 4.5 to 6.0
VSS
Output disable 4.5 to 6.0
Using as port
4.5 to 6.0
VSS
0.8VDD
-1.0
0.25VDD
0.98
400
µs
No.6730-11/22
LC86P5420
Parameter
Symbol
Pins
Conditions
VDD [V]
Oscillation fre- FmCF(1)
CF1, CF2
•6MHz (ceramic 4.5 to 6.0
quency range
resonator oscil(Note 1)
lation)
•Refer to figure 1
FmCF(2)
CF1, CF2
•3MHz (ceramic 4.5 to 6.0
resonator oscillation)
•Refer to figure 1
FmRC
RC oscillation 4.5 to 6.0
FsXtal
XT1, XT2
•32.768kHz
4.5 to 6.0
(crystal oscillation)
•Refer to figure 2
Oscillation
tmsCF(1)
CF1, CF2
•6MHz (ceramic 4.5 to 6.0
stable time
resonator oscilperiod
lation)
(Note 1)
•Refer to figure 3
tmsCF(2)
CF1, CF2
•3MHz (ceramic 4.5 to 6.0
resonator oscillation)
•Refer to figure 3
tssXtal
XT1, XT2
•32.768kHz
4.5 to 6.0
(crystal oscillation)
•Refer to figure 3
(Note 1) The oscillation constant is shown on table 1 and table 2.
min.
5.88
Ratings
typ.
6
max.
6.12
2.94
3
3.06
0.3
0.8
32.768
3.0
0.05
0.50
0.10
1.00
1.00
1.50
unit
MHz
kHz
ms
s
No.6730-12/22
LC86P5420
3. Electrical Characteristics at Ta= -- 30°C to +70°C, VSS=0V
Parameter
Input high
current
Symbol
IIH(1)
IIH(2)
IIH(3)
IIH(4)
Input low
current
IIL(1)
IIL(2)
IIL(3)
Output high
voltage
VOH(1)
VOH(2)
Output low
voltage
Pull-up MOS
Tr. resistor
VOL(1)
VOL(2)
VOL(3)
VOL(4)
Rpu
Hysteresis
voltage
VHIS
Pin
capacitance
CP
Ratings
VDD [V]
min.
typ.
Ports 0, 3 of Open •Output disable 4.5 to 6.0
drein output
•VIN=13.5V
(including off-leak
current of the
output Tr.)
•Port 0 without
•Output disable 4.5 to 6.0
pull-up MOS Tr. •Pull-up MOS Tr.
•Ports 1, 3
OFF.
•Ports 70, 71, 72, 73 •VIN=VDD
•Port 8
(including off-leak
current of the
output Tr.)
VIN=VDD
4.5 to 6.0
RES
VIN=VDD
4.5 to 6.0
Ports 74, 75
at using as port
•Ports 1, 3,
•Output disable 4.5 to 6.0
-1
•Port 0 without
•Pull-up MOS Tr.
pull-up MOS Tr. OFF.
•Ports 70, 71, 72, 73 •VIN=VSS
•Port 8
(including off-leak
current of the
output Tr.)
VIN=VSS
4.5 to 6.0
-1
RES
VIN=VSS
4.5 to 6.0
-1
Ports 74, 75
at using as port
Ports 0, 1, 3
IOH=-1.0mA
4.5 to 6.0 VDD-1
of CMOS output
•Ports 71, 72, 73
IOH=-0.1mA
4.5 to 6.0 VDD-0.5
•Ports 84, 85, 86, 87
Ports 0, 1, 3
IOL=10mA
4.5 to 6.0
IOL=1.6mA
4.5 to 6.0
•Ports 71, 72, 73
IOL=1.6mA
4.5 to 6.0
•Ports 84, 85, 86, 87
Port 70
IOL=1.0mA
4.5 to 6.0
•Ports 0, 1, 3
VOH=0.9 VDD 4.5 to 6.0
15
40
•Ports 70, 71, 72, 73
•Ports 84, 85, 86, 87
•Port 1
Output disable 4.5 to 6.0
0.1VDD
•Ports 70, 71, 72, 73
•RES
All pins
•f=1MHz
4.5 to 6.0
10
Unmeasurement
terminals for
input are set to
VSS level.
•Ta=25°C
Pins
Conditions
max.
5
unit
µA
1
1
1
V
1.5
0.4
0.4
0.4
70
kΩ
V
pF
No.6730-13/22
LC86P5420
4. Serial Input / Output Characteristics at Ta=-30°C to +70°C, VSS= 0V
Serial input
Serial output
Cycle
Low
level
width
High
level
pulse
width
Cycle
Low
level
pulse
width
High
level
pulse
width
Data set-up
time
Data hold
time
Output clock
Serial clock
Input clock
Parameter
Symbol
tCKCY(1)
tCKL(1)
Pins
SCK0, SCK1
tCKH(1)
tCKCY(2)
SCK0, SCK1
tCKL(2)
tCKH(2)
tICK
VDD [V]
Refer to figure 5 4.5 to 6.0
4.5 to 6.0
min.
2
1
4.5 to 6.0
1
•Use pull-up
4.5 to 6.0
resistor (1kΩ)
when open drain
output.
4.5 to 6.0
•Refer to figure 5
2
•SI0, SI1
•SB0, SB1
•SO0, SO1
•SB0, SB1
•Data set-up to 4.5 to 6.0
SCK0, 1
•Data hold from 4.5 to 6.0
SCK0, 1
•Refer to figure 5
•Use pull-up
4.5 to 6.0
resistor (1kΩ)
when open drain
output.
•Data hold from 4.5 to 6.0
SCK0, 1
•Refer to figure 5
Ratings
typ.
max.
unit
tCYC
1 / 2 tCKCY
4.5 to 6.0
tCKI
Output delay tCKO(1)
time
(Serial clock
is extrnal
clock)
Output delay tCKO(2)
time
(Serial clock
is internal
clock)
Conditions
1 / 2 tCKCY
µs
0.1
0.1
7 / 12 tCYC
+0.2
1 / 3 tCYC
+0.2
No.6730-14/22
LC86P5420
5. Pulse Input Conditions at Ta=-30°C to +70°C , VSS = 0V
Parameter
High / low
level pulse
width
Symbol
Pins
tPIH(1)
tPIL(1)
•INT0, INT1
•INT2 / T0IN
tPIH(2)
tPIL(2)
INT3 / T0IN
(The noise
rejection clock
select to 1 / 1.)
INT3 / T0IN
(The noise
rejection clock
select to 1 / 16.)
INT3 / T0IN
(The noise
rejection clock
select to 1 / 64.)
RES
tPIH(3)
tPIL(3)
tPIH(4)
tPIL(4)
tPIL(5)
Conditions
VDD [V]
•Interrupt accept- 4.5 to 6.0
able
•Timer0-countable
•Interrupt accept- 4.5 to 6.0
able
•Timer0-countable
min.
1
•Interrupt accept- 4.5 to 6.0
able
•Timer0-countable
32
•Interrupt accept- 4.5 to 6.0
able
•Timer0-countable
128
Reset acceptable 4.5 to 6.0
200
Ratings
typ.
max.
unit
tCYC
2
µs
6. A / D Converter Characteristics at Ta=-30°C to +70°C , VSS = 0V
Parameter
Resolution
Absolute
precision
(Note 2)
Conversion
time
Symbol
N
ET
tCAD
Pins
Conditions
VDD [V]
4.5 to 6.0
4.5 to 6.0
AD conversion 4.5 to 6.0
time=16 ✕ tCYC
(ADCR2=0)
(Note 3)
AD conversion
time=32 ✕ tCYC
(ADCR2=1)
(Note 3)
4.5 to 6.0
min.
Ratings
typ.
8
max.
±1.5
15.68
(tCYC =
0.98µs)
65.28
(tCYC =
4.08µs)
31.36
(tCYC =
0.98µs)
130.56
(tCYC =
4.08µs)
Analog input
VAIN
AN0 to AN7
VSS
VDD
voltage range
Analog port
IAINH
VAIN=VDD
4.5 to 6.0
1
input current
IAINL
VAIN=VSS
4.5 to 6.0
-1
(Note 2) Absolute precision excepts quantizing error (±1 / 2 LSB).
(Note 3) The conversion time means the time from executing the AD conversion instruction to setting the
complete digital conversion value to the register.
unit
bit
LSB
µs
V
µA
No.6730-15/22
LC86P5420
7. Current Dissipation Characteristics at Ta=-30°C to +70°C, VSS = 0V
Parameter
Current
dissipation
during basic
operation
(Note 4)
Symbol
IDDOP(1)
IDDOP(2)
IDDOP(3)
IDDOP(4)
Pins
VDD
Conditions
VDD [V]
4.5 to 6.0
•FmCF=6MHz
Ceramic resonator oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops.
•1 / 1 divider
•FmCF=3MHz 4.5 to 6.0
Ceramic resonator oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops.
•1 / 2 divider
•FmCF=0Hz
4.5 to 6.0
(when oscillation
stops).
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•1 / 2 divider
•FmCF=0Hz
4.5 to 6.0
(when oscillation
stops).
•FsXtal=32.768kHz
crystal oscillation
•System clock :
crystal oscillation
•Internal RC
oscillation stops.
•1 / 2 divider
min.
Ratings
typ.
14
max.
26
6.5
14
4
12
3.5
9
unit
mA
No.6730-16/22
LC86P5420
Parameter
Current
dissipation
HALT mode
(Note 4)
Symbol
IDDHALT(1) VDD
IDDHALT(2)
IDDHALT(3)
IDDHALT(4)
Pins
Conditions
•HALT mode
•FmCF=6MHz
Ceramic resonator oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops.
•1 / 1 devider
•HALT mode
FmCF=3MHz
Ceramic resonator oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops.
•1 / 2 devider
•HALT mode
FmCF=0Hz
(when oscillation
stops).
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•1 / 2 devider
•HALT mode
FmCF=0Hz
(when oscillation
stops).
•FsXtal=32.768kHz
crystal oscillation
•System clock :
32.768kHz
•Internal RC
oscillation stops.
•1 / 2 devider
HOLD mode
Ratings
typ.
4
max.
9
4.5 to 6.0
2.2
5
4.5 to 6.0
400
1600
4.5 to 6.0
25
100
0.05
30
VDD [V]
4.5 to 6.0
min.
Current
IDDHOLD VDD
4.5 to 6.0
dissipation
HOLD mode
(Note 4)
(Note 4) The currents of output transistors and pull-up MOS transistors are ignored.
unit
mA
µA
No.6730-17/22
LC86P5420
Table 1. Ceramic resonator oscillation guaranteed constant (main-clock)
A kind of oscillation Producer
Oscillator
6MHz ceramic resonator Murata
CSA 6.00MG
oscillation
CST 6.00MGW
Kyocera
KBR-6.0MSA
PBRC 6.00A (chip type)
KBR-6.0MKS
PBRC 6.00B (chip type)
3MHz ceramic resonator Murata
CSA 3.00MG
oscillation
CST 3.00MGW
Kyocera
KBR-3.0MS
* Both C1 and C2 must use K rank (±10%) and SL characteristics.
C1
C2
33pF
33pF
on chip
33pF
33pF
33pF
33pF
on chip
33pF
33pF
on chip
47pF
47pF
Table 2. Crystal oscillation guaranteed constant (sub-clock)
A kind of oscillation Producer
Oscillator
C3
C4
32.768kHz crystal
Kyocera
KF-38G-13P0200
18pF
18pF
oscillation
* Both C3 and C4 must use J rank (±5%) and CH characteristics.
(It is about the application which is not in need of high precision. Use K rank (±10%) and
SL characteristics.)
Notes
•Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts
as close to the oscillation pins as possible with the shortest possible pattern length.
•If you use other oscillators herein, we provide no guarantee for the characteristics.
CF1
C1
CF2
XT1
CF
C2
Figure 1. Main-clock circuit
Ceramic resonator oscillation
ILC00059
C3
XT2
X'tal
C4
Figure 2. Sub-clock circuit
Cryatal oscillation
ILC00065
No.6730-18/22
LC86P5420
VDD
VDD limit
0V
Power supply
Reset time
RES
Internal RC
resonator
oscillation
tms CF
CF1, CF2
tss Xtal
XT1, XT2
Operation mode
Unfixed
Reset
OCR6=1
Instruction execution mode
<Reset time and oscillation stable time.>
HOLD release signal
Valid
Internal RC
resonator
oscillation
tms CF
CF1, CF2
tss Xtal
XT1, XT2
Operation mode
HOLD
Instruction execution mode
<HOLD release signal and oscillation stable time.>
Figure 3. Oscillation stable time
ILC00044
No.6730-19/22
LC86P5420
VDD
RRES
RES
CRES
(Note) Fix the value of RRES, CRES that is
sure to reset untill 200µs, after Power supply
has been over inferior limit of supply voltage.
Figure 4. Reset circuit
ILC00052
0.5VDD
<AC timing point>
VDD
tCKCY
tCKL
tCKH
SCK0
SCK1
1kΩ
tICK
tCKI
SI0
SI1
tCKO
50pF
SO0, SO1
SB0, SB1
<Timing>
<Test load>
Figure 5. Serial input / output test condition
tPIL
ILC00073
tPIH
Figure 6. Pulse input timing condition
ILC00074
No.6730-20/22
LC86P5420
Notice for use
• The construction of the one-time programmable microcomputer with a blank built-in PROM makes it
impossible for Sanyo to completely factory-test it before shipping. To probe reliability of the programmed devices, the screening procedure shown in the following figure should always be followed.
• It is not possible to perform a writing test on the blank PROM. 100% yield, therefore, cannot be
guaranteed.
• Keeping the dry packing
The environment must be held at a temparature of 30°C or less and a humidity level of 70% or less.
• After opening the packing
After opening the packing, a controlled environment must be maintained until soldering.
The environment must be held at a temperature of 30°C or less and a humidity level of 70% or less.
Please solder within 96 hours.
a. Shipping with a blank PROM (Programming the data by yourself)
This microcomputer is provided DIP / QFP packages, but the condition before mounting is
different. Refer to the mounting procedure as follows.
QFP
DIP
Writing data for program / Verifying
Writing data for program / Verifying
Recommended process of screening
Recommended process of screening
Heat-soak
+1
Hr
150±5°C, 24
--0
Heat-soak
+1
Hr
150±5°C, 24
--0
Reading ascertain of program
Reading ascertain of program
Mounting
Mounting
b. Shipping with a programmed PROM (Programming the data by Sanyo)
DIP
QFP
Mounting
Mounting
No.6730-21/22
LC86P5420
memo :
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer's
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer's products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products(including technical data,services) described or
contained herein are controlled under any of applicable local export control laws and regulations,
such products must not be expor ted without obtaining the expor t license from the authorities
concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of January, 2001. Specifications and information herein are subject to
change without notice.
PS No.6730-22/22