Ordering number : EN*5786 CMOS LSI LC895126 CD-ROM Decoder with Built-in SCSI Interface Preliminary Overview The LC895126 is a CD-ROM decoder that in addition to CD-ROM functions also provides a built-in SCSI interface. • Supports 20MB/s transfers (This capability is currently under evaluation (July 1997) and cannot be guaranteed at present.) Package Dimensions Functions unit: mm • CD-ROM ECC functions, subcode read function, SCSI interface, CAV audio functions 3214-SQFP144 [LC895126] Features • Built-in SCSI interface (Includes a SCAM selection register) • Supports 24× playback and a 10MB/sec data transfer rate (when 16-bit data path 70-ns EDO DRAM is used). • Supports the use of up to 4 Mbit of buffer RAM. • Users can freely set up the CD main channel, C2 flag, and other areas in buffer RAM. • Batch transfer function (Function that transfers the CD main channel, C2 flag, and other data in a single operation) • Multiblock transfer function (Function that transfers multiple blocks automatically in a single operation) • Subcode ECC functions and CD-Text support • CAV audio functions • Intelligent functions (Including auto buffering, auto decoding, and CD-R support) SANYO: SQFP144 Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol Maximum supply voltage VDD max Input and output voltage VI, VO Allowable power dissipation Pd max Conditions Ratings Unit –0.3 to +7.0 V –0.3 to VDD +0.3 V Ta ≤ 70°C 550 mW Operating temperature Topr –30 to +70 °C Storage temperature Tstg –55 to +125 °C 260 °C Soldering conditions (pins only) 10 seconds Allowable Operating Ranges at Ta = –30 to +70°C, VSS = 0 V Parameter Symbol Conditions Ratings min typ Supply voltage VDD 4.5 Input voltage range VIN 0 5.0 max Unit 5.5 V VDD V SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN 13098HA (OT) No. 5786-1/7 LC895126 Electrical Characteristics at Ta = –30 to +70°C, VSS = 0 V, VDD = 4.5 to 5.5 V Parameter Symbol Input high-level voltage VIH1 Input low-level voltage VIL1 Input high-level voltage VIH2 Conditions TTL level pins: (1) TTL level pins: (9) Input low-level voltage VIL2 Pins with built-in pull-up resistors. Input high-level voltage VIH3 TTL level pins: (2) Input low-level voltage VIL3 Schmitt input pins Input high-level voltage VIH4 CMOS level pins: (3) Input low-level voltage VIL4 Schmitt input pins Input high-level voltage VIH5 Input low-level voltage VIL5 Output high-level voltage VOH1 Ratings min typ Unit max 2.2 V 0.8 2.2 0.8 2.2 0.8 0.8 VDD Output low-level voltage VOL1 IOL1 = 12 mA : (6) Output high-level voltage VOH2 IOH2 = –8 mA : (7) V V 0.2 VDD V V 0.8 IOH1 = –12 mA : (6) V V 2.0 (4), (8), (10) V V VDD – 2.1 V V 0.4 2.4 V V Output low-level voltage VOL2 IOL2 = 8 mA : (7) Output high-level voltage VOH2 IOH2 = –2 mA : (9), (5) Output low-level voltage VOL2 IOL2 = 2 mA : (9), (5) 0.4 Output low-level voltage VOL4 IOL4 = 48 mA : (10) 0.4 V +25 µA 240 kΩ Input leakage current Pull-up resistance IIL RUP VI = VSS or VDD: All input pins. (5), (9) 0.4 2.4 –25 60 V V 120 V The pin sets referred to above are as follows: INPUT (1) TEST0 to TEST4, CSCTRL, SUA0 to SUA6, X1EN, WFCK, SBS0 (2) C2PO, SDATA, BCK, LRCK, SCOR, ZRESET (3) ZCS, ZRD, ZWR (4) SCSISEL, XTALSEL OUTPUT (5) ZINT0, ZINT1, ZSWAIT (6) MCK, MCK2, MCK3 (7) EXCK, DSDATA, DLRCK, DBCK, ZRAS0, ZRAS1, ZCAS0, ZCAS1, ZOE, ZUWE, ZLWE, RA0 to RA8 INOUT (8) ACK, ATN (9) D0 to D7, IO0 to IO15, IOP0 to IOP4 (10) DB0 to DB7, DBP, BSY, I/O, MSG, SEL, RST, REQ, C/D Note: The XTAL0, XTALCK0, XTAL1, and XTALCK1 pins are not covered by the electrical characteristics. SCSI Interface Pin Input Characteristics Parameter Input threshold voltage Symbol Vt + t1 Ratings min VDD = 4.50 to 5.50 V Vt – t1 ∆Vtt1 Hysteresis Conditions VDD = 5.0 V typ 1.60 Unit max 2.00 V 0.80 1.10 V 0.41 0.5 V Active Negation Output Characteristics Parameter Symbol Conditions Output high-level voltage VOH IOH = –24 mA Output low-level voltage VOL IOL = 48 mA Ratings min typ Unit max 2.5 V 0.4 V Note: Active negation refers to the DB0 to DB7, REQ, and DBPB outputs. Figure 1 No. 5786-2/7 LC895126 Pin Functions I: Input pin, O: Output pin, B: Bidirectional pin, P: Power Supply pin, NC: Not Connection pin Pin No. Symbol Type 1 VSS0 P 2 IO2 B 3 IO1 B 4 IO0 B 5 MCK2SEL I 6 Function Buffer RAM data I/O pins. Built in pull-up resistors. Provided for switching between MCK2 (22 MHz, 20 MHz) and MCK3 (27 MHz, 25 MHz) in PLL mode. Currently, must be connected to VDD. NC 7 VSS0 P 8 VSS0 P 9 VSS0 10 P NC 11 NC 12 C2PO I 13 SDATA I 14 BCK I 15 LRCK I 16 EXCK O 17 WFCK I CD DSP interface Subcode I/O 18 VDD P 19 VSS0 P 20 SBSO I 21 SCOR I 22 DSDATA O 23 DLRCK O 24 DBCK O 25 MCK O 26 VSS0 P 27 XTALCK0 I Crystal oscillator circuit input 28 XTAL0 O Crystal oscillator circuit input 29 TEST0 I 30 TEST1 I 31 TEST2 I 32 TEST3 I Subcode I/O D/A converter outputs Outputs the XTALCK1 state (1/1, 1/2, or stopped) Test pins. These pins must be connected to VSS0. 33 TEST4 I 34 MCK2 O 35 MCK3 O 36 VSS0 P 37 VDD P 38 ZRESET I 39 ZRD I Microcontroller data read signal input 40 ZWR I Microcontroller data write signal input Outputs the XTALCK0 state (1/1, 1/2, 1/512, or stopped) Chip reset. The system is reset by a low-level input. Continued on next page. No. 5786-3/7 LC895126 Continued from preceding page. Pin No. Symbol Type 41 ZCS I Register chip select signal input from the microcontroller 42 CSCTRL I CS active low/active high selection input from the microcontroller 43 SUA0 I 44 SUA1 I 45 SUA2 I 46 SUA3 I 47 SUA4 I Function Microcontroller register selection signals 48 SUA5 I 49 SUA6 I 50 D0 B 51 D1 B 52 D2 B 53 D3 B 54 VDD P 55 VSS0 P 56 D4 B 57 D5 B 58 D6 B 59 D7 B 60 ZINT0 O Interrupt request signal output to the microcontroller (ECC side. Set up by register settings.) 61 ZINT1 O Interrupt request signal output to the microcontroller (SCSI side. Set up by register settings.) Wait signal output to the microcontroller Microcontroller data signals 62 ZSWAIT O 63 VSS0 P 64 IOP0 B 65 IOP1 B 66 IOP2 B 67 IOP3 B 68 IOP4 B 69 X1EN I 70 ZTALCK1 I Shock proof function oscillator circuit input. Used by the PLL circuit in PLL versions. 71 XTAL1 O Shock proof function oscillator circuit output. Used by the PLL circuit in PLL versions. 72 VSS0 P Analog system ground in PLL versions 73 VDD P Analog system power supply in PLL versions 74 VSS1 P 75 I/O B 76 REQ B 77 VSS1 P 78 C/D B 79 SEL B 80 General-purpose I/O Must be tied low in versions without a PLL circuit. Must be connected to VDD through a resistor in versions that use the PLL circuit. SCSI interface connections SCSI interface connections NC 81 VDD P 82 VSS1 P 83 MSG B 84 RST B 85 VSS1 P 86 ACK B 87 BSY B 88 VSS1 P SCSI interface connections SCSI interface connections Continued on next page. No. 5786-4/7 LC895126 Continued from preceding page. Pin No. Symbol Type 89 ATN B 90 VDD P 91 VSS1 92 Function SCSI interface connections P NC 93 DBP B 94 VDD P SCSI interface connections 95 DB7 B 96 DB6 B 97 VSS1 P 98 DB5 B 99 DB4 B 100 VDD P 101 DB3 B 102 DB2 B 103 VSS1 P 104 DB1 B 105 DB0 B 106 SCSISEL I SCSI pin assignment selection (No change when held low.) 107 XTALSEL I XATL oscillator selection in PLL mode 108 VSS1 P 109 VDD P 110 VSS0 P 111 ZRAS0 O RAS output 0 for buffer RAM (Normally, RAS 0 is used.) 112 ZRAS1 O RAS output 1 for buffer RAM 113 ZCAS0 O CAS output 0 for buffer RAM (Normally, CAS 0 is used.) 114 ZCAS1 O CAS output 1 for buffer RAM 115 ZOE O Buffer RAM output enable 116 ZUWE O Buffer RAM upper write enable Buffer RAM lower write enable SCSI interface connections SCSI interface connections SCSI interface connections SCSI interface connections 117 ZLWE O 118 VSS0 P 119 RA0 O 120 RA1 O 121 RA2 O 122 RA3 O 123 RA4 O 124 RA5 O 125 RA6 O 126 VDD P 127 VSS0 P 128 RA7 O 129 RA8 O 130 RA9 (IO15) B Buffer RAM address and data outputs. 131 RA10 (IO14) B Built in pull-up resistors. Buffer RAM address outputs Buffer RAM address outputs Continued on next page. No. 5786-5/7 LC895126 Continued from preceding page. Pin No. Symbol Type 132 IO13 B 133 IO12 B 134 IO11 B Buffer RAM data I/O. 135 IO10 B Built in pull-up resistors. 136 IO9 B 137 IO8 B 138 VSS0 P 139 IO7 B 140 IO6 B 141 IO5 B 142 IO4 B 143 IO3 B 144 VDD P Function Buffer RAM data I/O. Built in pull-up resistors. NC pins must be left open. Pin names that start with a ‘Z’ are negative logic (i.e. active low) pins. VSS0 is the logic system ground, and VSS1 is the SCSI interface system ground. If DRAM is used, undershoot prevention measures, such as inserting resistors in the RAS and CAS lines and inserting capacitors to ground, must be taken. Since this IC includes buffers that sink 48 mA, applications must take adequate noise reduction measures. No. 5786-6/7 LC895126 Block Diagram *1 WFCK, SBSO, SCOR *2 BCK, SDATA, LRCK, C2PO *3 DB0 to DB7, DBP, BSY, MSG, SEL, RST, REQ, I/O, C/D *4 ACK, ATN *5 ZRD, ZWR, SUA0 to AUA6, ZCS, CSCTRL *6 D0 to D7 *7 IO0 to IO15 *8 RA0 to RA10, ZRAS0, ZRAS1, ZCAS0, ZCAS1, ZOE, ZUWE, ZLWE *9 DBCK, DLRCK, DSDATA Note: The pins IO15 and RA9 share pin 130, and the pins IO14 and RA10 share pin 131. ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of January, 1998. Specifications and information herein are subject to change without notice. PS No. 5786-7/7