Ordering number : EN *5846 CMOS IC LC82221L Motion JPEG Decoder Preliminary Overview The LC82221L is a full-color digital image data expansion IC that accepts data in formats that essentially conform to the JPEG standard. With the provision of frame memory, this IC can input and output image data in standard video formats. In addition, it also supports a wide range of image display functions using that frame memory. As compared to earlier JPEG ICs, this IC features simplified JPEG functionality and a greater emphasis on display functions. Thus it supports the creation of excellent costperformance ratio systems for applications that require a display system. Features • High image quality image expansion using the JPEG system • Superlative cost performance achieved by only providing decoding functions. • Two built-in quantization tables. • High-speed processing achieved by using fixed Huffman tables. Application do not have to set up these tables. • Two Huffman tables, one for luminance data and one for chrominance data, are provided. • Supports scaling factor parameters that allow the quantization factor to be changed. • DRAM for code data buffering and image data playback can be connected directly. • Applications can use either 2Mb or 4Mb DRAMs based on the sizes of the image handled and the structure of the system. However, 16-bit data path DRAMs must be used. • Image data is output in synchronization with an image display synchronizing signal. • Color structure of the code data is Y:U:V=4:1:1. • Dedicated code data input bus provided to avoid loading the host bus. DMA transfers are also supported. • Users can select either RGB or YUV for image data output. • Built-in YUV to RGB color conversion circuit • The LC82221L supports image sizes up to 1024 pixels in the horizontal direction. The range of vertical sizes handled can be set up arbitrarily, since it is limited by the size of the DRAM provided. • 3.3-V single-voltage power supply. Low power. • The display position and display size can be set. • SOI and EOI marker support • Horizontal and vertical scrolling display functions • Support for overwrite display, in which the next data for expansion is displayed by overwriting the previously expanded image data Package Dimensions unit: mm 3214-SQFP144 [LC82221L] SANYO: SQFP144 SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 62698RM (OT) No. 5846-1/7 LC82221L Block Diagram No. 5846-2/7 LC82221L Specifications Electrical Characteristics Absolute Maximum Ratings at VSS = 0 V Parameter Symbol Maximum supply voltage VDD Input and output voltage VI, VO Conditions Ratings Unit –0.3 to +4.6 V –0.3 to VDD+0.3 V Input and output current II, IO –20 to +20 mA Operating temperature Topr –30 to +70 °C Storage temperature Tstg –55 to +125 °C Allowable Operating Ranges at Ta = –30 to +70°C Parameter Symbol Ratings Conditions min typ Supply voltage VDD 3.0 Input voltage VIN 0 3.3 Unit max 3.6 V VDD V DC Characteristics at Ta = –30 to +70°C, VDD = 3.0 to 3.6 V, VSS = 0 V Parameter Symbol Input high-level voltage VIH1 Input low-level voltage VIL1 Input high-level voltage VIH2 Input low-level voltage VIL2 Input high-level current IIH VIN = VDD; All input pins (including bus pins) IIL1 VIN = VSS : (3) IIL2 VIN = VDD; Pins with pull-up resistors: (4) Output high-level voltage VOH IOH = –6 mA; All output pins (including bus pins) Output low-level voltage VOL IOL = 6 mA; All output pins (including bus pins) Output leakage current IOZ When set to high-impedance output: (5) Pull-up resistance RUP (6) Input low-level current Ratings Conditions CMOS level inputs: (1) CMOS level Schmitt inputs: (2) min typ Unit max 0.7 VDD V 0.2 VDD 0.75 VDD V V 0.15 VDD V –10 +10 µA –10 +10 µA –100 –10 µA VDD – 0.8 V 0.4 –10 70 140 V +10 µA 280 kΩ Applicable Pins (1) CTLCPU, CTLA, CTLD, CLKSEL, CLK, CDD, TEST, MD, DG, DB, DR, ZPXEN, ZHSYNC, ZVSYNC, PXCLK (2) ZCTLCS, ZCTLRD, ZCTLWR, ZRESET, ZCDCS, ZCDWR (3) CTLCPU, CTLA, CTLD, CLKSEL, CLK, CDD, TEST, DG, DB, DR, ZPXEN, ZHSYNC, ZVSYNC, PXCLK, ZCTLCS, ZCTLRD, ZCTLWR, ZRESET, ZCDCS, ZCDWR (4) MD (5) ZCTLRDY, CTLD, ZCDRDY, MD, DG, DB, DR (6) MD No. 5846-3/7 LC82221L Pin Functions Pin Number Pin Name 1 VSS 2 ZCTLINT O Control bus interrupt request 3 ZCTLCS I Control bus select 4 ZCTLRD/RW I Control bus read or R/W select 5 ZCTLWR/DS I Control bus write/data strobe 6 ZCTLRDY O Control bus ready (tri-state output) 7 CTLCPU I Control bus CPU type selection 8 VDD 9 VSS 10 Type Description Ground +3.3-V power supply Ground NC 11 NC 12 CTLA5 I 13 CTLA4 I 14 CTLA3 I 15 CTLA2 I 16 CTLA1 I 17 CTLA0 I 18 VDD 19 VSS 20 CTLD7 I/O 21 CTLD6 I/O 22 CTLD5 I/O 23 CTLD4 I/O 24 CTLD3 I/O 25 CTLD2 I/O 26 CTLD1 I/O 27 CTLD0 I/O 28 VDD 29 VSS 30 CLKSEL0 I Clock divisor setting 31 CLKSEL1 I CLKSEL1:0 = 00: No divisor, 01: Divisor = 2, 10: Divisor = 3. 32 CLK I System (decode) clock input 33 34 Control bus address +3.3-V power supply Ground Control bus data +3.3-V power supply Ground NC ZRESET 35 I Hardware reset NC 36 VSS 37 VDD 38 ZCDCS/ZCDACK I Code bus select/code bus DMA acknowledge 39 ZCDINT/ZCDREQ O Code bus interrupt/code bus DMA request 40 ZCDWR I Code bus data write signal 41 ZCDRDY O Code bus ready (tri-state output) 42 CDD15 I Ground +3.3-V power supply 43 CDD14 I Code bus data 44 CDD13 I (CDD8 to CDD15 are unused in 8-bit mode.*) 45 CDD12 I Note: * These pins must be pulled up with a resistance of about 10 kΩ. Continued on next page. No. 5846-4/7 LC82221L Continued from preceding page. Pin Number Pin Name 46 VDD 47 VSS 48 CDD11 Type Ground I 49 CDD10 I 50 CDD9 I 51 CDD8 I 52 CDD7 I 53 CDD6 I 54 VDD 55 VSS 56 CDD5 Ground I 57 CDD4 I CDD3 I 59 CDD2 I 60 CDD1 I 61 CDD0 I VSS 63 VDD Code bus data +3.3-V power supply Ground 64 NC 65 NC 66 Code bus data +3.3-V power supply 58 62 Description +3.3-V power supply NC 67 TEST0 I 68 TEST1 I 69 TEST2 I 70 TEST3 I 71 TEST4 I 72 VSS 73 VDD 74 ZOE O Memory output enable 75 ZWEL O Memory write enable (L) Test pins * Ground +3.3-V power supply 76 ZRAS O Row address strobe 77 ZCASL O Column address strobe (L) 78 ZWEH/ZCASH O Memory write enable (H)/column address strobe (H) 79 VSS 80 MD15 I/O 81 MD14 I/O 82 MD13 I/O 83 MD12 I/O 84 MD11 I/O 85 MD10 I/O 86 MD9 I/O 87 MD8 I/O 88 MD7 I/O 89 MD6 I/O 90 VDD Ground Note:* These pins must be tied to ground. Frame memory interface data bus +3.3-V power supply Continued on next page. No. 5846-5/7 LC82221L Continued from preceding page. Pin Number Pin Name 91 VSS Type Description Ground 92 MD5 I/O 93 MD4 I/O 94 MD3 I/O 95 MD2 I/O 96 MD1 I/O 97 MD0 I/O 98 VDD 99 MA8 O 100 MA7 O 101 MA6 O 102 MA5 O 103 MA4 O 104 MA3 O 105 MA2 O 106 MA1 O 107 MA0 O 108 VSS 109 VDD 110 DG7 O 111 DG6 O 112 DG5 O 113 DG4 O 114 DG3 O 115 DG2 O 116 DG1 O 117 DG0 O 118 VSS 119 VDD 120 DB7 O 121 DB6 O 122 DB5 O 123 DB4 O 124 DB3 O 125 DB2 O 126 VDD 127 VSS 128 DB1 O 129 DB0 O 130 DR7 O 131 DR6 O 132 DR5 O 133 DR4 O 134 VSS Frame memory interface data bus +3.3-V power supply Frame memory address signals Ground +3.3-V power supply Pixel data bus G (U) * Ground +3.3-V power supply Pixel data bus B (V) * +3.3-V power supply Ground Pixel data bus B (V) * Pixel data bus R (Y) * Ground Note: * These pins must be pulled up with a resistance of about 10 kΩ. Continued on next page. No. 5846-6/7 LC82221L Continued from preceding page. Pin Number Pin Name Type 135 DR3 O Description 136 DR2 O 137 DR1 O 138 DR0 O 139 ZPXEN I Pixel data enable signal 140 ZBLANK O Blanking signal 141 ZHSYNC I Horizontal synchronizing signal 142 ZVSYNC I Vertical synchronizing signal 143 PXCLK I Pixel clock 144 VDD Pixel data bus R (Y) * +3.3-V power supply Note:* These pins must be pulled up with a resistance of about 10 kΩ. ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of June, 1998. Specifications and information herein are subject to change without notice. PS No. 5846-7/7