Ordering number : EN5889 Monolithic Linear IC LV1041M Dolby Prologic Decoder Overview The LV1041M is a Dolby Prologic Surround signalprocessing IC that implements in a single chip the functions of the Sanyo LV1016 and LA2786 ICs and a master volume control for the center and surround channels. This IC allows both systems of Dolby Prologic surround and digital surround to be formed into a single IC. Note *: Dolby and the double D symbol are registered trademarks of the Dolby Laboratories Licensing Corporation. This IC can only be used by Dolby licensees. Licensing information and corresponding technical information is available from:Dolby Licensing Corporation San Francisco, CA 94103-4813 USA Features Package Dimensions • Implements a Prologic surround decoder in a single chip. • Wide dynamic range • All modes can be controlled from control data transmitted serially over four lines: CLOCK, DATA, ENABLE, and ENABLE2. This function is compatible with the LV1016 and the LA2786. unit: mm 3174-QFP80E [LV1041M] Functions • • • • • • • • • • • • • • • Adaptive matrix Center mode control (normal, phantom, wide) 4/3 channel logic control Auto-balance (on/off) Prologic off mode (bypass and full bypass) Center trim (0 to –31 dB in 1-dB steps) On-chip memory: (8K SRAM) Variable delay time: 15, 20, 25, 30, 40, or 50 ms (15, 20, 25, or 30 ms for Dolby Prologic surround) New A/D and D/A converter circuits adopted On-chip Dolby B noise reduction On-chip input and output filters Built-in VDD circuit Surround trim (0 to –31 dB in 1-dB steps) Input and output muting functions Master volume control for the center and surround channels (0 to –44 dB in –2-dB steps, –44 to –76 dB in –4-dB steps, and muted) SANYO: QIP80E SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 51898RM (OT) No. 5889-1/19 LV1041M Specifications Maximum Ratings at Ta = 25°C Parameter Symbol Conditions Ratings VCC max Maximum supply voltage Allowable power dissipation Pd max Unit 12 Ta ≤ 70°C When mounted on a 114.3 × 76.1 × 1.6 mm fiberglass epoxy printed circuit board. V 1300 mW Operating temperature Topr –20 to +70 °C Storage temperature Tstg –40 to +150 °C Ratings Unit Operating Conditions at Ta = 25°C Parameter Symbol Recommended supply voltage VCC Operating supply voltage range VCC op Conditions 9 V 8 to 10 V V Input high-level voltage VIH 3.5 to 5.5 Input low-level voltage VIL 0 to 1.0 VO Dolby Dolby level V 300 mVrms Operating Conditions at Ta = 25°C, VCC = 9 V, VIN = 300 mV rms (left and right inputs), 0.707 × 300 mV rms (center and surround inputs), f = 1 kHz, center trim = 0 dB, surround trim = 0 dB, delay time = 20 ms, in wide mode, and with the center and surround master volume set to 0 dB. Parameter Symbol Conditions Quiescent current ICC No signal Center channel output level VOC C input Output level deviation VOL L, R, Sch from Cch, matrix output Matrix rejection (L) RjL Matrix rejection (C) Matrix rejection (R) Matrix rejection (S) Ratings min typ max Unit 80 110 mA –2 0 +2 dB –0.5 0 +0.5 dB L input –40 –25 dB RjC C input –40 –25 dB RjR R input –40 –25 dB RjS S input –40 –25 dB Total harmonic distortion (L) THDL L 24-pin output 0.02 0.09 % Total harmonic distortion (C) THDC C 31-pin output 0.02 0.09 % Total harmonic distortion (R) THDR R 21-pin output 0.02 0.09 % Total harmonic distortion (S) THDS2 S delay 33-pin output 0.1 0.7 % Signal-to-noise ratio (L) SN/L L 24-pin output, CCIR/ARM, RS = 10 kΩ –76 –71 dB Signal-to-noise ratio (C) SN/C C 31-pin output, CCIR/ARM, RS = 10 kΩ –77 –71 dB Signal-to-noise ratio (R) SN/R R 21-pin output, CCIR/ARM, RS = 10 kΩ –76 –71 dB Signal-to-noise ratio (S) SN/S S delay 33-pin output –75 –65 Signal handling (L) SHL L 24-pin output, VCC = 8.5 V, THD = 1% 15 16 dB Signal handling (C) SHC C 31-pin output, VCC = 8.5 V, THD = 1% 15 17 dB Signal handling (R) SHR R 21-pin output, VCC = 8.5 V, THD = 1% 15 16 dB Signal handling (S) SHS VCC = 8.5 V, THD = 3%, output 33-pin S delay 15 16 Noise sequencer output level Vns Each matrix out 53 60 Noise reduction frequency characteristics Dec1 0 dB, 1 kHz Dec2 –20 dB, 1 kHz Dec3 0 dB, 5 kHz Dec4 Dec5 dB dB 90 mV dB –1.5 0.0 +1.5 –24.0 –22.5 –21.0 dB –1.5 0.0 +1.5 dB –20 dB, 5 kHz –23.3 –21.8 –20.3 dB –40 dB, 5 kHz –46.8 –45.3 –43.8 dB [Prologic Off Mode] Left and right channels total harmonic distortion THDOFF L, R, 400 to 30 kHz BPF 0.01 0.03 % Left and right channels signal-tonoise ratio S/NOFF L, R, CCIR/ARM –90 –80 dB Left and right channels signal handling Shoff L, R, VCC = 8.5 V, THD = 1% Master volume muting attenuation VMUTE VIN = 1 Vrms 15 16 –92 dB –80 dB No. 5889-2/19 LV1041M Sample Application Circuit No. 5889-3/19