Ordering number : ENN6628 LV1050M Bi-CMOS IC LV1050M Dolby Pro Logic Surround Decoder Overview • The LV1050M is a Dolby Pro Logic surround effect signal-processing Bi-CMOS IC that in addition to LV1018 and LA2787 function, realizes virtual surround processing with the use of 5.1ch input signal. This IC can implement a Dolby Pro Logic surround system and various digital surround system in just one chip. • • • • • • • • • • • • • Input and output filter. Output : 7kHz L.P.F in dolby surround mode. 5kHz L.P.F in simulated surround mode. Built-in VDD. Simulated surround function. Fixed matrix : L+R, L--R. Front addition : 0, -2, -4 and -6 dB inverted and non inverted addition. Reverb function. Rear-channel monaural/stereo switching. Rear addition : 0, -2, -4 and -6 dB inverted and noninverted addition . Package Dimensions unit : mm 3174-QIP80E [LV1050M] 0.8 0.8 0.35 23.2 20.0 1.6 0.15 41 64 65 40 80 25 15.6 • 1 24 2.70 0.8 0.8 • 3.0max • Note : Dolby and Double D Symbol are registered trademarks of Dolby Laboratories Licensing Corporation. This IC is available only to licensees of Dolby Laboratories Licensing Corporation. San Francisco, C94103-4813, USA, from whom licensing and application information must be obtained. 1.0 • Adaptive matrix. Center mode control (Normal/Phantom/Wide). 4ch/3ch logic control. Auto balance (ON/OFF). Prologic off-mode (Bypass/Full Bypass). On-chip memory (8k bit S-RAM). Variable delay time. Dolby surround mode : 15, 20, 25, or 30ms. Simulated surround mode : 7.5, 15, 20, 25, 30, 40 or 50ms. Modified B type noise-reduction. Center trim, surround trim (LS-ch, RS-ch) and LFE trim (0 to -31dB in -1dB steps). 0.8 • 17.2 14.0 • • 1.6 Functions and Features Pseudo-tap function. Built-in input switch for the L, C, R, LS, RS, and LFE channels. Virtual surround function (VDS 2 modes, VDD 1 mode). Simulated surround function for Dolby Digital. Input and output muting function. Reference level : 300 mVrms. Operating supply voltage : 8 to 10V. Package : QIP80E. 21.6 SANYO : QIP80E Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 81000 RM IM No.6628-1/14 LV1050M Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Allowable power dissipation Symbol VCC max Pd max Conditions Ratings Ta ≤ 70°C ✻with board Unit 10.5 V 1400 mW Operating temperature Topr --20 to +70 °C Storage temperature Tstg --40 to +150 °C Note : ✻When mounted on a 114.3 mm ✕ 76.1 mm, t = 1.6 mm fiberglass epoxy printed circuit board. Operating Conditions at Ta = 25°C Parameter Symbol Recommended supply voltage VCC Operating supply voltage range VCCopg Conditions Ratings Control input high level Control input low level Dolby level Unit 9 V 3.5 to 5.5 V 0 to 1.5 VO Dolby V 8 to 10 300 V mVrms Electrical Characteristics at Ta = 25°C, VCC = 9 V, f = 1 kHz, VIN = 300 mV (L, R inputs), VIN = 212 mV (C,S inputs), center and surround trim = 0 dB. Unless otherwise specified : in pro logic on mode and with the 400 Hz to 30 kHz bandpass filter used. Parameter Quiescent current Symbol Conditions Ratings min typ Unit max ICC VOC 120 135 mA --2 0 2 dB VOA --0.5 0 0.5 dB Lch matrix rejection Rj, L 25 35 dB Cch matrix rejection Rj, C 25 35 dB Rch matrix rejection Rj, R 25 35 dB Sch matrix rejection Rj, LS, RS 25 35 dB Cch output level Output level deviation (Reference to the center output) Total harmonic distortion L, R, C THD 0.02 0.05 % Total harmonic distortion S THD 0.1 0.7 % S/N Lch S/N, L 65 76 dB S/N Cch S/N, C 65 77 dB S/N Rch S/N, R 65 76 dB S/N Sch S/N, LS,RS 60 72 dB CCIR/ARM, Rg = 10 kΩ Lch signal handling SH, L 15 16 dB Cch signal handling SH, C 15 18 dB Rch signal handling SH, R 15 16 dB Sch signal handling SH, LS, RS 15 16 dB Noise sequencer output VN S/N off L,R 50 70 Pro Logic off S/N (Full Bypass mode) 80 90 Pro Logic off total harmonic distortion THD off L,R NR frequency characteristics Virtual Dolby Surround S/N VCC = 8.5 V, f = 1 kHz, THD = 1% (L,C,R), THD = 3% (LS, RS) 90 mV dB 0.007 0.03 % --1.5 0.0 1.5 dB Dec1 0dB, 1kHz, VCC = 8.5 V, f = 1 kHz, THD = 1% (L,C,R), THD = 3% (LS, RS) Dec2 --20dB, 1kHz, VCC = 8.5 V, f = 1 kHz, THD = 1% (L,C,R), THD = 3% (LS, RS) 0dB, 5kHz, VCC = 8.5 V, f = 1 kHz, THD = 1% (L,C,R), THD = 3% (LS, RS) --24.0 --22.5 --21.0 dB Dec3 --1.5 0.0 1.5 dB Dec4 --20dB, 5kHz, VCC = 8.5 V, f = 1 kHz, THD = 1% (L,C,R), THD = 3% (LS, RS) --23.3 --21.8 --20.3 dB Dec5 --40dB, 5kHz, VCC = 8.5 V, f = 1 kHz, THD = 1% (L,C,R), THD = 3% (LS, RS) --46.8 --45.3 --43.8 dB 55 64 S/N v L, R CCIR/ARM, Rg=10 kΩ dB No.6628-2/14 FC-LS FC-RS Rt Lt FC-C FC-LFE FC-R FC-L INPUT BALANCE CONTROL NOISE SEQUENCER DOLBY PROLOGIC ADAPTIVE MATRIX AUDIO DELAY FIXED MATRIX C-TRIM 7kHz L. P. F. B-NR REAR STEREO FRONT MIX/ VIRTUAL LS-TRIM RS-TRIM LS-OUT RS-OUT R-OUT L-OUT LFE-OUT C-OUT LV1050M Block Diagram ILV00002 No.6628-3/14 LV1050M Sample Application Circuit LL--LOW, LEAK 3 + PG LOGDIFF VCS PG VLR LOGDIFF 62 + + 61 + 60 R VCA VCA S R + C--OUT 9 SW5 + S MODE 3PIN B 10 C 220 µF SW4 A 22 nF R NOISE--GEN 55 47 nF 54 SW5 A L 53 S L OSC 680 pF B B R NS--BPF2 DEV B B SW5 A 12 NS--BPF1 NOISE--FIL A SW6 ANALOG C--MODE OSC 11 GND1 BPL--CONT CH--CONT B CTRIM D MIX--IN 0.47 µF 56 4PIN 5PIN 6PIN + C--MODE 50 KΩ A C 10 µF AC--GND SW1B L 57 59PIN L.P.F C DC--CUT 47 µF 58 L VOL A 11PIN 59 50 KΩ VCA A MIX--OUT SW2 8 10 µF + VCA L A + VCA B + + 220 µF VCA R VOL A VREF LT--IN + LT--IN VCA B VCC1 RT--IN + RT--IN 2.2 µF 10 µF 0.1 µF FC--C--IN + 2.2 µF 6 220 µF FC--C--IN 2.2 µF + 5 7 L--BPF1 RECT -- 4 L--BPF2 BPF VCA VRBF 63 RECT RECT 10 µF L--DC--OUT 65 0.1 µF R--DC--OUT 66 0.1 µF 2 RECT C--DC--OUT 67 L--BPF3 68 + DC OUT3 69 0.47 µF R--RECT 70 4.7 µF DC OUT4 71 + 64 10 µF C--OUT + 1 10 µF MIX--OUT + VLR--TH 72 0.47 µF L--RECT 4.7 µF VLR--1 73 0.15 µF 74 + VLR--2 75 VCS--2 VCS--1 76 3.3 µF + VCS--TH 77 0.15 µF + 0.15 µF + 3.3 µF 78 BPF S--DC--OUT + 0.15 µF L+R--RECT 0.1 µF R--BPF1 79 4.7 µF DC OUT2 R--BPF3 0.1 µF 80 R--BPF2 0.47 µF L--R--RECT 4.7 µF DC OUT1 0.47 µF + VCC CLK FILTER DELAY--OUT B + L--OUT + B C + LFE--OUT 10 µF + OSC ADM--CONT 48 CR--OT 47 LC--INE 46 LC--INB 15 pF 10 µH 3 20 KΩ S LFE--OUT 0.1 µF 20 KΩ 20 KΩ + 10 µF CR--IN D 20 KΩ 18 DIGITAL SVC201 49 8K--SRAM C D RS--OUT RS--OUT -- 17 10 µF LS--OUT 50 B R GND VSS A A 16 ENABLE ENABLE R--STEREO D 10 µF LS--OUT 51 OUT--FILTER D + R--OUT C L C 15 B VOL/MUTE B 10 µF R--OUT DATA A SW12 A 14 + DATA B--NR DELAY--OUT A L--OUT 52 DATA--DEC 47 pF 106 105 104 13 103 102 101 DELAY--IN DELAY--IN REVERB 220 µF CLK A SW11 A B B C 500 Hz HPF 19 51 pF 100 pF ADM D 36PIN + DC OUT 20 VDD 0.33 µF + DC OUT--IN A SW11 21 B 1 µF 45 + B + 220 µF A SW11 + 0.1 µF VDD 44 A/D 82000 pF D L R 41 ANALOG + 39 kΩ DET IREF 40 2.2 µF NR--C2 39 200 pF + 38 100 pF + 37 0.022 µF 7KL.P.F 2.2 µF + VIR--OFP FC--L--IN 36 AGND FC--L--IN + 2.2 µF FC--R--IN FC--LS--IN + 35 FC--R--IN 0.1 µF 34 2.2 µF + 0.1 µF 33 FC--LS--IN 32 FC--RS--IN 31 FC--LFE--IN 30 POAPL 29 FC--RS--IN 2.2 µF 1 µF 28 FC--LFE--IN 2.2 µF + 27 POAPR LS--DC OUT--OUT 26 D/A 82000 pF LS--TRIM PYSLDIN + 3300 pF 42 24 25 NS A D A D A VIRTUAL 43 B C B C B C D A VIRTUAL LS LFE--TRIM RS--TRIM B D A RS C B D A 23 C B A 1 µF RS--DC OUT--IN C 220 µF RS--DC OUT--OUT + + 22 B + VCC2 LS--DC OUT--IN PYSRDIN 0.1 µF ILV00007 Notes on LV1050M Usage • Power is supplied to the matrix and steering control circuit in the LV1050M Dolby Prologic surround decoder from VCC1 (pin8) and GND1 (pin57). Power is supplied to the delay line circuit in the surround block from VCC2 (pin22)and GND2 (pin41), and power is supplied to the digital circuit blocks from VDD (pin45) and VSS (pin50). • One Point that requires care is that mutual interactions (due to, for example, common impedances) between these power supply lines may influences the signals being processed, if this happens, phenomena such as souns not being moved smoothly may occur. • To prevent such phenomena from occurring, observe the following recommendations. – Design the printed circuit board layout so that all VCC and ground lines are as short and as wide as possible. – Connect all VCC and ground lines to the power supply independently. – Connect capacitors (about 220µF) between each of the VCC and ground pairs as close to the IC pins as possible. Note : A sample power supply line layout is presented in the above diagram for reference. No.6628-4/14