Ordering number : EN4374A Thick-Film Hybrid IC STK311-010 RDS Demodulation + Synchronization and Error Correction Overview Package Dimensions The STK311-010 is a hybrid integrated circuit (HIC) for Radio Data System (RDS) applications which must conform to European Broadcasting Union (EBU) enforced recommendations. Since the Radio Data System (RDS) subjects every kind of data to multiplex broadcasting for FM broadcasts, the STK311-010 functions as a hybrid IC which demodulates the modulated signal’s data, previously multiplexed to a RDS signal, matches synchronization and performs error detection and correction. By combining SC system and photoresist technology with folded board construction and incorporating Sanyo’s unique insulated metal substrate technology (IMST) to the base, the STK311-010 has successfully been contained within a low-profile package. unit: mm 4132 [STK311-010] Applications • Car stereos • Home stereos Features • On-chip 57 kHz BPF provides adjustment-free performance • On-chip 4 MHz ceramic oscillator • Supports RDS data demodulation system designs incorporating fewer external components • On-chip ARI-SK/DK decoder Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Symbol Conditions VCC max Ratings Unit 6.3 V Operating temperature Topr –30 to +85 °C Storage temperature Tstg –40 to +100 °C Ratings Unit Recommended Operational Voltage at Ta = 25°Ct Parameter Supply voltage Symbol Conditions VCC Power supply voltage operating range VCC OP 5 V 4.7 to 5.5 V SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN N3096HA(OT)/10293YO 5-3279No. 4374-1/7 STK311-010 Operating Characteristics at Ta = 25°C, VCC = 5V Parameter Quiescent current Symbol Conditions min typ ICCO Band-pass filter gain VGBPF Band-pass filter selectivity CR Unit 38 9 12.5 17 dB f = 60 kHz (57 kHz = 0 dB) –6 –2.5 0 dB f = 54 kHz (57 kHz = 0 dB) –6 –3.5 0 dB –39 –33 dB f = 57 Hz f = 38 kHz (57 kHz = 0 dB) PLL capture range max 26 –0.9 5 mVrms, CW input mA % +1.5 % RDS detection seisitivity 4 pin input voltage which sets 12 pin to low 0.4 1.0 mVrms SK detection seisitivity 4 pin input voltage which sets 11 pin to low 1.0 2.0 mVrms DK detection seisitivity 4 pin input voltage which sets 10 pin to low 1.7 2.6 mVrms RDS input dynamic range 4 pin maximum input signal (ARI + RDS) which sets 12 pin to low 30 50 mVrms DK input dynamic range 4 pin maximum input signal (ARI) which sets 10 pin to low 75 100 mVrms 453 456 VCO free-run frequency Output high level voltage fOSC VOH *1 IOH = –50 µA VCC – 1.2 *1 IOH = –10 µA VCC – 0.5 459 kHz V V *2 IOL = 10 mA 1.5 V Output low level voltage VOL *2 IOL = 1.8 mA 0.4 V Ceramic oscillator stability time tCFS Refer to Figure 1 10 ms Reset time tRST Refer to Figure 2 Note: 1. DATA START, DATA OUT, CLOCK OUT 2. RECEIVE, CORRECTION, ERROR, DATA START, DATA OUT, CLOCK OUT Other The STK311-010 supports HIC internal settings for all output signals of CLK OUT and DATA START. These are shown in the following table. Table 1 Output Signal Settings Setting Polarity of CLK OUT 1 Negative edge trigger DATA START Output Every block 2 Negative edge trigger Only 2nd block 3 Positive edge trigger Every block 4 Positive edge trigger Only 2nd block Note: STK311-010 defaults to setting 1 though other settings are supported. No. 4374-2/7 STK311-010 Internal Equivalent Circuit Sample Application Circuit Sample System Configuration No. 4374-3/7 STK311-010 Pin Functions Pin No. Pin name 1 OSC This pin is for connecting the VCO ceramic oscillator (456 kHz). Functions 2 VCC This power supply pin is for LA2230 and LC7073 plus power supply. 3 AG 4 INPUT This is the input pin. 5 MONI This pin is for BPF (adjustment use) monitor output. 9 ID-ADJ This pin is for SK detection sensitivity adjustment use. 10 DK-ID Output pin for signaling existence of DK signal detection. When DK signal detection is possible, a low level output is enabled and when detection is not possible, a high level is established. 11 SK-ID Output pin for signaling existence of SK signal detection. When SK signal detection is possible, a low level output is enabled and when detection is not possible, a high level is established. 12 RDS-ID Output pin for signaling existence of RDS signal detection. When RDS signal detection is possible, a low level output is enabled and when detection is not possible, a high level is established. 13 DG 14 RESET This ground pin is for connecting the analog system (LA2230) ground (GND). This ground pin is for connecting the digital system (LC7073) ground (GND). This pin is for reset input. Reset restart inputs a low level for more than 4 clock cycles. Schmitt type with an on-chip pull-up resistor. Select input pin for error correction existence. This pin is for setting whether or not errors within RDS demodulation data are corrected or output as is. When set to 0, the correction function is disabled; a setting of 1 enables error correction. Error correction mode corrects up to 5 bits within 5 bit distance. 15 CORR. SEL 16 DATA START 17 DATA OUT Serial data output data CMOS type output pin with pull-up MOS transistor. 18 CLK OUT Clock output. CMOS type output pin with pull-up MOS transistor. 19 OSC CHK Output configuration controlled from serial data output block data starting signal DS control input. CMOS type output pin with pull-up MOS transistor. Pin for OSC 1 oscillation frequency check. No. 4374-4/7 STK311-010 Relationship of RDS Demodulation Data (LA2230 Output) and LC7073 Output Data • Serial data output from LC7073 (DATA OUT) is output 1 block slower than data received from LA2230/2231. Figure 3 Relationship of Demodulation Data and Output Data Serial Data Output Format and Timing S E F OE OF A/B B1 and B0 D15 to D0 : Start bit (defaults to 0) : Error flag Refer to table for flag settings : Correction flag : Offset E (defaults to 0, future expansion use) : Offset F (defaults to 0, future expansion use) : Group type version 0 : Version A 1 : Version B : Block number 00 : First block 01 : Second block 10 : Third block 11 : Fourth block : RDS data Figure 4 Table 2 Error (E) and Correction (F) Flags Item E F No error 0 0 Correction complete 0 1 Uncorrectable 1 1 Serial Data Output Format and Timing No. 4374-5/7 STK311-010 Control Input CORR.SEL Pin Read Timing Usually, this pin is used for checking pin states. However, the error correction can be activated using this control input at any time. During Synchronization Detection Pin status is read for every single bit of demodulation data from the RDS demodulation IC (indicated in the illustration by a down arrow ) and this continues for four times until the time that a single bit can be taken and read to the internal system. Figure 5 Pin Read Timing During Synchronization Detection After Synchronization Detection Pin status is read for every block header of demodulation data from the RDS demodulation IC (indicated in the illustration by a down arrow ) and this continues for four times until the time that a single bit can be taken and read to the internal system. Figure 6 Pin Read Timing After Synchronization Detection Data Characteristics No. 4374-6/7 STK311-010 ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of August, 1997. Specifications and information herein are subject to change without notice. No. 4374-7/7