Ordering number : ENN 6903 Bi-CMOS IC LV23000M Single-Chip Tuner IC for Radio/Cassette Players Overview Package Dimensions The LV23000M is a single-chip tuner IC for radio/cassette players that provides FM, AM, MPX, and PLL circuits. It allows the tuner PCB to be simplified significantly. unit: mm 3129-MFP36SD [LV23000M] 19 36 7.9 • AM tuner • FM tuner • Multiplex stereo decoder • PLL frequency synthesizer 9.2 10.5 Functions 1 18 0.25 2.25 2.5max 15.3 0.4 0.8 0.85 0.1 • Tuner circuit includes built-in PLL for easy end product design. • Supports FCC standards • Built-in adjustment-free multiplex VCO • AM low-cut control • Provides the transistor required to implement an active low-pass filter. 0.65 Features SANYO: MFP36SD (375 mil) • CCB is a trademark of SANYO ELECTRIC CO., LTD. • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO. Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 62901RM (OT) No. 6903-1/14 LV23000M Specifications Maximum Ratings at Ta = 25°C Parameter Symbol Maximum supply voltage Maximum input voltage Ratings Unit VCC 7.0 V VDD max VDD 7.0 V VIN1 max CE, DI, CL 7.0 V VIN2 max XIN VDD + 0.3 V Ta ≤ 70°C* 400 mW VO1 max DO 7.0 V VO2 max XOUT, PD VO3 max BO1, BO2, AOUT Allowable power dissipation Pdmax Maximum output voltage Conditions VCC max VDD + 0.3 V 12.0 V Operating temperature Topr –20 to +70 °C Storage temperature Tstg –40 to +125 °C Ratings Unit Note: * When mounted on a 114.3 × 76.1 × 1.6 mm glass epoxy printed circuit board. Operating Conditions at Ta = 25°C Parameter Symbol Recommended supply voltage Operating supply voltage range Conditions VCC 5.0 V VDD 3.0 V VCC op 4.0 to 6.0 V VDD op 2.5 to 3.6 V PLL Block Allowable Operating Ranges at Ta = –20 to +70°C, VSS = 0 V Parameter Symbol Supply voltage VDD High-level input voltage VIH Low-level input voltage Output voltage Operating frequency Conditions Ratings min typ max Unit 2.5 3.6 V CE, CL, DI 0.7VDD 6.0 V VIL CE, CL, DI 0 0.3VDD V VO1 DO 0 6.0 V VO2 BO1, BO2, AOUT 0 10 fIN1 XIN: VIN1 75 V kHz fIN2 FMIN: VIN2 10 160 fIN3 AMIN (SNS = 1): VIN3 2 40 MHz fIN4 AMIN (SNS = 0): VIN4 0.5 10 MHz MHz Note: The XIN pin has an extremely high input impedance, which may result in current leakage problems. No. 6903-2/14 LV23000M Operating Characteristics at Ta = 25°C, VCC = 5.0 V, VDD = 3.0 V, in the specified test circuit, using Yamaichi Electronics socket IC51-0362-736 Parameter Symbol Conditions Ratings min typ Unit max [FM Front End Characteristics] : fc = 98 MHz, fm = 1 kHz, 22.5 kHzdev. 3 dB sensitivity Practical sensitivity 3 dB LS QS 60 dBµV EMF, referenced to a 22.5 kHz dev. output, –3 dB input 12 dBµV EMF For a 30 dB signal-to-noise ratio input 12 dBµV EMF [FM IF Monaural Characteristics] : fc = 10.7 MHz, fm = 1 kHz, 75 kHzdev. Demodulator output VO 100 dBµ V, the pin 12 output 210 330 Signal-to-noise ratio S/N 100 dBµ V, the pin 12 output 68 75 Total harmonic distortion (mono) THD 100 dBµ V, the pin 12 output 0.3 1.5 % 100 dBµ V, referenced to a 75 kHz dev. output, –3 dB input 38 44 dBµV 51 61 dBµV 3 dB sensitivity IF counter sensitivity Muting attenuation 3 dB LS IF-C3 Mute-Att SDC0 = 1, SDC1 = 0, the pin 18 (DO) output 41 100 dBµ V, the pin 12 output 420 mVrms dB 68 dB [FM IF Stereo Characteristics] : fc = 10.7 MHz, fm = 1 kHz, L+R = 90%, Pilot = 10% Separation SEP 100 dBµ V, L-mod, Pin 12 output/pin 13 output Total harmonic distortion (main) THD 100 dBµ V, main modulation, the pin 12 output 28 40 0.5 dB 1.5 % [AM Characteristics] : fc = 1000 kHz, fm = 1 kHz, 30% mod Detector output 1 VO1 23 dBµ V, the pin 12 output 20 40 80 mVrms Detector output 2 VO2 80 dBµ V, the pin 12 output 60 110 160 mVrms Signal-to-noise ratio 1 S/N1 23 dBµ V, the pin 12 output 1.5 20 Signal-to-noise ratio 2 S/N2 80 dBµ V, the pin 12 output 47 54 Total harmonic distortion THD 80 dBµ V, the pin 12 output IF counter sensitivity IF-C The pin 18 (DO) output AM low cut LOW-CUT 80 dBµ V, referenced to fm = 1 kHz, the pin 12 output when fm = 100 Hz. dB dB 1.2 3.0 % 16 26 36 dBµV 5 8 11 dB [Current Drain] FM tuner block ICCFM In FM mode with no input 20 30 40 mA AM tuner block ICCAM In AM mode with no input 10 20 30 mA 1 2 5 mA PLL block IDD fr = 83 MHz, X'tal = 75 kHz, With no input to the tuner block Built-in feedback resistor Rf XIN Built-in output resistor Rd XOUT [PLL Characteristics] 8 MΩ 250 kΩ Hysteresis VHIS CE, CL, DI High-level output voltage VOH PD: IO = –1 mA VOL1 PD: IO = 1 mA VOL2 BO1, BO2: IO = 1 mA VOL2 BO1, BO2: IO = 5 mA 1.25 V VOL3 DO: IO = 1 mA 0.25 V VOL4 Low-level output voltage High-level input current Low-level input current 0.1VDD V VDD – 1.0 V 1.0 V 0.25 V AOUT: IO = 1 mA, AIN = 2.0 V 0.5 V IIH1 CE, CL, DI: VI = 6.0 V 5.0 µA IIH2 XIN: VI = VDD 0.9 µA IIH3 AIN: VI = 6.0 V 0.16 200 nA IIL1 CE, CL, DI: VI = 0 V 5.0 µA IIL2 XIN: VI = 0 V 0.9 µA IIL3 nA 0.16 AIN: VI = 0 V 200 IOFF1 AOUT, BO1, BO2: VO = 10 V 5.0 µA IOFF2 DO: VO = 6.0 V 5.0 µA High-level 3-state off leakage current IOFFH PD: VO = 6.0 V 0.01 200 nA Low-level 3-state off leakage current IOFFL PD: VO = 0 V 0.01 200 nA Output leakage current No. 6903-3/14 (12)TEST (11)IFS (10)PD-C (16)SDC1 (3)IF-CTR (8)DZ-C (7)UNLOCK (6)DO-C (15)SDC0 (14)STSW DI (9)O-PORT (4)IFSW (9)O-PORT (5)BDSW (23)R-CTR (3)IF-CTR (13)Don't care (1)P-CTR P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 SNS DVS CTE DNC R0 R1 R2 R3 DI 0 1 0 BO1 IFSW B02 BDSW1 STSW SDC0 DOC0 DOC1 DOC2 UL0 UL1 DZ0 DZ1 GT0 GT1 SDC1 DLC IFS TEST0 TEST1 TEST2 LV23000M Structure of the DI Control Data (Serial Input Data) (1) IN1 mode Address 0 0 0 1 0 1 0 0 (2) IN2 mode Address 1 0 0 1 0 1 0 0 No. 6903-4/14 LV23000M Description of the DI Control Data No. Control block/data Description Related data • Specifies the divisor used by the programmable dividers. This is a binary value with P15 as the MSB. The LSB depends on DVS and SNS. Programmable divider data (1) DVS SNS LSB Divisor setting (N) Actual divisor 1 * P0 272 to 65535 The actual setting times 2 0 1 P0 272 to 65535 The actual setting 0 0 P4 4 to 4095 The actual setting Note: When P4 is the LSB, bits P0 to P3 are ignored. P0 to P15 DVS, SNS • Selects the input signal (FMIN or AMIN) to the programmable divider and switches the input frequency range. (* : don’t care) DVS SNS Input Operating frequency range 1 * FMIN 10 to 160 MHz 0 1 AMIN 2 to 40 MHz 0 0 AMIN 0.5 to 10 MHz • Data that selects the reference frequency (fref) Reference divider data (2) R0 to R3 R3 R2 R1 R0 Reference frequency 0 0 0 0 25 kHz 0 0 0 1 25 kHz 0 0 1 0 25 kHz 0 0 1 1 25 kHz 0 1 0 0 12.5 kHz 0 1 0 1 6.25 kHz 0 1 1 0 3.125 kHz 0 1 1 1 3.125 kHz 1 0 0 0 5 kHz 1 0 0 1 5 kHz 1 0 1 0 5 kHz 1 0 1 1 1 kHz 1 1 0 0 3 kHz 1 1 0 1 15 kHz 1 1 1 0 PLL INHIBIT + X'tal OSC STOP 1 1 1 1 PLL INHIBIT Note: PLL INHIBIT • In this state, the programmable divider block and the IF counter block are stopped, FMIN, AMIN, and IFIN are pulled down (to ground), and the charge pump goes to the highimpedance state. • Measurement start data for the IF counter CTE = 1: Start the count. = 0: Reset the counter. IF counter control data (3) CTE GT0, GT1 • Determines the measurement time for the general-purpose counter. GT0 GT1 Measurement time 0 0 4 ms Wait time 3 to 4 ms 0 1 8 ms 3 to 4 ms 1 0 16 ms 3 to 4 ms 1 1 32 ms 3 to 4 ms IFS Continued on next page. No. 6903-5/14 LV23000M Continued from preceding page. No. Control block/data Mute control data Description Related data • Determines the output of the IFSW output port and controls the muting function. Data = 0: Receive mode (4) = 1: Muted IFSW FM/AM band switching control data (5) • Determines the output of the BDSW output port and switches the reception band. Data = 0: AM = 1: FM BDSW • Determines the output of the DO pin. DOC2 DOC1 DOC0 0 0 0 DO pin state Open 0 0 1 Low when the unlocked state is detected 0 1 0 end-UC (See the section indicated with the asterisk (*) below.) 0 1 1 Open 1 0 0 Open 1 0 1 Open 1 1 0 Low when stereo detected 1 1 1 Open • The open state is selected after the power on reset. DO pin control data (6) Note: end-UC: The IF counter measurement complete check. UL0, UL1 DOC0 DOC1 DOC2 CTE DO pin ➀ Count start ➁ Count end ➂ CE : HI (1) If the end-UC setting is used, the DO pin will automatically go to the open state when an IF count operation starts (CTE transitions from 0 to 1). (2) When the IF counter measurement completes, the DO pin goes low and it becomes possible to check for the count completed state. (3) The DO pin goes to the open state when serial data I/O is performed (when the CE pin is high). Note: The DO pin goes to the open state during the data input period (IN1 and IN2 modes when CE is high), regardless of the values of the DO pin control data (DOC0:2). During the data output period (OUT mode when CE is high), the DO pin outputs the content of the internal DO serial data in synchronization with the CL signal, regardless of the values of the DO pin control data (DOC0:2). Unlock detection data (7) UL0, UL1 • Phase error (øE) detection width selection data used for PLL lock state discrimination. The unlocked state is recognized when a phase error in excess of the specified detection width occurs. UL1 UL0 øE detection width Detection output DOC0 0 0 Stopped Open DOC1 0 1 0 Directly outputs øE DOC2 1 * ±6.67 µ Extends øE by 1 to 2 ms Note: When the unlocked state is detected, the DO pin goes low and UL in the serial data output will be 0. Continued on next page. No. 6903-6/14 LV23000M Continued from preceding page. No. Control block/data Description Related data • Controls the phase comparator dead band. Phase comparator control data (8) DZ0, DZ1 DZ1 DZ0 Dead band mode 0 0 DZA 0 1 DZB 1 0 DZC 1 1 DZD Dead band widths: DZA < DZB < DZC < DZD Output port data (9) • Sets the outputs from the BO1 and BO2 output ports. Data = 0: Open BO1, BO2 = 1: Low • Forcibly controls the state of the charge pump output. DLC Charge pump control data (10) Charge pump output 0 Normal operation 1 Forced to the low level. DLC If deadlock occurs due to VCO oscillation when the VCO control voltage (Vtune) is 0 V, the deadlock can be released by setting the charge pump output low and setting Vtune to VCC. (This is referred to as a deadlock clear circuit.) (11) IFS • This bit should normally be set to 1. However, setting this bit to 0 sets the device to degraded input sensitivity mode, and the input sensitivity is reduced by about 10 to 30 mV rms. • IC test data IC test data TEST0 TEST1 (12) TEST0 toTEST2 All bits must be set to 0. TEST2 All these bits are set to 0 after the power on reset. (13) DNC Forced mono control data (14) • This bit must be set to 0. • Determines the output of the STSW output port and controls the forced stereo function. Data = 0: Mono = 1: Stereo STSW • Determines the outputs of the SDC0 and SDC1 ports and sets the SD sensitivity. (15) (16) SD sensitivity adjustment data SDC0 SDC1 SDC0 SDC1 SD sensitivity (typ) 0 0 42 dBµV 0 1 45 dBµV 1 0 51 dBµV 1 1 56 dBµV No. 6903-7/14 LV23000M Structure of the DO Control Data (Serial Output Data) (1) OUT mode 0 1 0 1 0 1 0 0 DO (3)IF-CTR (1)IN-PORT DI STIND SDIND 0 UL C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 Address DO Output Data No. Control block/data Stereo indicator SD indicator (1) Control data STIND, SDIND PLL unlocked data UL IF counter Binary counter C19 to C0 Related data • Indicates the states of the stereo and SD indicators at the point latched. The data is latched at the point the devices goes to data output mode (OUT mode). STIND ← Stereo indicator state: 0: ST on, 1: ST off SDINC ← SD indicator state: 0: SD on, 1: SD off • Indicates the state of the unlock detection circuit at the point latched. UL ← 0: Unlocked (2) (3) Description 1: Locked or detection stopped mode. • Indicates the content of the IF counter (20-bit binary counter) at the point latched. UL0 UL1 CTE C19 ← MSB of the binary counter GT0 C0 ← LSB of the binary counter GT1 No. 6903-8/14 LV23000M Serial Data Input (IN1 / IN2) tSU, tHD, tEL, tES, tEH ≥ 0.75µs, tLC < 0.75µs (1) CL: Normally high tEL tES tEH CE CL tSU DI tHD B0 B1 B2 B3 A0 A1 A2 A3 P0 P1 P2 P3 R0 R1 R2 R3 tLC Internal data (2) CL: Normally low tES tEL tEH CE CL tHD tSU DI B0 B1 B2 B3 A0 A1 A2 A3 P0 P1 P2 P3 R0 R1 R2 R3 tLC Internal data Serial Data Output (OUT) tSU, tHD, tEL, tES, tEH ≥ 0.75µs, tDC, tDH < 0.35µs (1) CL: Normally high tEL tEH tES CE CL tSU DI tHD B0 B1 B2 B3 A0 A1 A2 A3 tDC tDC DO I2 I1 tDH UL C3 C2 C1 C0 (2) CL: Normally low tEL tES tEH CE CL tSU DI tHD B0 B1 B2 B3 A0 A1 A2 A3 tDC tDC DO I2 I1 tDH UL C3 C2 C1 C0 Note: Since the DO pin is an n-channel open-drain output, the data transition times (tDC and tDH) depend on the value of the pull-up resistor and the printed circuit board capacitance. No. 6903-9/14 LV23000M Serial Data Timing VIH CE tCH VIH VIL CL VIL tCL VIH VIL VIH tEL VIH VIL VIH tEH tES DI VIL tSU VIL tHD tDC tDC tDH DO tLC Internal data latch Old New <<When CL Stops at the Low Level>> VIH CE CL VIL tCL tCH VIH VIL VIH VIH tEL VIH VIH VIL tES tEH DI VIL VIL tHD tSU tDH tDC DO tLC Internal data latch Old New <<When CL Stops at the High Level>> Parameter Symbol Pins Conditions Ratings min typ max Unit Data setup time tSU DI, CL 0.75 µs Data hold time tHD DI, CL 0.75 µs Clock low-level time tCL CL 0.75 µs Clock high-level time tCH CL 0.75 µs CE wait time tEL CE, CL 0.75 µs CE setup time tES CE, CL 0.75 µs CE hold time tEH CE, CL 0.75 Data latch transition time tLC Data output time tDC DO, CL tDH DO, CE These times depend on the value of the pull-up resistors and the printed circuit board capacitances. µs 0.75 µs 0.35 µs No. 6903-10/14 AM ANT B.P.F 1 AM RF FM RF 36 2 REG GND2 35 3 FM MIX 34 4 GND 1 VCC2 33 5 AM MIX FM OSC 32 6 VCC1 OSC BUFFER AM OSC 31 7 AM IF AM DET 450kHz AGC 30 10.7MHz 8 FM IF FM DET FM S- METER SD 29 ST TRIG LPF 9 IF BUFFER PILOT DET 28 10 27 +B ST SW 11 FF 26 FF FF 12 25 AM Low - cut L- OUT 13 DECODER PHASE COMP VCO 24 R- OUT MUTE 14 VSS 23 VDD 21 15 UNIVERSAL COUNTER 17 REFERENCE DEVIDER 19 18 UNLOCK DETECTOR POWER ON RESET 20 MICROCONTROLLER 16 CCB I/F DATA SHIFT REGISTOR LATCH SWALLOW COUNTER PHASE DETECTOR CHARGE PUMP PROGRAMMABLE DIVIDER 22 VD D Vcc LV23000M LV23000M Block Diagram No. 6903-11/14 AM ANT FM IN REG 2 AM RF IN 1 + GND1 FM MIX 4 Vcc2 3 33 FM RF OUT 10p 34 FM RF 10 Vcc1 6 AM MIX 5 16p 7 + 1µ + + 10 4.7µ 3.3k 9 1µ SW1 0.047µ 8 P-DET P-COMP FM IF IN A-IN A-OUT 27 SW7 4.7k 0.33µ 5.1k BO1 300 51 10k SW8 1k 28 SW9 SW10 0.01µ 29 51k 51k BO2 30 100µ 1k SVC383 0.01µ AM IF IN FM IF IN + AM OSC 0.047µ 31 FM OSC 390p 0.047µ 32 1000p 10 FM OSC 33k SA-181 33k SFU450B 1000p 10µ GND2 39m 35 FM RF IN SVC201 36 0.047µ 51 0.047µ GFWB3 B.P.F 33k SVC201 8p SA-164 100k SFE10.7 MA5 0.047µ 0.047µ 11 FM DET PD 26 0.01µ L-OUT 13 12 0.01µ R-OUT 14 VSS R-OUT 23 L-OUT 24 DET OUT 25 0.01µ 10k 330p AM AGC LOW CUT SW6 22µ + CDA10.7 MG1 Vt=8V + 22 15 CE MPX IN 4.7µ 10p 17 CL 19 SW2 18 DO 51k SW3 SW4 CFV-206 X-IN 10p SW5 X-OUT 20 100k MICROCONTROLLER 16 DI VDD 21 0.1µ 100µ + V DD =3.0V Vcc=5.0V V DD LV23000M LV23000M Test Circuit Diagram No. 6903-12/14 LV23000M 75kHz --10 22.5kHz --30 --40 --50 --60 --70 --80 VCC=5V VDD=3V fc=83MHz fm=1kHz 22.5kHzdev AM=30%mod 0 --10 Output — dBm --20 VCC=5V VDD=3V fc=83MHz fm=1kHz VSM THD(75kHz) THD(22.5kHz) Input — dBµV EMF Input — dBµV EMF AM characteristics AM characteristics VCC=5V VDD=3V fc=1000kHz fm=1kHz 30%mod VAGC — V, Total harmonic distortion,THD — % Output — dBm --20 FM characteristics S-meter voltage, VSM — V, Total harmonic distortion, THD — % FM characteristics 0 --30 --40 --50 --60 --70 --80 VCC=5V VDD=3V fc=1000kHz fm=1kHz --90 Input — dBµV Input — dBµV No. 6903-13/14 LV23000M Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of June, 2001. Specifications and information herein are subject to change without notice. PS No. 6903-14/14