Ordering number : EN*5237 CMOS LSI LC8905V Digital Audio Interface Receiver Preliminary Overview Package Dimensions The LC8905V is for use in IEC 958 and EIAJ CP-1201 format data transmission between digital audio equipment. This LSI is used on the receiving side, and handles synchronization with the input signal and demodulation of that signal to a normal format signal. unit: mm 3175A-SSOP24 [LC8905V] Features • On-chip PLL circuit synchronizes with the transmitted IEC 958 and EIAJ CP-1201 format signal. • Provides 128fs, bit, and L/R clock outputs. • System clock can be selected to be either 384fs or 512fs. • Microprocessor interface code settings for different output types — Input pin, emphasis output, input bi-phase data output, and validity flag output settings — Audio data output format setting — Channel status output (32-bit output for consumer products) — Subcode Q output with CRC flags (80 bits) • Start ID and shortening ID detection for DAT (Digital Audio Tape recorder) that use subcodes • CMOS, single-voltage power supply • Miniature package: SSOP-24 SANYO: SSOP24 SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN D3095HA (OT) No. 5237-1/16 LC8905V Pin Assignment Pin Functions Pin No. Symbol I/O 1 DIN1 I Data input with built-in amplifier (for coaxial or optical module input) Data input (for optical module input) 2 DIN2 I 3 E/DOUT O 4 VDD Description Emphasis, input bi-phase, and validity flag output Power supply 5 R I VCO gain control input 6 VIN I VCO free-running setting input 7 VCO O 8 GND PLL low-pass filter setting Ground 9 CKSEL I 10 XMODE I System clock selection input (384fs or 512fs) Reset input 11 AVOCK I PLL error lock avoidance clock input 12 TST1 I Test input (Must be connected to ground in normal operation) 13 TST2 I Test input (Must be connected to ground in normal operation) 14 SCLK/CL I Microprocessor interface clock input 15 XLAT/CE I Microprocessor interface latch/chip enable input 16 SWDT/DI I Microprocessor interface write data input 17 SRDT/DO O Microprocessor interface read data output 18 DQSY/LD O Microprocessor interface subcode Q and ID synchronization output 19 CKOUT O VCO clock output (free running, 384fs, or 512fs) 20 FS128 O 128fs clock output 21 BCK O Bit clock output 22 LRCK O L/R clock output (left channel = high, right channel = low) 23 DATAOUT O Audio data output 24 ERROR O PLL lock error mute output No. 5237-2/16 LC8905V Block Diagram No. 5237-3/16 LC8905V Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Symbol Maximum supply voltage Conditions Ratings VDD max Unit –0.3 to +7.0 V –0.3 to VDD + 0.3 V Maximum I/O voltages VI VO max Operating temperature Topr –30 to +75 °C Storage temperature Tstg –55 to +125 °C Allowable Operating Ranges Parameter Supply voltage Symbol Conditions VDD min typ max Unit 4.5 5.0 5.5 V Electrical Characteristics DC Characteristics at Ta = –30 to +75°C, VDD = 4.5 to 5.5 V, VSS = 0 V max Unit Input high-level voltage Parameter Symbol VIH1 Applies to the DIN2 pin. TTL levels Conditions 2.2 VDD + 0.3 V Input low-level voltage VIL1 Applies to the DIN2 pin. TTL levels –0.3 +0.8 V Input high-level voltage VIH2 Applies to the CKSEL, AVOCK, TST1, and TST2 pins. CMOS levels 0.7 VDD VDD + 0.3 V Input low-level voltage VIL2 Applies to the CKSEL, AVOCK, TST1, and TST2 pins. CMOS levels –0.3 0.3 VDD V Input high-level voltage VIH3 Applies to the XMODE, SCLK/CL, XLAT/CE, SWDT/DI pins. CMOS Schmitt inputs 0.8 VDD VDD + 0.3 V Input low-level voltage VIL3 Applies to the XMODE, SCLK/CL, XLAT/CE, SWDT/DI pins. CMOS Schmitt inputs –0.3 0.2 VDD V Input high-level voltage VOH IOH = –1 µA Input low-level voltage VOL IOL = 1 µA Current drain IDD VDD = 5.0 V, Ta = 25°C, input data fs = 48 kHz Input amplitude Vpp Measured before the DIN1 pin input capacitor. min typ VDD – 0.05 V VDD + 0.05 10 0.4 15 V mA VDD + 0.3 V max Unit AC Characteristics at Ta = –30 to +75°C, VDD = 4.5 to 5.5 V Parameter Symbol Input pulse width tWBI Output pulse width tWBO Conditions fs = 48 kHz min µs 160 ns ns Output data setup time tDSO 80 Output data hold time tDHO 80 tBD –10 Output delay typ 10 ns 0 +10 ns No. 5237-4/16 LC8905V No. 5237-5/16 LC8905V Microprocessor Interface Block AC Characteristics at Ta = –30 to +75°C, VDD = 4.5 to 5.5 V (when CKSEL is low) Parameter Symbol Conditions min typ max Unit CL low pulse width tWL 100 ns CL high pulse width tWH 100 ns Data setup time tDS 50 ns Data hold time tDH 50 ns CE delay time tD3 1.0 µs 50 CL delay time tD4 CE delay time tD5 LD pulse width tW fs = 44.1 kHz Data delay time tD1 CL = 30 pF 75 ns Data delay time tD2 CL = 30 pF 75 ns ns 100 136 ns µs Input mode Output mode No. 5237-6/16 LC8905V Microprocessor Interface Block AC Characteristics at Ta = –30 to +75°C, VDD = 4.5 to 5.5 V (when CKSEL is high) Parameter Symbol Conditions min typ max Unit CL low pulse width tWL 100 ns CL high pulse width tWH 100 ns Data setup time tDS 50 ns Data hold time tDH 50 ns CE delay time tD 100 µs LD pulse width tW fs = 44.1 kHz Data delay time tD1 CL = 30 pF 75 ns Data delay time tD2 CL = 30 pF 75 ns 136 µs Input mode Output mode No. 5237-7/16 LC8905V Functions 1. Data Input and Output (DIN1, DIN2, E/DOUT) The DIN1 pin has a built-in amplifier, and can receive signals with an amplitude of about 400 mVp-p (coaxial input). The DIN2 pin is only for use with optical modules. Note that although the data input pins are controlled by the microprocessor, DIN1 can be selected when a microprocessor is not used. The microprocessor interface pins must be tied low in such applications. The E/DOUT normally outputs channel status information. However, it can be set to output either the input bi-phase data or the validity flag by command codes from the microprocessor. 2. PLL (R, VIN, VCO, AVOCK) This circuit includes a built-in VCO and supports sampling frequencies of 32, 44.1, and 48 kHz. The resistor connected to R functions as both the VCO gain control and as temperature compensation. The VIN pin sets the VCO free-running frequency. The PLL circuit can be reset within a fixed period when it operates incorrectly, for example, if a lock pull-in failure occurs, by inputting an asynchronous, continuously operating clock signal to the AVOCK pin. 3. Clock Settings and Output (FS128, BCK, LRCK, DATAOUT, CKSEL, CKOUT) A 128fs clock signal is output from the FS128 pin. Figure 1 shows the output timing for the BCK, LRCK, and DATAOUT pins. The CKOUT clock output is set by the CKSEL pin as listed in the table below. CKSEL CKOUT L 384fs clock output H 512fs clock output The microprocessor interface format is also set by CKSEL as listed in the table below. CKSEL Microprocessor interface L Figure 2 H Figure 3 No. 5237-8/16 LC8905V Figure 1 Data Output Timing No. 5237-9/16 LC8905V Figure 2 Microprocessor Interface Timing 1 No. 5237-10/16 LC8905V Figure 3 Microprocessor Interface Timing 2 No. 5237-11/16 LC8905V Microprocessor Interface (SCLK/CL, XLAT/CE, SWDT/DI, SRDT/DO, DQSY/LD) 1. Data input and output addresses are allocated as follows: Figure 2: Microprocessor Interface Timing 1 Data input or output Figure 3: Microprocessor Interface Timing 2 B0 B1 B2 B3 A0 A1 A2 A3 B0 B1 B2 B3 A0 A1 A2 Data input F7 1 1 1 0 1 1 1 1 EA 0 1 0 1 0 1 1 A3 1 C bit output F8 0 0 0 1 1 1 1 1 E9 1 0 0 1 0 1 1 1 Subcode Q, ID output F9 1 0 0 1 1 1 1 1 E8 0 0 0 1 0 1 1 1 2. The input command codes control the following settings: • System stop • Data input pin settings • Input bi-phase data output selection • Validity flag output selection • Audio data output format setting DI1: Stops VCO operation and thus stops the system. DI1 L H System Operating Stopped DI2: Selects which input data to demodulate. DI2 L H Data demodulation input DIN1 DIN2 DI3 and DI4: Select the E/DOUT pin output. DI3 L H DI4 L H L H E/DOUT Emphasis data output Validity flag output DIN1 input data output DIN2 input data output DI5 and DI6: Set the audio data output format. DI5 DI6 DATAOUT L L H H 16-bit right- 20-bit rightjustified justified MSB first LSB first L H 20-bit rightjustified MSB first 20-bit leftjustified MSB first All bits are set low immediately after XMODE is switched from low to high. DI0 and DI7 are not used. No. 5237-12/16 LC8905V 3. The following output settings can be controlled: • Channel status (C bit) output • Subcode Q data output • Status ID and shortening ID detection for DAT that use subcodes C bit output • This function presumes that this IC will be used in consumer mode and thus only handles the first 32 bits. • The flag is fixed at the high level (although there is no flag in the type 1 microprocessor interface timing), and the data format is LSB first. • Error and update checking is not applied to the data. • The internal shift register is reset if a PLL lock error occurs. • An interval of at least 6 msec must be provided between consecutive data readout operations. Subcode Q output • Subcode Q can be read out after the fall of the DQSY/LD signal. Also note that the data is updated every time this signal falls. However, this signal will not be output (fall) unless 96 bits of subcode Q data (include the CRC check bits) is input. • The flag outputs a high when the CRC check passes, and low if the CRC check fails. • The bit order is LSB first within each byte of the 80 bits of subcode Q data. ID detection • The start ID and shortening ID are only detected when the DAT category code (1100000L) is received. • These IDs are detected as follows: — A low pulse is output from DQSY/LD if a start ID (R0) or a shortening ID (L1) is detected following a sync signal (L0). — After this signal, data can be read out from SRDT/DO by inputting the same address value as that used for subcode Q data to SWDT/DI. Figure 4 User Data for DAT that Use Subcodes • The table below shows the relationship between the sync signal (L0), the start ID (R0), the shortening ID (L1), and the data output. (L0): SYNC H (R0): Start ID H L (L1): Shortening ID L H Flags + 80 data bits Detected ID H all H all L Start ID Shortening ID • Output pins The output scheme used for SRDT/DO differs depending on the microprocessor interface format selected by CKSEL. CKSEL Format SRDT/DO L Figure 2 Open-drain output H Figure 3 Three-state output No. 5237-13/16 LC8905V Error (ERROR) The ERROR pin goes high if there is an error in the input data or if the PLL is unlocked. It holds the high level for about 200 to 300 msec after data demodulation returns to normal and then goes low. The table below lists the data processing when an error has occurred. DATAOUT C bit Sub Q ID E/DOUT Up to 8 consecutive parity errors Type of error Previous data value Output Output Output Output Over 8 consecutive parity errors L Output Output Output Output PLL lock error L L L L L System Reset (XMODE) Normal system operation is started by setting XMODE high after the power supply has risen above at least 4.5 V. If XMODE is set low, the VCO free-running oscillator clock is output from CKOUT. Setting XMODE low once again after power on resets the system. No. 5237-14/16 LC8905V Sample Application Circuit No. 5237-15/16 LC8905V ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1997. Specifications and information herein are subject to change without notice. No. 5237-16/16