SEMTECH SC1532

400mA SmartLDO
MOSFET
January 3, 2000
TM
with Internal Pass
SC1532
TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com
DESCRIPTION
Intended for applications such as Power Managed PCI,
the SC1532 is designed to maintain a glitch-free 3.3V
output when at least one of two inputs, 5V (VIN1) and
3.3V (VIN2), is present.
The SC1532 combines a 5V to 3.3V linear regulator
with an integral 3.3V bypass switch, along with logic
and detection circuitry to control which supply provides
the power for the output.
Whenever VIN1 exceeds a predetermined threshold
value, the internal 3.3V PMOS linear regulator is enabled, and the internal pass NMOS is turned off.
When VIN1 falls below a lower threshold value, the
NMOS pass device is turned on and the PMOS linear
regulator is turned off. This ensures an uninterrupted
3.3V output even if VIN1 falls out of specification.
When both supplies are simultaneously available, the
PMOS linear regulator will be turned on, and the
NMOS pass will be turned off, thus preferentially supplying the output from the 5V supply.
FEATURES
• Glitch-free transition between input sources
• Internal logic selects input source
• 5V detector with hysteresis
• 1% regulated output voltage accuracy
• 400mA load current capability
APPLICATIONS
• Desktop Computers
• Network Interface Cards (NICs)
• PCMCIA/PCI Interface Cards
• Peripheral Cards
ORDERING INFORMATION
(1)
Part Number
Package
SC1532CS
SO-8
Note:
(1) Add suffix ‘TR’ for tape and reel packaging.
The internal 5V detector has its upper threshold (for
VIN1 rising) set to 4.18V (typical) while the lower
threshold (for VIN falling) is at 4.1V (typical) giving a
hysteresis of approximately 80mV.
The SC1532 is available in the popular SO-8 surface
mount package.
TYPICAL APPLICATION CIRCUIT
3.3VAUX IN
U1
1
2
3
4
5V IN
3.3V OUT
VIN2
VIN1
VO
CP
GND
GND
GND
GND
8
7
6
5
SC1532
C1
4.7uF
C2
4.7uF
C3
4.7uF
C4
1nF
NOTES:
(1) Ceramic capacitors are recommended - see Applications Information for further details.
(2) Output capacitor C3 needs to be 1.0uF or greater for stability. Additional capacitance (tantalum or ceramic) will
improve overall performance.
1
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
400mA SmartLDO
MOSFET
TM
with Internal Pass
SC1532
January 3, 2000
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Maximum
Units
VIN1, VIN2
-0.5 to +7
V
CP
-0.5 to +16
V
Output Current
IO
400
mA
Operating Ambient Temperature Range
TA
-5 to +70
°C
Operating Junction Temperature Range
TJ
-5 to +125
°C
TSTG
-65 to +150
°C
TLEAD
300
°C
θJA
65
°C/W
ESD
4
kV
Input Supply Voltages
Charge Pump Capacitor Pin Voltage
Storage Temperature Range
Lead Temperature (Soldering) 10 Sec
Thermal Impedance Junction to Ambient
(1)
ESD Rating (Human Body Model)
NOTE:
(1) 1 inch square of 1/16” FR-4, double sided, 1 oz. minimum copper weight.
ELECTRICAL CHARACTERISTICS
Unless specified, TA = 25°C, VIN1 = 5V, VIN2 = 3.3V, IO = 400mA, CIN1 = 4.7uF, CIN2 = 4.7uF, CO = 4.7uF, Cp=1nF.
Values in bold apply over full operating temperature range.
Parameter
Symbol
Test Conditions
MIN
TYP MAX Units
VIN1
VIN2 = 0V
4.3
5.0
5.5
V
IQ1
VIN1 = 5V, 0V ≤ VIN2 ≤ 3.6V, IO = 0mA
2.0
3.0
mA
VIN1
Supply Voltage
Quiescent Current
4.0
(1)
Reverse Leakage From VIN2
IVIN1
VIN1 = 0V, VIN2 = 3.6V, IO = 0mA
0
1
µA
3.3
3.6
V
VIN2
Supply Voltage
VIN2
Quiescent Current
IQ2
3.0
VIN2 = 3.3V, 0V ≤ VIN1 ≤ 5.5V, IO = 0mA
650 1300
µA
2000
(1)
Reverse Leakage From VIN1
IVIN2
VIN1 = 5.5V, VIN2 = 0V, IO = 0mA
Low Threshold Voltage
VTH(LO)
VIN1 Falling, IO = 20mA
3.90
4.10
Hysteresis
VHYST
IO = 20mA
60
80
150
mV
High Threshold Voltage
VTH(HI)
VIN1 Rising, IO = 20mA
4.18
4.30
V
5V Detect
0
1
µA
(1)(2)
V
2
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
400mA SmartLDO
MOSFET
TM
with Internal Pass
SC1532
January 3, 2000
ELECTRICAL CHARACTERISTICS (Cont.)
Unless specified, TA = 25°C, VIN1 = 5V, VIN2 = 3.3V, IO = 400mA, CIN1 = 4.7uF, CIN2 = 4.7uF, CO = 4.7uF, Cp=1nF.
Values in bold apply over full operating temperature range.
Parameter
Symbol
Test Conditions
VO
IO = 20mA
MIN
TYP MAX Units
-1
+1
-2
+2
VO
LDO Voltage Accuracy
4.3V ≤ VIN1 ≤ 5.5V, 0mA ≤ IO ≤ 400mA
(1)
3.90V ≤ VIN1 ≤ 4.3V, VIN2 = 3.3V,
(1)
0mA ≤ IO ≤ 400mA
VIN2 Pass Device On Resistance (Aux. NMOS)
%
V
3.000
RDS(ON)
VIN1 < 3.9V, 0mA ≤ IO ≤ 400mA
360
500
mΩ
REG(LINE)
VIN1 = 4.3V to 5.5V
0.3
0.6
%
(1)(3)
Line Regulation
0.7
Load Regulation
REG(LOAD)
IO = 20mA to 400mA
0.3
0.6
%
0.7
Current Limit (LDO)
Output Current
ILIM
VIN1 = 5V, VIN2 = 0V, VO = 0V
600
975 1200
mA
1400
Over Temperature Protection
High Trip Level
Hysteresis
THI
VIN1=5V
175
ºC
THYS
VIN1=5V
10
ºC
NOTES:
(1) Guaranteed by design.
(2) Recommended source impedance for 5V supply: ≤ 0.125Ω. This will ensure clean transitions between supplies
with no “chattering” (see Applications Information).
(3) Refer to block diagram.
3
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
400mA SmartLDO
MOSFET
TM
with Internal Pass
SC1532
January 3, 2000
BLOCK DIAGRAM
PIN CONFIGURATION
Top View
(SO-8)
PIN DESCRIPTIONS
Pin
Pin Name
Pin Function
1
VIN2
Secondary input supply, nominally 3.3V.
2
VIN1
Main input supply for the IC, nominally 5V.
3
VO
3.3V out.
4
CP
Charge pump capacitor connection.
5
GND
Ground pin.
6
GND
Ground pin.
7
GND
Ground pin.
8
GND
Ground pin.
4
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
400mA SmartLDO
MOSFET
TM
with Internal Pass
SC1532
January 3, 2000
TYPICAL CHARACTERISTICS
Quiescent Current (IQ1) vs.
Junction Temperature vs. VIN2
Quiescent Current (IQ2) vs.
Junction Temperature vs. VIN1
800
2.0
VIN2 = 3.6V
VIN1 = 0V
1.8
700
1.6
600
VIN1 = 5.5V
500
1.2
VIN2 = 0V
1.0
0.8
IQ2 (µA)
IQ1 (mA)
1.4
400
300
0.6
200
0.4
VIN1 = 5V
IO = 0mA
0.2
VIN2 = 3.3V
IO = 0mA
100
0.0
0
-25
0
25
50
75
100
-25
125
0
25
50
75
100
125
100
125
TJ (°C)
TJ (°C)
LDO Output Voltage vs. Junction
Temperature vs. Output Current
LDO Line Regulation vs.
Junction Temperature
3.310
0.40
VIN1 = 5V
VIN2 = 3.3V
3.305
VIN1 = 4.3V to 5.5V
IO = 400mA
0.35
IO = 0mA
0.30
IO = 200mA
VO (V)
3.295
3.290
IO = 400mA
3.285
REG(LINE) (%)
3.300
0.25
0.20
0.15
3.280
0.10
3.275
0.05
3.270
0.00
-25
0
25
50
75
100
125
-25
25
50
75
TJ (°C)
LDO Load Regulation vs.
Junction Temperature
LDO Current Limit vs.
Junction Temperature
1200
0.40
0.35
0
TJ (°C)
VIN1 = 5V
VIN2 = 3.3V
IO = 20mA to 400mA
VIN1 = 5V
VIN2 = 0V
VO = 0V
1000
800
0.25
ILIM (mA)
REG(LOAD) (%)
0.30
0.20
0.15
600
400
0.10
200
0.05
0.00
0
-25
0
25
50
TJ (°C)
75
100
125
-25
0
25
50
75
100
125
TJ (°C)
5
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
400mA SmartLDO
MOSFET
TM
with Internal Pass
SC1532
January 3, 2000
TYPICAL CHARACTERISTICS (Cont.)
VIN2 Pass Device On Resistance vs.
Junction Temperature
5V Detect Threshold Voltage vs.
Junction Temperature
4.30
500
450
400
VIN1 = 0V
VIN2 = 3.3V
IO = 400mA
4.25
VIN2 = 3.3V
IO = 20mA
VTH(HI)
4.20
4.15
300
VTH (V)
RDS(ON) (mΩ
Ω)
350
250
200
4.10
VTH(LO)
4.05
150
4.00
100
3.95
50
0
3.90
-25
0
25
50
75
TJ (°C)
VO(MIN) With VIN1 Rising
100
125
-25
0
25
50
75
100
125
TJ (°C)
(1)(2)
Trace 1: VO, offset 3.3V, 100mV/div.
Trace 2: VIN1 rising through VTH(HI), 2V/div.
VO(MIN) = 3.11V
VO(MIN) With VIN1 Falling
(1)(2)
Trace 1: VO, offset 3.3V, 100mV/div.
Trace 2: VIN1 falling through VTH(LO), 2V/div.
VO(MIN) = 3.05V
NOTES:
(1) In Application Circuit on page 1.
(2) RL = 8.2Ω.
6
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
400mA SmartLDO
MOSFET
TM
with Internal Pass
SC1532
January 3, 2000
TYPICAL CHARACTERISTICS (Cont.)
(1)
Transient Load Response
Trace 1: VO, offset 3.3V, 50mV/div.
Trace 2: IO stepping from 0mA to 400mA
NOTES:
(1) In Application Circuit on page 2.
APPLICATIONS INFORMATION
Introduction
The SC1532 is intended for applications such as power
managed PCI and network interface cards (NICs),
where operation from a 3.3V VAUX supply may be required when the 5V supply has been shut down. It provides a simple, low cost solution that uses very little
pcb real estate. During regular operation, 3.3V power
for the PCI card is provided by the SC1532’s on-board
low dropout regulator, generated from the 5V supply.
When the 5V supply is removed and 3.3V VAUX is
available, the SC1532 connects this supply directly to
its output using an internal NMOS pass device.
Component Selection
Output capacitors - Semtech recommends a 4.7µF or
greater ceramic capacitor at the output for the best
combination of performance and cost effectiveness.
Increasing the capacitance value improves transient
response and glitch performance. The SC1532 is very
tolerant of output capacitor value and ESR variations,
in fact any combination of capacitors with C ≥ 1µF and
ESR < 1Ω is sufficient for stability. This target is easily
met using surface mount ceramic or tantalum capacitors.
Input capacitors - Semtech recommends the use of a
4.7µF ceramic capacitor at both inputs. This allows for
the device being some distance from any bulk capacitance on the rail. Additionally, input droop due to load
transients is reduced, improving load transient response and aiding smooth supply transitions. Tantalum capacitors should not be used.
Charge pump capacitor - Semtech recommends the
use of a 1nF ceramic capacitor between CP and GND.
Thermal Considerations
When operating from the 5V supply, the power dissipation in the SC1532 is approximately equal to the product of the output current and the input to output voltage
differential:
PD ≈ (VIN 1 − VO ) • I O
The absolute worst-case dissipation is given by:
PD ( MAX ) = (VIN1( MAX ) − VO ( MIN ) )• IO ( MAX ) + VIN1( MAX ) • IQ1( MAX )
+ VIN 2 ( MAX ) • IQ 2 ( MAX )
Note that the VIN2(MAX) x IQ2(MAX) term does not apply if
VIN2 is not supplied.
7
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
400mA SmartLDO
MOSFET
TM
with Internal Pass
SC1532
January 3, 2000
APPLICATIONS INFORMATION (Cont.)
Inserting VIN1 = 5.5V, VO = 3.234V, IO = 400mA,
VIN2 = 3.6V, IQ1 = 4mA and IQ2 = 2mA yields:
PD ( MAX ) = 0 . 936 W
Using this figure, we can calculate the maximum thermal impedance allowable to maintain TJ ≤ 125°C at an
ambient temperature of 55°C:
R TH ( J − A )( MAX )
(T
=
J( MAX )
− TA ( MAX ) )
PD ( MAX )
=
(125 − 55 ) = 75 °C / W
0 .936
This is readily achievable using pcb copper area to aid
in conducting the heat away from the device (see Figure 1 below).
VIN1 Source Impedance
In general, this can be avoided by minimizing supply
trace lengths and resistances. In circumstances where
the source impedance is causing supply “chattering”,
increasing the value of the VIN1 input capacitor should
solve the problem by reducing the instantaneous drop
or jump in VIN1 as the supplies are switched.
Layout Considerations
While layout for linear devices is generally not as critical as for a switching application, careful attention to
detail will ensure reliable operation. See Figure 1 below
for a sample layout.
1) Attaching the part (pins 5 to 8) to a larger copper
footprint will enable better heat transfer from the device, especially on PCBs where there are internal
ground and power planes.
2) Place the input and output capacitors close to the
device for optimal transient response.
In order to ensure seamless transitions between supplies with VIN1 rising and falling, it is recommended
that the source impedance of VIN1 is less than
0.125Ω. This is because as the output current
switches from VIN1 to VIN2 and visa-versa, the supplies can “chatter” if:
I O • R SOURCE > VHYST
Top Copper
Top Silk Screen
Fig. 1: Suggested pcb layout based upon Application Circuit on Page 1.
NOTES:
(1) All vias go to ground plane.
(2) Copper area on pins 5 thru 8 is recommended, 0.5” x 0.5” area only is shown. Connect to the ground plane
with a via or vias.
8
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
400mA SmartLDO
MOSFET
TM
with Internal Pass
SC1532
January 3, 2000
OUTLINE DRAWING - SO-8
JEDEC
REF: MS-012AA
MINIMUM LAND PATTERN - SO-8
ECN99-789
9
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320