SEMTECH SC1531CSTR

SC1531(A)
200mA & 250mA SmartLDOsTM
POWER MANAGEMENT
Description
Features
u
u
u
u
Whenever VIN exceeds a predetermined threshold value,
u
the internal 3.3V linear regulator is enabled, and DR is
u
pulled high.
u
When VIN falls below a lower threshold value, DR is pulled u
The SC1531(A) is designed to maintain a glitch-free 3.3V
output when at least one of two inputs, 5V (VIN) and
3.3V (VAUX), is present.
low and the internal linear regulator is turned off. DR has
been designed to drive the gate of an external low
threshold P-channel MOSFET, which can be used to
connect the 3.3V supply directly to the regulator output.
This ensures an uninterrupted 3.3V output even if VIN
falls out of specification. A typical RDS(ON) of 400mW is
recommended (320mW for SC1531A).
Glitch-free transition between input sources
Internal logic selects input source
Gate drive for external PMOS bypass switch
5V detection with hysteresis
1% regulated output voltage accuracy
200mA load current capability (250mA for SC1531A)
Remote sense
SO-8 package
Applications
u
u
u
u
u
Desktop Computers
Network Interface Cards (NICs)
PCMCIA/PCI Interface Cards
CardbusTM Technology
Power supplies with multiple input sources
When both supplies are simultaneously available, the
drive pin (DR) will be pulled High, turning off the external
PMOS switch.
The internal 5V detector has its upper threshold (for VIN
rising) set to 4.18V (typical) while the lower threshold (for
VIN falling) is at 4.05V (typical) giving a hysteresis of
approximately 130mV.
The SENSE pin, which is connected to the load, connects
internally to the inverting input of the LDO error
amplifier. It enables tight regulation of the load voltage
(while the 5V supply is present) despite variations in load
current.
Notes for Typical Application Circuit:
(1) External switch (Q1): use Motorola MGSF1P02ELT1
or equivalent (PMOS, typical Gate Threshold Voltage =
1V, typical RDS(ON) = 0.4W at VGS = 2.5V) for SC1531. Use
Vishay Si2301DS or equivalent for SC1531A.
(2) Connection of VAUX (pin 3) is optional.
The SC1531(A) is available in the popular SO-8 surface
mount package.
Typical Application Circuit
Q1
U1
1
2
3
4
5V
3.3V
C1
0.1uF
Revision 1, December 2000
C2
4.7uF
C3
0.1uF
VIN
DR
NC
VO
VAUX SENSE
GND
NC
SC1531
1
8
7
6
5
3.3V OUT
C4
4.7uF
C5
0.1uF
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SC1531(A)
POWER MANAGEMENT
Absolute Maximum Rating
Parameter
Sy mbol
Maximum
U nits
VIN
-0.5 to +7
V
VAUX
-0.5 to +7
V
LD O Output C urrent (SC 1531)
IO
200
mA
LD O Output C urrent (SC 1531A)
IO
250
mA
Thermal Impedance Juncti on to Ambi ent
q JA
130
°C /W
Thermal Impedance Juncti on to C ase
q JC
47
°C /W
Operati ng Ambi ent TemperatureRange
TA
-5 to +70
°C
Operati ng Juncti on Temperature Range
TJ
-5 to +125
°C
Storage Temperature Range
TSTG
-65 to +150
°C
Lead Temperature (Solderi ng) 10 Sec.
TLEAD
300
°C
ESD Rati ng
V ESD
2
kV
Input Supply Voltage
Auxi li ary Supply Voltage
Electrical Characteristics
Unless specified: TA = 25°C, VIN = 5V, VAUX = 3.3V, IO = max. rated, CO = 4.7µF. Values in bold apply over full operating temperature range.
Parameter
Sy mbol
Test C onditions
Min
Ty p
Max
U nits
VIN
VAUX = 0V
4.3
5.0
5.5
V
IQ
VIN = 5V, VAUX = 0V, IO = 0mA
7.0
10.0
mA
VIN
Supply Voltage
Qui escent C urrent
11.0
VIN = 5V, VAUX = 3.3V, IO = 0mA
7.5
10.0
mA
12.0
Reverse Leakage From VAUX
IVIN
VAUX = 3.6V, VIN = 0V, IO = 0mA
1.0
10
µA
20
VAU X
Supply Voltage
VAUX
Qui escent C urrent
IQ(AUX)
3.0
VAUX = 3.3V, VIN = 0V, IO = 0mA
3.3
3.6
V
0.8
1.5
mA
2.0
VAUX = 3.3V, VIN = 5V, IO = 0mA
0.6
1.0
mA
2.0
Reverse Leakage From VIN
IVAUX
VIN = 5.5V, VAUX = 0V, IO = 0mA
7
50
µA
100
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SC1531(A)
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: TA = 25°C, VIN = 5V, VAUX = 3.3V, IO = max. rated, CO = 4.7µF. Values in bold apply over full operating temperature range.
Parameter
Sy mbol
Test C onditions
Min
Ty p
Max
U nits
Low Threshold Voltage
VTH(LO)
VIN Falli ng
3.90
4.05
4.20
V
Hysteresi s
VHYST
90
200
5V D etect(1)(2)(3)
mV
80
Hi gh Threshold Voltage
VTH(HI)
VIN Ri si ng
VO
IO = 20mA
3.267
4.3V £ VIN £ 5.5V, 0mA £ IO £ IO(MAX)
3.234
3.9V £ VIN £ 4.3V, VAUX = 3.3V,
0mA £ IO £ IO(MAX)(4)
3.000
4.30
V
3.333
V
VO
LD O Output Voltage
Li ne Regulati on
REG(LINE)
VIN = 4.3V to 5.5V
3.300
3.366
0.12
0.40
%
0.60
Load Regulati on
REG(LOAD)
IO = 20mA to IO(MAX)
0.12
0.40
%
0.60
SEN SE
SENSE Pi n Impedance
RSENSE
6.0
8.5
kW
3.4
VIN - 0.8
V
DR
D ri ve Voltage
V DR
4.3V £ VIN £ 5.5V, IDR = 200µA
3.3
VIN < VTH(LO), IDR = -200µA
35
150
mV
200
Peak D ri ve C urrent
D ri ve Hi gh D elay(1)(5)
IDR(PK)
tDH
Si nki ng: VIN = 3.9V, VDR = 1V;
7
Sourci ng: VIN = 4.3V, (VIN - VDR) = 2V
6
C DR = 1.2nF, VIN rampi ng up, measured
mA
0.5
tDL
C DR = 1.2nF, VIN rampi ng down, measured
from VIN = VTH(LO) to VDR = 2V
µs
2.0
from VIN = VTH(HI) to VDR = 2V
D ri ve Low D elay(1)(5)
1.0
0.5
1.0
µs
2.0
See next page for Notes.
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SC1531(A)
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Notes:
(1) Guaranteed by design.
(2) See 5V Detect Thresholds below.
(3) Recommended source impedance for 5V supply: £ 0.25W (0.2W for SC1531A). This will ensure that
IO x RSOURCE < VHYST, thus avoiding DR toggling during 5V detect threshold transitions.
(4) In Application Circuit on page 1.
(5) See Timing Diagram below.
5V Detect Thresholds(1)
Note:
(1) VIN rise and fall times (10% to 90%) to be
³
100µs.
Timing Diagram(1)
Note:
(1) VIN rise and fall times (10% to 90%) to be £ 100ns.
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SC1531(A)
POWER MANAGEMENT
Pin Configuration
Ordering Information
(TOP VIEW)
Part N umber(1)
Output C urrent
P ackag e
SC 1531C S.TR
200mA
SO-8
SC 1531AC S.TR
250mA
SO-8
Note:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.
(SOIC-8)
Block Diagram
Pin Descriptions
Pin
Pin N ame
1
VIN
Thi s i s the mai n i nput supply for the IC , nomi nally 5V.
2
NC
No connecti on.
3
VAUX
Thi s i s the auxi li ary i nput supply, nomi nally 3.3V. C onnecti on of thi s pi n i s opti onal, and wi ll sli ghtly
i mprove the turn-on ti me of the external MOSFET. Leave floati ng i f not used.
4
GND
Logi c and power ground.
5
NC
6
SENSE
7
VO
LD O 3.3V output.
8
DR
D ri ver output for external P-channel MOSFET pass element.
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Pin Function
No connecti on.
Sense pi n for VO. C onnect to VO at the load to mi ni mi ze voltage drop across PC B traces. If
remote sense functi on i s not requi red, connect di rectly to pi n 7.
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SC1531(A)
POWER MANAGEMENT
Typical Characteristics
Quiescent Current vs. Main Input Voltage
Quiescent Current vs. Main Input Voltage
vs. Junction Temperature, VAUX = 0V
vs. Junction Temperature, VAUX = 3.3V
8
10
IO = 0mA
VAUX = 0V
7
IO = 0mA
VAUX = 3.3V
9
8
6
7
IQ (mA)
IQ (mA)
5
4
3
6
5
4
3
2
-5°C
25°C
125°C
1
1
0
0
1
2
3
4
5
-5°C
25°C
125°C
2
0
6
0
VIN (V)
1
2
3
VIN (V)
4
5
6
Auxiliary Quiescent Current vs. Auxiliary Input Voltage
Auxiliary Quiescent Current vs. Auxiliary Input Voltage
vs. Junction Temperature, VIN = 0V
vs. Junction Temperature, VIN = 5V
0.6
0.7
IO = 0mA
VIN = 0V
IO = 0mA
VIN = 5V
0.6
0.5
0.5
IQ(AUX) mA
IQ(AUX) (mA)
0.4
0.3
0.4
0.3
0.2
0.2
-5°C
25°C
125°C
0.1
-5°C
25°C
125°C
0.1
0
0
0
0.3
0.6
0.9
1.2
1.5 1.8 2.1
VAUX (V)
2.4
2.7
3
3.3
3.6
0
0.3
0.6
0.9
1.2
1.5 1.8 2.1
VAUX (V)
2.4
2.7
3
3.3
3.6
LDO Output Voltage vs.
Junction Temperature
3.34
3.33
IO = 200mA
VIN = 5V
3.32
VO (V)
3.31
3.30
3.29
3.28
3.27
3.26
-25
0
25
50
75
100
125
TJ (°C)
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SC1531(A)
POWER MANAGEMENT
Typical Characteristics (Cont.)(1)
Drive High Delay
Drive Low Delay
Trace 1: VIN stepping from 3V to 5.5V
Trace 2: DR going high at VTH(HI)
tDH < 225ns
Trace 1: VIN stepping from 5.5V to 3V
Trace 2: DR going low at VTH(LO)
tDL < 125ns
VO(MIN) With VIN Rising(2)
VO(MIN) With VIN Falling(2)
Trace 1: VIN with 3A charging a 1500uF capacitor
Trace 2: DR going high at VTH(HI)
Trace 3: VO, offset 3.3V. VO(MIN) = 3.19V
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Trace 1: VIN - discharging a 1500uF capacitor
Trace 2: DR going low at VTH(LO)
Trace 3: VO, offset 3.3V. VO(MIN) = 3.14V
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SC1531(A)
POWER MANAGEMENT
Typical Characteristics (Cont.)(1)
Load Transient Response
Load Transient Response
Trace 1: VO
Trace 2: IO stepping from 200mA to 0mA
Trace 1: VO
Trace 2: IO stepping from 0mA to 200mA
Notes:
(1) In Application Circuit on page 1.
(2) IO = 200mA.
Applications Information
Introduction
The SC1531(A) is intended for applications such as power
managed PCI and network interface cards (NICs), where
operation from a 3.3V VAUX supply may be required when
the 5V supply has been shut down. It provides a very
simple, low cost solution that uses very little pcb real
estate. During regular operation, 3.3V power for the PCI
card is provided by the SC1531(A)’s on-board low
dropout regulator, generated from the 5V supply. When
the 5V supply is removed and 3.3V VAUX is available, the
SC1531(A) connects this supply directly to its output
using a tiny SOT-23 external p-channel FET. Connection
of pin 3 (VAUX) to the 3.3V supply is optional, and adds
active pull-down to the Drive pin.
target is easily met using surface mount ceramic or
tantalum capacitors.
Component Selection
P-channel bypass FET - selection of the external FET is
determined by two main requirements:
1) the FET has to have a very low gate threshold
(typically ~1V) in order to be sufficiently turned on with
VGS £ 3.3V.
2) the FET RDS(ON) must be low enough such that:
Input capacitors (5V) - Semtech recommends the use of
a 4.7µF ceramic or tantalum capacitor plus a 0.1µF
ceramic capacitor at the input. This allows for the device
being some distance from any bulk capacitance on the
rail. Additionally, input droop due to load transients is
reduced, improving load transient response.
Input capacitors (3.3V) - Semtech recommends
decoupling this pin (if used) with a 0.1µF ceramic
capacitor.
Output capacitors - Semtech recommends a minimum
bulk capacitance of 4.7µF at the output, along with a
0.1µF ceramic decoupling capacitor. Increasing the bulk
capacitance will improve the overall transient response.
The device is very tolerant of capacitor value and ESR
variations, in fact, any combination of capacitors with
C ³ 4.7µF and ESR < 1W is sufficient for stability. This
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VAUX − (I O ( MAX ) • R DS ( ON ) ) ≥ VO ( MIN )
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SC1531(A)
POWER MANAGEMENT
Applications Information (Cont.)
(Remember that at 125°C, RDS(ON) is generally 1.5x the
value at 25°C.)
This is readily achievable using pcb copper area to aid in
conducting the heat away from the device (see Figure 1
on page 10). Heatsinking the bypass FET is not
necessary - its power dissipation is given by:
Thermal Considerations
PD ( MAX ) = (I O ( MAX ) ) 2 • R DS ( ON )( MAX )
When operating from the 5V supply, the power
dissipation in the SC1531(A) is approximately equal to
the product of the output current and the input to
output voltage differential:
For IO = 200mA, and RDS(ON) = 0.6W, PD = 24mW.
Layout Considerations
PD ≈ (VIN − V OUT ) • I OUT
While layout for linear devices is generally not as critical
as for a switching application, careful attention to detail
will ensure reliable operation. See Figure 1 on page 10
for a sample layout.
The absolute worst-case dissipation is given by:
PD ( MAX ) = (VIN
− VO
( MAX )
( MIN )
)• I
O ( MAX )
+ VAUX
( MAX )
• I Q ( AUX )( MAX )
Note that the VAUX (MAX) x I Q(AUX) term does not apply if
VAUX is not available or not connected.
1) Attaching the part to a larger copper footprint will
enable better heat transfer from the device, especially
on PCBs where there are internal ground and power
planes.
2) Place the bulk and decoupling capacitors close to the
device for optimal transient response.
3) If the SENSE lead is being used, route it to the load
using a seperate trace from the main VO path. If it is not
being used, connect to pin 7 as shown.
4) The external bypass FET is shown close to the device
for convenience only. Since it is not being switched, longer
gate drive traces can be used without problem.
Inserting VIN = 5.5V, VO = 3.234V, IO = 200mA,
VAUX = 3.6V and IQ(AUX) = 2mA yields:
PD ( MAX ) = 0 . 46 W
Using this figure, we can calculate the maximum thermal
impedance allowable to maintain TJ £ 125°C:
R TH ( J − A )( MAX ) =
(T
J( MAX )
− TA (MAX ) )
PD( MAX )
=
(125 − 70 ) = 120 °C / W
0 .46
R TH ( J − C )( MAX ) = 47 °C / W , therefore R TH ( C − A )( MAX ) = 73 °C / W
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SC1531(A)
POWER MANAGEMENT
Application Information (Cont.)
Top Copper
Top Silk Screen
Figure 1: Suggested pcb layout based upon Application Circuit on Page 1.
Bill of Materials (Application Circuit Page 1)
Qty. R eference
P art/D escription
Vendor
3
C 1, C 3, C 5
0.1µF cerami c
Vari ous
2
C 2, C 4
4.7µF cerami c or tantalum
Vari ous
1
Q1
MGS F1P 02E LT1
Motorola
1
U1
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S i 2301D S
S C 1531(A )C S
V i shay
N otes
C 1 not requi red i f VA UX not connected
P -channel, low gate threshold, £ 400mW (S C 1531)
P -channel, low gate threshold, £ 200mW (S C 1531A )
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SC1531(A)
POWER MANAGEMENT
Outline Drawing - SO-8
JEDEC REF: MS-012AA
Land Pattern - SO-8
Contact Information
Semtech Corporation
Power Management Products Division
652 Mitchell Rd., Newbury Park, CA 91320
Phone: (805)498-2111 FAX (805)498-3804
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