SC1544 ACPI Controller for Advanced Motherboards POWER MANAGEMENT Description PRELIMINARY Features K Complete programmable supply for instantly available Semtechs SC1544, SC243x and SC1112A or SC1114 provide all the voltages necessary for an ACPI system. PC systems K Supports 2.5V memory or 3.3V memory (-2.5 or -3.3 The SC1544 offers five independant supplies: a 5V dual supply for USB, a 3.3V dual supply for PCI, a 3.3V or 2.5V dual supply for memory, a 1.5V or 3.3V supply for AGP and a 1.8V supply. The AGP supply is programmble using the system TYPEDET signal. option in part number) K 5V dual and 3.3V dual supplies are programmable to be active or inactive in S5 K Integrated AGP voltage supply with TYPEDET signal An on-board internal charge pump eliminates the need for P-channel MOSFETs and enables function from a single 5V supply (system 5VSB). All dual outputs are over current protected. K K K K K The SC1544 differs from the SC1547 in three important ways: 1) the device initially starts up in S5, and not G0 like the SC1547; 2) the gate drives for the 1.8V and AGP outputs are always high in normal operation; 3) no OCP on the 1.8V and AGP outputs. for 3.3V or 1.5V operation Integrated LDO for 1.8V supply Integrated charge pump removes the need for PMOS FETs, enables single supply operation Over current protection on all dual outputs Inherent soft-start capability TSSOP-24 package Applications K Instantly available motherboards Typical Application Circuit 5V GND C1 100uF/6.3V 3.3V GND C2 100uF/6.3V 5VSB GND C3 100uF/6.3V Q1 IRLR3103 Q2 IRLR3103 5V DUAL GND C4 100uF/6.3V Q3 IRLR3103 Q4 IRLR3103 3.3V DUAL GND C5 100uF/6.3V Q5 IRLR3103 Q6 IRLR3103 3.3V DUAL MEM GND C6 100uF/6.3V Q7 IRLR3103 AGP GND C7 100uF/6.3V Q8 IRLR3103 1.8V GND U1 C8 100uF/6.3V 1 2 3 4 5 6 TYPEDET 7 PWR_OK 8 EN 9 /SLP_S3 10 /SLP_S5 11 USB 12 PCI G5 3.3VDM SC1544-3.3 G8 1.8V G6 G4 G7 3.3VD AGP GND TYPEDET G2/3 PWR_OK G1 EN 5VD /S3 5VSB /S5 FC USB +CAP PCI -CAP 24 23 22 21 20 19 18 17 16 15 14 C10 0.1uF 13 C9 Revision 3, May 2002 1 C11 1uF 0.01uF www.semtech.com SC1544 POWER MANAGEMENT Absolute Maximum Ratings PRELIMINARY Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Input Supply Voltage Symbol Maximum Units V 5V S B -0.6 to 7 V -0.6 to V5VSB V Logic Input Pins Charge Pump Output Voltage V FC -0.6 to 13.2 V Thermal Impedance Junction to Case θJ C 15.6 °C/W Thermal Resistance Junction to Ambient θJ A 83.8 °C/W Operating Ambient Temperature Range TA 0 to 70 °C Operating Junction Temperature Range TJ 0 to 125 °C Storage Temperature Range TSTG -65 to +150 °C Lead Temperature (Soldering) 10 Sec. TLEAD 300 °C Electrical Characteristics(1) Unless specified: all applicable silver box supplies (3.3V, 5V, 5VSB) ± 5%, GND = 0V, VSENSE PINS = VOUT(NOM), TA = 25°C. Values in bold apply over full operating ambient temperature range. Parameter Symbol Test Conditions Min Typ Max Units 4.5 5.0 5.5 V 10 15 mA IN Supply Voltage Quiescent Current V 5V S B IQ All states (S0, S3, S5, disabled) 20 Undervoltage Lockout Threshold Voltage VUVLO V5VSB Rising 3.5 4.0 4.4 V Logic Inputs (EN, PCI, PWR_OK, /S3, /S5, TYPEDET, USB) Logic Pin Sink Current(2) ISINK VBIAS = 5V, all logic pins 0.1 1 µA Logic Pin Source Current ISOURCE EN, VEN = 0V 0.5 3 µA PCI, TYPEDET, USB, VPIN = 0V 50 200 /S3, PWR_OK, VPIN = 0V 100 400 /S5, V/S5 = 0V 150 600 Threshold Voltage 2.4 VIH V VIL 0.8 V 1.836 V 1.8V Output Output Voltage(3) V1.8V 1mA ≤ IOUT ≤ 720mA 1.764 1.746 2002 Semtech Corp. 2 1.800 1.854 www.semtech.com SC1544 POWER MANAGEMENT Electrical Characteristics (Cont.)(1) PRELIMINARY Unless specified: all applicable silver box supplies (3.3V, 5V, 5VSB) ± 5%, GND = 0V, VSENSE PINS = VOUT(NOM), TA = 25°C. Values in bold apply over full operating ambient temperature range. Parameter Symbol Test Conditions Line Regulation(3) REGLINE Load Regulation(3) Min Typ Max Units V5VSB = 4.75V to 5.25V, IOUT = 0A 0.01 0.10 % REGLOAD V5VSB = 5V, IOUT = 0A to 720mA 0.01 0.20 % VG8(HI) V1.8V = 1.7V, IG8 = 10µA VG8(LO) S3, IG8 = -10µA IG8(SOURCE) V1.8V = 1.7V, VG8 = 5V 2 4 IG8(SINK) V1.8V = 1.9V, VG8 = 3V -3.5 -5 I1.8V Sinking, V1.8V = 1.8V -70 -100 -130 µA 1mA ≤ IOUT ≤ 720mA -1.5 VOUT(NOM) +1.5 % 1.8V Output (Cont.) Gate 8 Drive Voltage(4) Gate 8 Drive Current(4) Sense Pin Bias Current 8.00 8.75 0.8 V 1.0 mA 2.5V/3.3V Dual Memory Output Output Voltage(5) V3.3VDM -2.5 +2.5 Line Regulation(5) REGLINE V5VSB = 4.75V to 5.25V, IOUT = 0A 0.01 0.10 % Load Regulation(5) REGLOAD V5VSB = 5V, IOUT = 0A to 720mA 0.01 0.20 % VG5(HI) V3.3VDM = VOUT(NOM) - 100mV, IG5 = 10µA, S0 VG5(LO) IG5 = -10µA, S3 IG5(SOURCE) V3.3VDM = VOUT(NOM) - 100mV, VG5 = 5V, S0 2 4 IG5(SINK) V3.3VDM = VOUT(NOM) + 100mV, VG5 = 3V, S0 -3.5 -5 VG6(HI) V3.3VDM = VOUT(NOM) - 100mV, IG6 = 10µA, S3 8.00 8.75 VG6(LO) IG6 = -10µA, S0 IG6(SOURCE) V3.3VDM = VOUT(NOM) - 100mV, VG6 = 5V, S3 2 4 IG6(SINK) V3.3VDM = VOUT(NOM) + 100mV, VG6 = 3V, S3 -3.5 -5 I3.3VDM Sinking, 3.3V option, V3.3VDM = 3.3V -330 -475 -620 Sinking, 2.5V option, V3.3VDM = 2.5V -215 -310 -405 1mA ≤ IOUT ≤ 720mA 3.250 3.300 3.350 Gate 5 Drive Voltage(6) Gate 5 Drive Current(6) Gate 6 Drive Voltage(7) Gate 6 Drive Current(7) Sense Pin Bias Current 8.00 8.75 0.8 0.8 V 1.0 mA V 1.0 mA µA 3.3V Dual Output Output Voltage(8) V3.3VD 3.217 V 3.383 Line Regulation(8) REGLINE V5VSB = 4.75V to 5.25V, IOUT = 0A 0.01 0.10 % Load Regulation(8) REGLOAD V5VSB = 5V, IOUT = 0A to 720mA 0.01 0.20 % 2002 Semtech Corp. 3 www.semtech.com SC1544 POWER MANAGEMENT Electrical Characteristics (Cont.)(1) PRELIMINARY Unless specified: all applicable silver box supplies (3.3V, 5V, 5VSB) ± 5%, GND = 0V, VSENSE PINS = VOUT(NOM), TA = 25°C. Values in bold apply over full operating ambient temperature range. Parameter Symbol Test Conditions Min Typ VG3(HI) IG3 = 10µA 8.00 8.75 VG3(LO) IG3 = -10µA IG3(SOURCE) VG3 = 5V 0.5 0.7 IG3(SINK) VG3 = 3V -10 -14 VG4(HI) V3.3VD = 3.2V, IG4 = 10µA 8.00 8.75 VG4(LO) V3.3VD = 3.4V, IG4 = -10µA IG4(SOURCE) V3.3VD = VOUT(NOM) - 100mV, VG4 = 5V 2 4 IG4(SINK) V3.3VD = VOUT(NOM) + 100mV, VG4 = 3V -3.5 5 I3.3VD Sinking, V3.3VD = 3.3V -70 -100 VG2(HI) IG2 = 10µA 8.00 8.75 VG2(LO) IG2 = -10µA IG2(SOURCE) VG2 = 5V 0.5 0.7 IG2(SINK) VG2 = 3V -10 -14 VG1(HI) IG1 = 10µA 8.00 8.75 VG1(LO) IG1 = -10µA IG1(SOURCE) VG1 = 5V 0.5 0.7 IG1(SINK) VG1 = 3V -10 -14 I5VD V 5V D = 5 V VAGP 1mA ≤ IOUT ≤ 720mA Max Units 3.3V Dual Output (Cont.) Gate 3 Drive Voltage(9) Gate 3 Drive Current(9) Gate 4 Drive Voltage(10) Gate 4 Drive Current(10) Sense Pin Bias Current 40 0.8 V 100 mV mA V 1.0 mA -130 µA 5V Dual Output Gate 2 Drive Voltage(11) Gate 2 Drive Current(11) Gate 1 Drive Voltage(12) Gate 1 Drive Current(12) Sense Pin Bias Current(2) 40 40 V 100 mV mA V 100 mV mA 16 µA +2.0 % AGP Output Output Voltage(13) -2.0 VOUT(NOM) -3.0 +3.0 Line Regulation(13) REGLINE V5VSB = 4.75V to 5.25V, IOUT = 0A 0.01 0.10 % Load Regulation(13) REGLOAD V5VSB = 5V, IOUT = 0A to 720mA 0.01 0.20 % VG7(HI) VAGP = VOUT(NOM) - 100mV, IG7 = 10µA VG7(LO) VAGP = VOUT(NOM) + 100mV, IG7 = -10µA Gate 7 Drive Voltage(4) 2002 Semtech Corp. 4 8.00 8.75 0.8 V 1.0 V www.semtech.com SC1544 POWER MANAGEMENT Electrical Characteristics (Cont.)(1) PRELIMINARY Unless specified: all applicable silver box supplies (3.3V, 5V, 5VSB) ± 5%, GND = 0V, VSENSE PINS = VOUT(NOM), TA = 25°C. Values in bold apply over full operating ambient temperature range. Parameter Symbol Test Conditions Min Typ Max Units IG7(SOURCE) VAGP = VOUT(NOM) - 100mV, VG7 = 5V 2 4 IG7(SINK) VAGP = VOUT(NOM) + 100mV, VG7 = 3V -3.5 -5 IAGP VAGP = 3.3V, TYPEDET = High -235 -340 -445 VAGP = 1.5V, TYPEDET = Low -70 -105 -140 V 5V S B = 5 V 9.0 9.5 10.0 V 30 50 70 %VOUT 75 ms AGP Output (Cont.) Gate 7 Drive Current(4) Sense Pin Bias Current mA µA FC (Charge Pump) Output Voltage V FC Overcurrent Protection(14) Trip Threshold VTH(OC) Short Circuit Immunity(15) 1 Notes: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required. (2) Guaranteed by design. (3) Applies to S0 only. (4) Gates 7 and 8 are high whenever 5VSB is present and greater than VUVLO, unless the over current protection has been tripped. (5) Applies to S3 sleep state only for 3.3V Dual Memory option. Applies to both S0 and S3 sleep state for 2.5V Dual Memory Option (6) Gate 5 is high in S0 and low in the S3 and S5 sleep states. (7) Gate 6 is high in the S3 sleep state and low in S0 and in the S5 sleep state. (8) Applies to S3 sleep state and S5 sleep state when the PCI pin is high. (9) Gate 3 is high in S0 and low in the S3 and S5 sleep states. (10) Gate 4 is high in the S3 sleep state and the S5 sleep state when the PCI pin is high. Gate 4 is low in S0, and in the S5 sleep state when the PCI pin is low. (11) Gate 2 is high in S0 and low in the S3 and S5 sleep states. (12) Gate 1 is high in the S3 sleep state and the S5 sleep state when the USB pin is high. Gate 1 is low in S0, and in the S5 sleep state when the USB pin is low. (13) Applies to S0 only. VAGP = 3.3V when TYPEDET is high and 1.5V when the TYPEDET pin is low. (14) Applies to 2.5V/3.3V Dual Memory, 3.3V Dual and 5V Dual outputs when enabled only. When an output is disabled, that output is not monitored for OCP. The 1.8V and AGP outputs do not have over current protection. (15) Minimum and maximum time limits for over current protection to trip when powered up (or enabled) into a shorted output and when a short is applied to an enabled, OCP protected output. 2002 Semtech Corp. 5 www.semtech.com SC1544 POWER MANAGEMENT State Diagram Showing Gate Drive Status PRELIMINARY Note: (1) State machine will not allow illegal transitions such as S3 to S5. In order to get to S5 from S3, it is first necessary to enter S0. 2002 Semtech Corp. 6 www.semtech.com SC1544 POWER MANAGEMENT Timing Diagrams PRELIMINARY Startup Normal Operation 2002 Semtech Corp. 7 www.semtech.com SC1544 POWER MANAGEMENT Power Matrix PRELIMINARY This table shows which output is powered from which supply under each system state. System USB State PCI /S3 /S5 PWR_OK 3.3V/2.5V Dual Memory 3.3V D u al 5V D u al 3.3V/1.5V AGP(2) 1.8V(2) 5V 3.3V 3.3V ON ON Comments S0 X(1) X(1) 1 1 1 3.3V 3.3V S3 X(1) X(1) 0 1 0 5V S B 5V S B 5V S B S5 0 0 0 0 0 OFF OFF OFF ON ON All outputs off 0 1 0 0 0 OFF 5V S B OFF ON ON PCI enabled 1 0 0 0 0 OFF OFF 5V S B ON ON USB enabled 1 1 0 0 0 OFF 5V S B 5V S B ON ON PCI & USB enabled Notes: (1) X = dont care. In S0 and S3, the 3.3V dual and 5V dual outputs are not affected by the state of the PCI and USB pins. These outputs are only controlled by the sate of the PCI and USB pins in S5. (2) Gate 7 and Gate 8 are high in all states with 5VSB > UVLO and OCP not tripped. If powered from 3.3V as shown in the table, the AGP and 1.8V outputs are only present in S0, and will ramp with the 3.3V supply as it comes up. This avoids dips in the 3.3V supply which would otherwise occur if Gate 7 and Gate 8 went high after the 3.3V supply came up, demanding high currents to charge output capacitors. If powered from 5VSB they can be used to create 1.5VSB, 1.8VSB or 3.3VSB as required. Gates At A Glance This table shows which gate drive pin controls which MOSFET: Gate Number: Pin Number: Drives the FET betw een: FET mode: 1 18 5V S B 5V Dual pass device 2 19(1) 5V 5V Dual pass device 3 19(1) 3.3V 3.3V Dual pass device 4 22 5V S B 3.3V Dual linear regulator and 5 1 3.3V 3.3V/2.5V Dual Memory pass device/linear regulator(2) 6 3 5V S B 3.3V/2.5V Dual Memory linear regulator 7 4 3.3V AGP linear regulator 8 24 3.3V 1.8V linear regulator Notes: (1) Note common pin for Gate 2 and Gate 3 - both FETs are operating as pass devices only in S0. (2) FET is acting as a pass device for 3.3V Dual Memory and as a linear regulator for 2.5V Dual Memory. 2002 Semtech Corp. 8 www.semtech.com SC1544 POWER MANAGEMENT Pin Configuration PRELIMINARY Ordering Information Top View Part Number P ackag e SC1544TS-X.XTR (1)(2) TSSOP-24 SC1544EVB(3) N/A Notes: (1) Where -X.X denotes voltage options. Available voltages are: 2.5V and 3.3V (2.5V Dual Memory or 3.3V Dual Memory). (2) Only available in tape and reel packaging. A reel contains 2500 devices. (3) Evaluation board for SC1544 - specify voltage option when ordering. TSSOP-24 Block Diagram Marking Information Top View x.x = voltage option (Example: 3.3) yyww = Date code (Example: 0012 xxxxxx = Lot number (Example: P94A01) 2002 Semtech Corp. 9 www.semtech.com SC1544 POWER MANAGEMENT Pin Descriptions PRELIMINARY Pin # Pin Name 1 G5 2 3.3VDM 3 G6 Gate drive for MOSFET between 5VSB and 2.5V/3.3V Dual Memory. 4 G7 Gate drive for MOSFET between VCC3 and 1.5V/3.3V AGP. High when 5VSB is present and greater than UVLO. 5 AGP 6 TYPEDET Select 1.5V or 3.3V for AGP, high = 3.3V. 7 PWR_OK Power_OK signal from silver box. 8 EN Enable signal active high. Connect to 5VSB if not being used. Cycling the enable pin will reset the over current latches. 9 /S3 Pulling this pin low (with /S5 high) causes the device to enter the S3 sleep state. Pulling both /S3 and /S5 low will cause the device to enter the S5 sleep state. 10 /S5 Pulling this pin low along with /S3 causes the device to enter the S5 sleep state. 11 USB Enable pin for 5V Dual during S5 sleep state, high = ON. 12 PC I Enable pin for 3.3V Dual during S5 sleep state, high = ON. 13 -CAP Negative end of charge pump capacitor. Connect a 10nF ceramic capacitor between this pin and pin 14 (+CAP). 14 +CAP Positive end of charge pump capacitor. 15 FC 16 5V S B 17 5V D 18 G1 19 G2/3 Gate drive for MOSFETs between VCC5 and 5V Dual and VCC3 and 3.3V Dual. 20 GND Reference ground. 21 3.3VD 22 G4 23 1.8V 24 G8 2002 Semtech Corp. Pin Function Gate drive for MOSFET between VCC3 and 2.5V/3.3V Dual Memory. Sense pin for 3.3V Dual Memory. Sense pin for 2.5V Dual Memory for 2.5V option. Sense pin for 1.5V/3.3V AGP. Charge pump output (9V nominal). Decouple this pin with a 0.1µF ceramic capacitor. 5V standby supply from silver box. Decouple this pin with a 1µF ceramic capacitor. Sense pin for 5V Dual. Gate drive for MOSFET between 5VSB and 5V Dual. Sense pin for 3.3V Dual. Gate drive for MOSFET between 5VSB and 3.3V Dual. Sense pin for 1.8V LDO. Gate drive for MOSFET between VCC3 (or 5VSB) and 1.8V. High when 5VSB is present and greater than UVLO. 10 www.semtech.com SC1544 POWER MANAGEMENT Typical Applications Circuits PRELIMINARY 5V C1 100uF/6.3V GND 3.3V C2 100uF/6.3V GND 5VSB C3 100uF/6.3V GND Q1 IRLR3103 Q2 IRLR3103 5V DUAL C4 100uF/6.3V GND Q3 IRLR3103 Q4 IRLR3103 3.3V DUAL C5 100uF/6.3V GND Q5 IRLR3103 Q6 IRLR3103 3.3V DUAL MEM C6 100uF/6.3V GND Q7 IRLR3103 AGP C7 100uF/6.3V Q8 IRLR3103 GND 1.8V U1 C8 100uF/6.3V GND 1 2 3 4 5 6 TYPEDET 7 PWR_OK 8 EN 9 /SLP_S3 10 /SLP_S5 11 USB 12 PCI SC1544-3.3 G5 G8 3.3VDM 1.8V G6 G4 G7 3.3VD AGP GND TYPEDET G2/3 PWR_OK G1 EN 5VD /S3 5VSB /S5 FC USB +CAP PCI -CAP 24 23 22 21 20 19 18 17 16 15 14 C10 0.1uF 13 C9 C11 1uF 0.01uF Notes: (1) 3.3V option shown - see below for Q5 configuration for 2.5V option. (2) 1.8V output shown powered from 3.3V. If powered from 5VSB, this becomes 1.8VSB. (3) See Applications Information. 3.3V GND C2 100uF/6.3V D1 5VSB GND C3 100uF/6.3V Q5 Q6 2.5V DUAL MEM GND U1 1 C6 100uF/6.3V 2 3 Q5 body diode in series with D1 to pre-charge 2.5V Dual Memory D1 to ensure that the linear regulator will still regulate 4 5 6 7 8 9 10 11 12 2002 Semtech Corp. 11 G5 2.5VDM G6 G7 SC1544-2.5 G8 1.8V G4 3.3VD AGP GND TYPEDET G2/3 PWR_OK G1 EN 5VD /S3 5VSB /S5 FC USB +CAP PCI -CAP 24 23 22 21 20 19 18 17 16 15 14 13 www.semtech.com SC1544 POWER MANAGEMENT Applications Information Theory Of Operation The SC1544 provides a simple way to power five seperate voltage buses while controlling them correctly using the ACPI control interface (PWR_OK, /SLP_S3 and /SLP_S5). It requires only a single supply rail (5VSB from the system silver box) to operate. An internal charge pump generates the gate voltages required to enable the use of n-channel FETs throughout the design. The external FETs are operated in two discrete modes: 1) as pass devices where VOUT = VIN - (IOUT * RDS(ON)) 2) as linear regulators. Please refer to the Gates At A Glance section on page 8 and the Typical Applications Circuits on page 11 to determine which FETs operate in which mode. PRELIMINARY To prevent false latching due to capacitor inrush currents, low supply rails or momentary overloads, the current limit latch has a timer. If VOUT is above the OCP threshold (VTH(OC)) before the timer times out, then the outputs do not latch. Reducing Commutation Noise The slew rate of the linears is slow enough to provide soft commutation. The non-linear switch outputs (5V and 3.3V Duals) have fast slew rates. It may be necessary to put a resistor in series with the gate to reduce transients (3.3V Dual Memory shown): 3.3V U1 R1 1 Q5 IRLR3103 Linear Mode: the SC1544 contains a bandgap reference trimmed for optimal temperature coefficient which is fed into the inverting input of an error amplifier. The output voltage of each linear regulator (monitored by the sense pin for that output) is divided down internally using a resistor divider and compared to the bandgap voltage. The error amplifier drives the gate of the appropriate external FET to maintain the voltage at the non inverting input, and hence the output voltage. Pass Device Mode: when a particular output is enabled (please refer to the Power Matrix section on page 8) in pass mode (i.e. 5VSB to 5V Dual), the appropriate gate drive will be driven high to turn the FET hard on, minimizing the voltage drop due to IOUT*RDS(ON). The sense pins serve two functions: 1) to sense the output voltage for the linear regulators 2) to sense the output voltage for over current protection Over Current Protection is provided for all dual outputs. OCP is implemented by utilizing the RDS(ON) of the FETs. As the output current increases, the regulation loop maintains the output voltage (linear mode only) by turning on the FET more and more. Eventually, as the RDS(ON) low limit is reached (pass devices are already operating at this point) the FET will be unable to turn on any further and the output voltage will start to fall. When the output voltage falls to approximately 50% of nominal, all outputs are latched off. Toggling the enable pin or cycling 5VSB will reset the latch. 2002 Semtech Corp. 2 10k (typ.) 3 4 3.3V DUAL MEM 5 6 7 8 9 10 11 12 SC1544-3.3 G5 3.3VDM G8 1.8V G6 G4 G7 3.3VD AGP GND TYPEDET G2/3 PWR_OK G1 EN 5VD /S3 5VSB /S5 FC USB +CAP PCI -CAP 24 23 22 21 20 19 18 17 16 15 14 13 Another possible source of commutation noise occurs at startup on 3.3V Dual Memory, when the standby FET, Q6 and the pass-through FET, Q5 are both off. 3.3V Dual Memory will charge to 3.3V minus 0.7V (the drop across the Q5 body diode). When PWR_OK asserts, Q6 turns on shorting 3.3V to 3.3V Dual Memory, pulling it down locally momentarily. This should not be an issue as long as there is sufficient capacitance on 3.3V locally. Another way to reduce this drop is to place a schottky diode across Q5 with the cathode towards 3.3V Dual Memory so this rail charges to 3.3V minus 0.4V, thus reducing the drop when Q5 turns on: 3.3V C1 + TO PIN 1 Increase bulk capacitance (preferred) Q5 IRLR3103 D1 (optional) TO PIN 2 3.3V DUAL MEM 12 www.semtech.com SC1544 POWER MANAGEMENT Applications Information (Cont.) PRELIMINARY Linear Regulator Stability For the 2.5V Dual Memory linear regulator: When extremely low ESR capacitors (Oscons, Polymers, high value ceramics) are used on outputs requiring fast transients (3.3V/2.5V memory), the linear regulators may exhibit some overshoot and/or transient instability. External compensation may be necessary (5VSB to 3.3V Dual Memory shown): R2 ≤ 2.5 350µA • 100 ≤ 71 Ω 2.5V < VOUT (AJUSTED) < 3.3V GND C6 100uF/6.3V R1 I SENSE U1 1 2 U1 3.3V DUAL MEM 1 R1 1k 2 3 C1 22nF 4 Q6 IRLR3103 5 6 7 5VSB 8 9 10 11 12 VOUT (FIXED) SC1544-3.3 G5 3.3VDM G6 G7 AGP G8 1.8V G4 3.3VD GND TYPEDET G2/3 PWR_OK G1 EN /S3 /S5 5VD 5VSB FC USB +CAP PCI -CAP 4 22 5 21 6 20 7 19 8 18 9 17 10 16 11 15 12 C2 Ceramic - high frequency decoupling It is possible to adjust the output voltage of the linear regulators (1.8V, 2.5V Dual Memory and AGP) by applying an external resistor divider to the sense pin (see below). Since the sense pins sink a nominal 100µA (1.8V LDO, 150µA for the 1.5V AGP LDO, 325µA for the 3.3V AGP LDO and 350µA for the 2.5V Dual Memory LDO), the resistor values should be selected to allow 100x that current to flow through the divider. This will ensure that variations in the sense current will have negligible affect on the output voltage regulation. Thus a target value for R2 (maximum) can be calculated: VOUT(FIXED ) ISENSE • 100 Ω 2002 Semtech Corp. G8 1.8V G6 G4 G7 3.3VD AGP GND TYPEDET G2/3 PWR_OK G1 EN 5VD /S3 5VSB /S5 FC USB +CAP PCI -CAP 24 23 22 21 20 19 18 17 16 15 14 13 13 Adjusting the Output Voltage of the Linear Regulators R2 ≤ 2.5VDM SC1544-2.5 14 3.3V DUAL MEM + R2 23 Another possibility is to use dual capacitor types for the load capacitor - a ceramic capacitor will provide high frequency decoupling for the load while an electrolytic capacitor (high ESR) will tame the Q to prevent instability: C1 Electrolytic - bulk 3 24 G5 The output voltage can only be adjusted upwards from the fixed output voltage, and can be calculated using the following equation: R1 VOUT( ADJUSTED ) = VOUT(FIXED ) • 1 + + R1 • ISENSE Volts R 2 Therefore to set the 2.5V Dual Memory linear regulator to 2.6V, for example, R1 = 2.8Ω and R2 = 69.8Ω. The maximum voltage to which an output can be set using this method is limited by the input voltage to the FET(s) and the RDS(ON) of the FET(s). Please note that this technique cannot be used for the 3.3V Dual Memory, 3.3V Dual and 5V Dual outputs since the output is switched via a pass device (i.e. not regulated) when not in S0. Fault Protection Hints Loss of AC Power: if it is possible during brownouts or momentary loss of AC power to the computer silver box that PWR_OK can assert low while S3 and S5 remain high then the over current protection may trigger. This is because the state machine will ignore this illegal transition and monitor all outputs as if they are still in S0, despite the fact that the inputs are going away. If 5VSB decays slowly, S3 and S5 remain high, and one output drops below the OCP threshold for long enough 13 www.semtech.com SC1544 POWER MANAGEMENT Applications Information (Cont.) PRELIMINARY Fault Protection Hints (Cont.) that the OCP times out then the outputs will latch off. Then if the AC power returns after the OCP latches off, but before the 5VSB supply drops below UVLO, then the device will not start up again until EN or 5VSB is cycled. One way to avoid this happening is to force the device into S3 if PWR_OK goes low but S3 and S5 remain high using the circuit shown below. This will supply the outputs from 5VSB which will either cause 5VSB to drop below UVLO and reset the part when the AC power comes back up, or it may prevent OCP occuring at all. Either way correct functionality will be guaranteed once AC power returns. U1 1 2 3 4 5 6 7 PWR_OK 8 D1 1N4148 9 /SLP_S3 10 R1 4.7k 11 12 SC1544-2.5 G5 G8 2.5VDM 1.8V G6 G4 G7 3.3VD AGP GND TYPEDET G2/3 PWR_OK G1 EN 5VD /S3 5VSB /S5 FC USB +CAP PCI -CAP 24 23 22 21 20 19 18 17 16 15 14 13 Incorrect Signals From Silver Box: Some silver boxes have been found that produce incorrect voltages on the PWR_OK line, producing dangerous negative voltage spikes up to -1V or greater. Such spikes exceed the absolute maximum ratings for this device and can cause the device to malfunction. If a supply produces such spikes they can be clamped to GND using a small schottky diode as shown below, completely removing any threat. U1 1 2 3 4 5 6 7 PWR_OK 8 D1 9 10 11 12 2002 Semtech Corp. G5 2.5VDM SC1544-2.5 G8 1.8V G6 G4 G7 3.3VD AGP GND TYPEDET G2/3 PWR_OK G1 EN 5VD /S3 5VSB /S5 FC USB +CAP PCI -CAP 24 23 22 21 20 19 18 17 16 15 14 13 14 www.semtech.com SC1544 POWER MANAGEMENT Outline Drawing - TSSOP-24 PRELIMINARY Land Pattern - TSSOP-24 Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 2002 Semtech Corp. 15 www.semtech.com