TA1317ANG TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic TA1317ANG Deflection Processor IC for TV TA1317ANG is a deflection processor IC for a large and wide picture tube. TA1317ANG incorporates an EW, a vertical distortion correction circuit and a dynamic focus correction circuit. It can control various functions via I2C BUS line. Features • Vertical drive (AC/DC-coupling) • Picture height adjustment • Vertical shift adjustment • Vertical symmetry correction • Vertical linearity correction • Vertical S correction • Vertical integral correction • Vertical/Horizontal EHT compensation • EW drive (parabola/PWM output) • Picture width • EW trapezium correction • EW parabola correction • EW corner correction (top only/bottom only/top & bottom) • EW S correction • Center curve correction (SAW/PAR) • Parabola output for horizontal and vertical dynamic focus (H/V output independently) • Horizontal and vertical dynamic focus phase adjustment • Horizontal and vertical dynamic focus amplitude adjustment • Horizontal dynamic focus curve characteristic adjustment • V-ramp limiter circuit • Analog blanking output Weight: 1.22 g (typ.) 1 2005-08-18 TA1317ANG V SYMMETRY V→I V LINEARITY V-S CORRECTION DIGITAL GND SCL SDA PULSE GENE H-DF OUT V-RAMP LVP IN AGC V-DF OUT 22 CENTER OUT TC FILTER 23 BLK OUT V-RAMP FILTER 24 VIN AGC FILTER Block Diagram 21 20 19 18 17 16 15 14 13 ANALOG BLK CENTER OUT LVP DETECT + CENTER PARABOLA CENTER SAW V- ∫∫ CORRECTION + I CBUS DECODER V-DF AMP H-DF OUT V→I V-DF PHASE EW-S CORRECTION EW CORNER V→I + EW TRAPEZIUM V AMP + H-DF PHASE EW AMP V EHT V GUARD DETECT V→I H-DF BATHTUB H EHT V-RAMP LIMITER DAC 2 V-DF OUT EW WIDTH H-RAMP V PHASE 2 EHT IN V DRIVE V-DC REF V NF 7 8 9 10 11 12 FBP IN 6 EW FILTER 5 EW FD 4 ANALOG GND 3 EW PWM 2 VCC 1 CENTER DAC EW PWM VREF BAND-GAP 2005-08-18 TA1317ANG Pin Functions Pin No. Pin Name Function Interface Circuit Input/Output Signal 10 kΩ 1 ⎯ 10.3 kΩ VREF 1 kΩ 40 kΩ 1 Internal reference voltage adjustment pin. If the CRT DY has a temperature coefficient, it can be cancelled in the TV by applying the inverse temperature coefficient to this pin. In case of not using it, connect a 0.01 µF capacitor between this pin and GND. 1 kΩ 7 9 CENTER DAC DC 2 5 kΩ 2 DAC output pin. When bus write function VD = 0, 2 bit DAC output; VD = 1, 7 bit DAC output. In case of not used, it should be open. 50 Ω 7 9 7 EHT IN DC 3 11 kΩ 4.5 V 3 EHT input pin. In case of not using it, connect a 0.01 µF capacitor between this pin and GND. 10 kΩ 9 7 V DRIVE Vertical output pin 100 Ω 4 30 kΩ ⎯ 4.5 kΩ 4 9 3 2005-08-18 TA1317ANG Pin No. Pin Name Function Interface Circuit Input/Output Signal 1 kΩ 7 V-DC REF DC 30 kΩ 5 DC reference voltage output pin when V is DC coupling. In case of not used, it should be open. 5 kΩ 5 40 kΩ 9 6 7 V NF VCC Vertical negative feedback input pin. When VD = 0, if pin is 1.2 V (typ.) or below, or 3.7 V (typ.) or higher, returns abnormal detection result to BUS read function (V guard), forcibly setting pin 20 to High. When VD = 1, if pin is 2.4 V (typ.) or below, or 7.4 V (typ.) or higher, abnormality is detected. 7 12.5 kΩ 6 50 Ω 9 VCC pin. Connect 9 V (typ.). ⎯ ⎯ 7 8 EW PWM EW D drive (PWM) output pin. Open collector output. In case of not used, it should be open. 8 9 9 ANALOG GND GND pin for analog block ⎯ ⎯ 7 10 EW FD EW feedback pin 10 60 kΩ 9 4 2005-08-18 TA1317ANG Pin No. Pin Name Function Interface Circuit Input/Output Signal 7 EW FILTER 100 Ω 11 ⎯ 100 Ω 500 Ω 11 Connect phase compensation filter for EW output. The EW parabola waveform can be extracted from this pin. 9 7 Th: 2.25 V Input frequency: 28 k~45 kHz 2.25 V FBP IN 500 Ω 12 5.0 V 12 FBP input pin. In case of H-DF and EW-PWM outputs are not used, it should be open. 9 15 7 SDA 2 SDA pin for I C bus 50 Ω 20 kΩ 13 SDA 3V 13 Th: 2.25 V ACK 15 7 SCL 2 SCL pin for I C bus 20 kΩ 14 SCL 3V 14 Th: 2.25 V 15 15 DIGITAL GND ⎯ GND pin for digital block 5 ⎯ 2005-08-18 TA1317ANG Pin No. Pin Name Function Interface Circuit Input/Output Signal H-DF OUT H-BLK 200 Ω 1 kΩ 16 22.5 kΩ 16 Outputs parabola waveform for horizontal dynamic focus. Mask the pulse in horizontal blanking if it is not needed. In case of not used, it should be open. 100 Ω 7 H-DF OUT 9 15 LVP IN 7 3 kΩ 17 DC 5V 17 LVP detection pin. Connect reference voltage used to protect deflection circuit against low supply voltage. If this pin is 5.0 V (typ.) or below, returns abnormal detection result to bus read function. In case of LVP detection is not used, it should be open. 9 7 V-DF OUT 100 Ω 18 2 kΩ 1 mA 18 Outputs parabola waveform for vertical dynamic focus. In case of not used, it should be open. 9 CENTER OUT or 19 1 kΩ 22.5 kΩ 19 Outputs center curve correction waveform. Connect this pin to curve correction input pin of horizontal sync IC. In case of not used, it should be open. 100 Ω 7 9 6 or composite of above two waveforms 2005-08-18 TA1317ANG Pin No. Pin Name Function Interface Circuit Input/Output Signal 20 BLK OUT 200 Ω Analog blanking output pin. Open collector output. In case of not used, it should be open. 200 Ω 7 1 kΩ 20 9 7 21 VIN Inputs vertical trigger pulse. Notifies subsequent circuit of input fall as trigger. Th: 1.5 V 2 kΩ 21 9 7 22 TC FILTER Connects filter for generating internal pulse. 100 Ω 22 ⎯ 10 kΩ 9 7 1 kΩ 23 23 V-RAMP FILTER Connects filter for generating vertical ramp signal. 100 Ω ⎯ 1 kΩ 9 7 2005-08-18 TA1317ANG Pin No. Pin Name Function Interface Circuit Input/Output Signal 24 8 2.25 V AGC FILTER 3.2 V 24 Connects filter used to automatically adjust oscillation amplitude of vertical ramp signal. Can switch AGC sensitivity by BUS write function. 500 Ω 500 Ω 7 1 kΩ ⎯ 9 2005-08-18 TA1317ANG Bus Control Map Write Mode Slave Address: 8CH (10001100) Sub-Address D7 MSB D6 D5 D4 D3 D2 D1 PICTURE HEIGHT 00 PICTURE WIDTH1 01 D0 LSB Preset MSB LSB VD 1000 0000 1000 0000 V SHIFT V LINEARITY V-EHT COMPENSATION 1000 0000 03 ANALOG V-BLK STOP PHASE H-EHT COMPENSATION 1000 0000 04 ANALOG V-BLK START PHASE V-RAMP LIMIT2 1000 0000 1000 0000 02 V CENTERING 05 V-RAMP LIMIT1 06 V-DF PHASE V-DF AMPLITUDE 1000 1000 07 H-DF PHASE H-DF AMPLITUDE 1000 1000 08 H-DF CURVE V INTEGRAL CORRECTION 1000 0000 V AGC 09 0A * * V S CORRECTION 1000 0000 EW PARABOLA 1000 0000 V STOP 1000 0000 EW TRAPEZIUM 0B 0C EW TOP CORNER * * PICTURE WIDTH2 1000 0000 0D EW BOTTOM CORNER * * * 1000 0000 0E EW S CORRECTION * * * 1000 0000 0F EW CORNER * * * 1000 0000 CENTER PARABOLA 10 CENTER SAW V SYMMETRY 11 1000 1000 0000 0000 Read Mode Slave Address: 8DH (10001101) 0 D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB V DF H DF LVP V NF V GUARD EW OUT V OUT POR 9 2005-08-18 TA1317ANG Bus Control Function Write Mode Register Name/Number of Bits PICTURE HEIGHT/7 Function Explanation Output Change Picture Change Preset Adjusts the picture height. 0000000: min 1000000: center 1111111: max Solid line Dashed line center (1000000) Pin 6 VD/1 Changes V-DRIVE mode 0: DC-coupling PICTURE WIDTH/7 ⎯ 1: AC-coupling DC-coupling ⎯ (0) Adjusts the picture width. 0000000: max 1000000: center 1111111: min Solid line Dashed line center Sub-address 0C-D0 bit comes LSB. (1000000) Pin 11 V SHIFT/2 Where VD = 0, sets DAC output level of pin 2 is set. Where VD = 1, sets DC level of V-DRIVE is adjusted. Solid line 00: min Dashed line min 11: max Pin 6 (VD = 1) (00) VD = 1 V LINEARITY/5 Corrects the vertical linearity. 00000: min 10000: center 11111: max Solid line Dashed line center Pin 6 10 (10000) 2005-08-18 TA1317ANG Register Name/Number of Bits V-EHT COMPENSATION/3 Function Explanation Output Change Picture Change Adjusts the compensated rate for the V-DRIVE by EHT-IN (pin 3). 000: min Solid line 111: max Dashed line min Pin 6 ANALOG V-BLK STOP PHASE/5 Sets the analog blanking stop phase on pin 20. Inputs the output from pin 20 to an external BLK-IN of synchronization IC. 00000: min H-EHT COMPENSATION/3 10000: center 11111: max (000) Solid line Dashed line center ⎯ (10000) Adjusts the compensated rate for the EW output by EHT-IN (pin 3). 000: min Solid line 111: max Dashed line min (000) Pin 11 ANALOG V-BLK START PHASE/5 Sets the analog blanking start phase on pin 20. Inputs the output from pin 20 to external BLK-IN of synchronization IC. 00000: min V-RAMP LIMIT LEVEL/4 Preset 10000: center 11111: max Solid line Dashed line center ⎯ (10000) Sets the V-ramp slice level. 0000: OFF 0001: min 1111: max ⎯ Sub-address 05-D0 bit comes MSB. Pin 6 11 OFF (0000) 2005-08-18 TA1317ANG Register Name/Number of Bits V CENTERING/7 Function Explanation Output Change Picture Change Preset Where VD = 0, DC level of V-DRIVE is adjusted. Where VD = 1, DAC output level of pin 2 is set. Solid line 0000000: min Dashed line min 1000000: center Pin 6 (VD = 0) 1111111: max (0000000) VD = 0 V-DF PHASE/4 Adjusts the phase of the vertical dynamic focus output. 0000: min 1000: center 1111: max ⎯ center (1000) Pin 18 V-DF AMPLITUDE/4 Adjusts the amplitude of the vertical dynamic focus output. 0000: min 1000: center 1111: max ⎯ center (1000) Pin 18 H-DF PHASE/4 Adjusts the phase of the horizontal dynamic focus output. 0000: min 1000: center 1111: max ⎯ center (1000) Pin 16 12 2005-08-18 TA1317ANG Register Name/Number of Bits H-DF AMPLITUDE/4 Function Explanation Output Change Picture Change Preset Adjusts the amplitude of the horizontal dynamic focus output. 0000: min 1000: center 1111: max center ⎯ (1000) Pin 16 H-DF CURVE/4 Adjusts the curve characteristic of the horizontal dynamic focus output. 0000: max 1111: min max ⎯ (0000) Pin 16 V INTEGRAL CORRECTION/4 Adjusts the vertical integral correction. 0000: min 1111: max Solid line Dashed line min (0000) Pin 6 V AGC/2 Sets the AGC gain for V-ramp. V S CORRECTION/6 Adjusts the vertical S correction. 00: LOW 000000: min ⎯ 11: HIGH 100000: center 111111: max LOW ⎯ Solid line (00) Dashed line min (000000) Pin 6 EW PARABOLA/6 Adjusts the amplitude of the EW output. 000000: min 111111: max Solid line Dashed line min (000000) Pin 11 13 2005-08-18 TA1317ANG Register Name/Number of Bits EW TRAPEZIUM/7 Function Explanation Output Change Picture Change Preset Adjusts the EW trapezium correction. 0000000: min 1000000: center 1111111: max Solid line Dashed line center Note: When this data is changed, V symmetry characteristic will be also changed. V STOP/1 (1000000) Pin 11 Switches over the V-stop mode. 0: Normal 1: V stop/BLK stop Normal ⎯ (0) Pin 6 EW TOP CORNER/5 Adjusts the EW top corner correction. 00000: max 10000: center 11111: min Solid line Dashed line center (10000) Pin 11 EW BOTTOM CORNER/5 Adjusts the EW bottom corner correction. 00000: max 10000: center 11111: min Solid line Dashed line center (10000) Pin 11 EW S CORRECTION/5 Adjusts the EW S correction. 00000: max 10000: center 11111: min Solid line Dashed line center (10000) Pin 11 14 2005-08-18 TA1317ANG Register Name/Number of Bits EW CORNER/5 Function Explanation Output Change Picture Change Preset Adjusts the EW corner correction. 00000: max 10000: center 11111: min Solid line Dashed line center (10000) Pin 11 CENTER PARABOLA/4 Adjusts the parabola-component amplitude. 0000: max 1000: center 1111: min Solid line Dashed line center Pin 19 (1000) CENTER SAW/4 Adjusts the saw-component amplitude. 0000: min 1000: center 1111: max Solid line Dashed line center Pin 19 (1000) V SYMMETRY/8 Corrects the vertical symmetry. 00000000: min 10000000: center 11111111: max Note: When this data is changed, EW trapezium characteristic will be also changed. 15 Solid line Pin 6 Dashed line center (10000000) 2005-08-18 TA1317ANG Read Mode Register Name/Number of Bits V DF/1 Function Explanation Vertical dynamic focus output self-check. 0: NG (no) H DF/1 Horizontal dynamic focus output self-check. 0: NG (no) LVP/1 1: OK (yes) V-DRIVE output self-check. 0: NG (no) POR/1 1: ON (abnormal) EW output self-check. 0: NG (no) V OUT/1 1: OK (yes) Detects abnormality on V-NF input. If abnormal, Pin 20 goes high. 0: OFF (normal) EW OUT/1 1: ON (pin 17 is low) V-NF input self-check. 0: NG (no) V GUARD/1 1: OK (yes) LVP (low voltage protection) is detected. 0: OFF (pin 17 is high) V NF/1 1: OK (yes) 1: OK (yes) Power-on reset. Responds with 0 at first reading after power-on, 1 at second reading. 0: Resister preset 1: Normal 16 2005-08-18 TA1317ANG 2 Data Transfer Formats via I C Bus Slave address A6 A5 A4 A3 A2 A1 A0 W/R 1 0 0 0 1 1 0 0/1 Start and Stop Condition SDA SCL S P Start condition Stop condition Bit Transfer SDA SCL Change of SDA allowed SDA stable Acknowledge SDA by transmitter Bit 9: High impedance SDA by receiver Only bit 9: Low impedance SCL from master 1 8 9 S Clock pulse for acknowledge 17 2005-08-18 TA1317ANG Data Transmit Format 1 S Slave address 7 bit 0 A MSB S: Start condition Sub address 8 bit A Transmit data 9 bit A P MSB MSB A: Acknowledge P: Stop condition Data Transmit Format 2 S Slave address 0 A Sub address ･･････ A Transmit data Sub address A A ･･････ Transmit data n A P Data Receive Format S Slave address 7 bit 1 A Receive data 8 bit A P MSB MSB At the moment of the first acknowledge, the master transmitter becomes a receiver and the slave receiver becomes a transmitter. The Stop condition is generated by the master. Optional Data Transmit Format: Automatic Increment Mode S Slave address 7 bit 0 A 1 MSB Sub address 7 bit A Transmit data 1 8 bit MSB MSB ････ Transmit data 2 8 bit A P MSB In this transmission method, sub-addresses are incremented automatically and data is set from the specified sub-address. I2C BUS Conditions Characteristics Symbol Min Typ. Max Unit Low level input voltage VIL 0 ⎯ 1.5 V High level input voltage VIH 2.7 ⎯ Vcc V VOL1 0 ⎯ 0.4 V Input current each I/O pin with an input voltage between 0.1 VDD and 0.9 VDD Ii −10 ⎯ 10 µA Capacitance for each I/O pin Ci ⎯ ⎯ 10 pF fSCL 0 ⎯ 100 kHz Low level output voltage at 3 mA sink current SCL clock frequency tHD;STA 4.0 ⎯ ⎯ µs Low period of SCL clock tLOW 4.7 ⎯ ⎯ µs High period of SCL clock tHIGH 4.0 ⎯ ⎯ µs Set-up time for a repeated START condition tSU;STA 4.7 ⎯ ⎯ µs Data hold time tHD;DAT 100 ⎯ ⎯ ns Data set-up time tSU;DAT 250 ⎯ ⎯ ns Set-up time for STOP condition tSU;STO 4.0 ⎯ ⎯ µs tBUF 4.7 ⎯ ⎯ µs Hold time START condition Bus free time between a STOP and START condition 18 2005-08-18 TA1317ANG Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating Unit VCCmax 12 V Input pin voltage Vin GND − 0.3 to VCC + 0.3 V Power dissipation PD (*) 1250 mW Power dissipation reduction rate 1/θja −10 mW/°C Operating temperature Topr −20~65 °C Storage temperature Tstg −55~150 °C Power supply voltage *: See the figure below. PD (mW) 1250 Power dissipation 850 0 0 25 65 Ambient temperature 150 Ta (°C) Figure 1 PD – Ta Curve Operating Conditions Characteristics Description Min Typ. Max Unit Supply voltage (VCC) Pin 7 8.5 9.0 9.5 V EHT input voltage Pin 3 0.0 ⎯ 9.0 V FBP input amplitude Pin 12 4.0 ⎯ 9.0 V FBP input frequency Pin 12 28 ⎯ 45 kHz FBP input width Pin 12 2.5 ⎯ ⎯ µs SCL/SDA pull-up voltage Pins 13 & 14 3.0 5.0 9.0 V LVP input voltage Pin 17 0.0 ⎯ 9.0 V V input amplitude Pin 21 3.0 ⎯ 9.0 V V input frequency Pin 21 50 ⎯ 120 Hz V input width Pin 21 2.5 ⎯ ⎯ µs EW PWM input current Pin 8 ⎯ ⎯ 5 mA 19 2005-08-18 TA1317ANG Electrical Characteristics (unless otherwise specified, VCC = 9 V, Ta = 25°C) Current dissipation Pin Name Symbol Test Circuit Min Typ. Max Unit VCC ICC ⎯ 40 50.8 62 mA Pin voltages Pin No. Pin Name Symbol Test Circuit Min Typ. Max Unit 1 VREF V1 ⎯ 4.60 4.88 5.10 V 5 V -DC REF V5 ⎯ 4.60 4.88 5.10 V Min Typ. Max Unit 1.2 1.5 1.7 V 3.90 4.10 4.30 2.95 3.15 3.35 0.97 1.07 1.17 AC Characteristics Characteristics Vertical trigger input shaped voltage Timing pulse output voltage Vertical ramp wave amplitude Vertical drive amplification Vertical drive output voltage Vertical NF signal amplitude Vertical phase adjustment 1 (V shift) change amount Vertical phase adjustment 2 (V centering) change amount Vertical amplitude adjustment (picture height) change amount Vertical linearity correction (V linearity) change amount Vertical symmetry (V symmetry) change amount Symbol Test Circuit VTH ⎯ VTCH ⎯ VTCM ⎯ VTCL ⎯ VRMP ⎯ (Note 3) 1.65 1.75 1.85 Vp-p GV ⎯ (Note 4) 21 24 27 dB V4H ⎯ V4L ⎯ VNFM ⎯ VDC (80) ⎯ VDC (83) ⎯ VDC ⎯ Test Condition (Note 1) (Note 2) 2.5 3.3 4.1 0.00 0.00 0.30 1.65 1.85 2.05 3.00 3.55 4.10 5.65 6.20 6.75 2.30 2.65 3.00 1.64 1.82 2.00 2.87 3.16 3.45 (Note 5) (Note 6) (Note 7) V VDD (00) ⎯ VDD (FE) ⎯ VDD ⎯ 1.30 1.45 1.60 VNFL ⎯ 0.85 1.00 1.15 VNFH ⎯ 2.55 2.75 2.95 VNFP ⎯ 43 48 53 VNFN ⎯ −53 −48 −43 V1 (00) ⎯ 0.90 1.06 1.22 V2 (00) ⎯ 0.69 0.81 0.93 V1 (80) ⎯ 0.82 0.96 1.10 V2 (80) ⎯ 0.77 0.91 1.05 V1 (F8) ⎯ 0.73 0.86 0.99 V2 (F8) ⎯ 0.85 1.00 1.15 VLIN ⎯ 9.5 10.5 12.5 4.60 4.95 5.20 5.40 5.70 6.00 0.67 0.76 0.85 VVT (00) ⎯ VVT (FF) ⎯ VVT ⎯ (Note 8) V Vp-p V V Vp-p (Note 9) (Note 10) (Note 11) 20 % Vp-p % V 2005-08-18 TA1317ANG Characteristics Vertical S correction (V S correction) change amount Vertical integral correction (V ∫ correction) change amount Symbol Test Circuit VS (80) ⎯ VS (BF) ⎯ VS ⎯ V ∫ (80) ⎯ V ∫ (8F) ⎯ V∫ Vertical EHT compensation (V EHT compensation) change amount EHT input dynamic range Horizontal amplitude adjustment (picture width) change amount Parabola amplitude adjustment (EW parabola) change amount EW top corner correction (EW top corner) change amount EW bottom corner correction (EW bottom corner) change amount EW corner correction change amount EW S correction change amount EW trapezium correction change amount Horizontal EHT compensation (H-EHT compensation) DC change amount Parabola amplitude EHT compensation Test Condition (Note 12) (Note 13) ⎯ VE (80) ⎯ VE (87) ⎯ VEHT ⎯ VEHL ⎯ VEHH ⎯ VEV (00) ⎯ VEV (FC) ⎯ (Note 14) Min Typ. Max 1.92 2.26 2.60 1.27 1.50 1.73 17 21 25 1.54 1.82 2.10 1.62 1.90 2.18 3.0 4.0 5.2 1.58 1.86 2.14 1.44 1.69 1.94 8.5 10.0 11.5 1.9 2.4 2.9 5.9 6.4 6.9 5.20 6.15 7.10 1.30 1.55 1.80 (Note 15) (Note 16) Unit Vp-p % Vp-p % Vp-p % V VEV ⎯ 4.20 4.60 5.00 VPB (00) ⎯ 0.00 0.02 0.06 VPB (20) ⎯ 1.6 2.0 2.3 VPB (3F) ⎯ 2.8 3.3 3.8 VPB ⎯ 2.8 3.3 3.8 VTC (00) ⎯ 2.3 2.8 3.2 VTC (F8) ⎯ 0.9 1.2 1.4 VTCP ⎯ 32 40 46 VTCN ⎯ −46 −40 −32 VBC (00) ⎯ 2.4 2.8 3.2 VBC (F8) ⎯ 0.9 1.2 1.4 VBCP ⎯ 32 45 55 VBCN ⎯ −52 −40 −35 (Note 17) V Vp-p Vp-p (Note 18) % Vp-p (Note 19) VM (00) ⎯ 2.4 2.8 3.2 VM (F8) ⎯ 0.8 1.1 1.4 VMP ⎯ 40 47 57 VMN ⎯ −52 −42 −32 VS (00) ⎯ 2.2 2.6 3.0 VS (F8) ⎯ 1.0 1.4 1.6 VSP ⎯ 28 35 40 VSN ⎯ −40 −32 −27 VET (00) ⎯ 2.4 2.7 3.0 VET (FE) ⎯ −3.0 −2.7 −2.4 VETP ⎯ 11.0 13.5 16.0 VETN ⎯ −16.0 −13.5 −11.0 VHC (80) ⎯ 3.0 3.6 4.2 VHC (87) ⎯ 4.0 4.7 5.4 % Vp-p (Note 20) % Vp-p (Note 21) (Note 22) (Note 23) VHC ⎯ 1.0 1.2 1.4 EHT (1) ⎯ 1.55 1.90 2.20 EHT (7) ⎯ 1.65 2.00 2.30 EHT ⎯ 2.7 4.0 5.3 (Note 24) 21 % ms % V Vp-p % 2005-08-18 TA1317ANG Symbol Test Circuit VX (00) VX (40) VX (80) ⎯ VX (C0) Sawtooth correction (cent saw) maximum amplitude VN (8F) VN (80) ⎯ Parabola correction (cent par) maximum amplitude VP (F8) ⎯ VP (08) ⎯ VHD (80) ⎯ Characteristics AGC operating current Horizontal DF amplitude adjustment (H DF amp) Horizontal DF phase adjustment (H DF phase) Horizontal DF bathtub (H DF curve) adjustment Vertical DF amplitude adjustment (V DF amp) Vertical DF phase adjustment (V DF phase) LVP detection voltage Vertical guard detection voltage Vertical guard detection output current (BLK-OUT output current) Vertical centering DAC output voltage 1 (V centering) Vertical centering DAC output voltage 2 (V shift) Vertical centering change amount in V STOP mode Vertical NF signal amplitude at DC coupling Vertical NF center voltage at DC coupling Test Condition Min Typ. Max ⎯ 20 35 50 ⎯ 45 65 85 250 340 430 ⎯ 535 715 895 ⎯ 4.3 5.0 5.7 4.3 5.0 5.7 (Note 25) (Note 26) 1.9 2.2 2.5 1.9 2.2 2.5 2.1 2.8 3.3 2.4 3.1 4.0 2.6 3.4 4.3 (Note 27) VHD (88) ⎯ VHD (8F) ⎯ VHDP ⎯ 7 10 13 VHDN ⎯ −15 −12 −7 −2.9 −2.1 −0.9 0.9 2.1 2.9 3.0 4.2 4.8 15 20 25 10 15 20 THD (08) ⎯ THD (F8) ⎯ THD ⎯ (Note 28) (Note 29) THB (00) ⎯ THB (F0) ⎯ THB ⎯ 1.1 2.1 3.1 VVD (80) ⎯ 2.05 2.40 2.75 VVD (88) ⎯ 2.30 2.70 3.10 VVD (8F) ⎯ 2.55 3.00 3.45 VVDP ⎯ 7 10 13 VVDN ⎯ −15 −10 −7 TVD (08) ⎯ −2.5 −2.0 −1.5 TVD (F8) ⎯ 1.5 2.0 2.5 3.4 4.0 4.6 4.7 5.0 5.3 7.0 7.3 7.6 2.1 2.4 2.7 450 630 750 0.20 0.50 0.55 4.7 5.0 5.3 0.20 0.60 0.80 4.7 5.0 5.3 1.7 1.9 2.1 2.25 2.50 2.75 2.7 3.0 3.3 (Note 30) (Note 31) (Note 32) Unit µA Vp-p Vp-p Vp-p % µs µs Vp-p % ms TVD ⎯ VLVP ⎯ VVGH ⎯ VVGL ⎯ I20 ⎯ VCA (00) ⎯ VCA (FE) ⎯ VCD (80) ⎯ VCD (83) ⎯ VY (00) ⎯ VY (80) ⎯ VY (FE) ⎯ VDFB ⎯ (Note 39) 0.85 0.95 1.05 Vp-p VC ⎯ (Note 40) 2.25 2.50 2.75 V (Note 33) (Note 34) (Note 35) V (Note 36) 22 µA V (Note 37) (Note 38) V V V 2005-08-18 TA1317ANG Characteristics Vertical ramp cut level Symbol Test Circuit VCHH ⎯ VCLH ⎯ BLHL Min Typ. Max 20.0 26.0 32.0 26.0 32.1 38.0 ⎯ 5.05 5.90 6.75 BLHM ⎯ 2.30 2.70 3.10 BLHH ⎯ ⎯ 0.00 0.10 5.10 6.00 6.90 Analog blanking phase Parabola amplitude adjustment (EW parabola) change amount at PWM Test Condition (Note 41) (Note 42) ⎯ BLLM ⎯ 2.05 2.40 3.00 BLLH ⎯ ⎯ 0.00 0.10 VPP (00) ⎯ 0.00 0.02 0.06 VPP (20) ⎯ ⎯ VPP ⎯ 1.6 2.00 2.30 2.80 3.30 3.80 2.80 3.30 3.80 (Note 43) 23 % ms BLLL VPP (3F) Unit Vp-p 2005-08-18 TA1317ANG Test Condition Test Condition Note No. 1 Parameter Vertical trigger input shaped voltage Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 OFF B ON OFF B ON A A (1) Input vertical trigger pulse (figure below) to pin VIN. (2) Increase vertical trigger pulse level (VT) from 0 VP-P. When timing pulse is output to pin 22 (TC FILTER), measure vertical trigger pulse level VTH. Vertical cycle = 20 ms Vertical trigger pulse Pulse level (VT) 0V 640 µs 2 Timing pulse output voltage OFF B ON OFF B ON A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Measure pin 22 (TC FILTER) voltages (VTCH, VTCM, VTCL) as shown in the figure below. VTCH Pin 22 (TC FILTER) waveform VTCM VTCL Pin 23 (V-RAMP FILTER) waveform 24 2005-08-18 TA1317ANG Test Condition Note No. 3 Parameter Vertical ramp wave amplitude Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 OFF B ON OFF B ON A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Measure pin 23 (V-RAMP FILTER) amplitude VRMP as shown in the figure below. Pin 23 (V-RAMP FILTER) waveform Vertical drive amplification OFF C ON OFF B ON A A (1) No signal input to pin VIN. (2) Set VD (V-DRIVE mode switch) (sub-address: 00) to AC-Coupling mode (data: 81). (3) Connect external power supply (V6) to TP6 (V fb). (4) Change external power supply (V6) until pin 4 (V DRIVE) voltage is 0.8 V. The voltage is made V6A. (5) Measure pin 4 voltage (V4A) when the external power supply voltage is V6A + 0.2 V. (6) Calculate the drive amplification (GV) using the following formula. Pin 4 (V DRIVE) voltage (V4) 4 VRMP V4H V4A 0.8 V V4L V6A V6A + 0.2 V Pin 6 (V NF) external supply voltage (V6) GV = 20 log 25 V4A − 0.8 0.2 2005-08-18 TA1317ANG Test Condition Note No. 5 Parameter Vertical drive output voltage Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 OFF C ON OFF B ON A A (1) Measure V4H using the figure for Note 4. (2) Measure V4L using the figure for Note 4. 6 Vertical NF signal amplitude OFF C ON OFF B ON A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Set VD (sub-address: 00) to AC-Coupling mode (data: 81). (3) Set V INTEGRAL CORRECTION (sub-address: 08) to center (data: 88). (4) Set V S CORRECTION (sub-address: 09) to center (data: A0). (5) Set V SHIFT (sub-address: 01) data to 82. (6) Measure Pin 6 (V NF) vertical sawtooth amplitude VNFM. Pin 6 (V NF) waveform 26 VNFM 2005-08-18 TA1317ANG Test Condition Note No. 7 Parameter Vertical phase adjustment 1 (V shift) change amount Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 OFF B ON OFF B ON A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Set VD (sub-address: 00) to AC-Coupling mode (data: 81). (3) Set V INTEGRAL CORRECTION (sub-address: 08) to center (data: 88). (4) Set V S CORRECTION (sub-address: 09) to center (data: A0). (5) Set V SHIFT (sub-address: 01) to minimum (data: 80) and measure VDC (80) as shown in the figure below. (6) Set V SHIFT (sub-address: 01) to maximum (data: 83) and measure VDC (83) as shown in the figure below. (7) Calculate change amount VDC using the following formula. Pin 6 (V NF) waveform VDC (83) VDC (80) 10 ms 10 ms VDC = VDC (83) − VDC (80) 27 2005-08-18 TA1317ANG Test Condition Note No. 8 Parameter Vertical phase adjustment 2 (V centering) change amount Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 ON A OFF OFF B ON A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Set VD (sub-address: 00) to DC-Coupling mode (data: 80). (3) Set V INTEGRAL CORRECTION (sub-address: 08) to center (data: 88). (4) Set V S CORRECTION (sub-address: 09) to center (data: A0). (5) Set V CENTERING (sub-address: 05) to minimum (data: 00) and measure VDD (00) as shown in the figure below. (6) Set V CENTERING (sub-address: 05) to maximum (data: FE) and measure VDD (FE) as shown in the figure below. (7) Calculate change amount VDD using the following formula. Pin 6 (V NF) waveform VDD (FE) VDD (00) 10 ms 10 ms VDD = VDD (FE) − VDD (00) 28 2005-08-18 TA1317ANG Test Condition Vertical amplitude adjustment (picture height) change amount Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 OFF B ON OFF B ON A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Set VD (sub-address: 00) to AC-Coupling mode (data: 81). (3) Set V INTEGRAL CORRECTION (sub-address: 08) to center (data: 88). (4) Set V S CORRECTION (sub-address: 09) to center (data: A0). (5) Set V SHIFT (sub-address: 01) data to 82. (6) Set PICTURE HEIGHT (sub-address: 00) to minimum (data: 01) and measure Pin 6 (V NF) amplitude (VNFL). (7) Set PICTURE HEIGHT (sub-address: 00) to maximum (data: FF) and measure Pin 6 (V NF) amplitude (VNFH). (8) Determine variable ranges (VNFP, VNFN) using the following formulas. Pin 6 (V NF) waveform VNFP = 29 VNFL 9 Parameter VNFH Note No. VNFH − VNFM VNFM × 100, VNFN = VNFL − VNFM × 100 VNFM 2005-08-18 TA1317ANG Test Condition 10 Parameter Vertical linearity correction (V linearity) change amount Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 OFF B ON OFF B ON A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Set VD (sub-address: 00) to AC-Coupling mode (data: 81). (3) Set V INTEGRAL CORRECTION (sub-address: 08) to center (data: 88). (4) Set V S CORRECTION (sub-address: 09) to center (data: A0). (5) Set V SHIFT (sub-address: 01) data to 82. (6) Set V LINEARITY (sub-address: 02) to minimum (data: 00) and measure V1 (00) and V2 (00) as shown in the figure below. (7) Set V LINEARITY (sub-address: 02) to center (data: 80) and measure V1 (80) and V2 (80) as shown in the figure below. (8) Set V LINEARITY (sub-address: 02) to maximum (data: F8) and measure V1 (F8) and V2 (F8) as shown in the figure below. (9) Calculate maximum correction VLIN from measured result using the following formula. Pin 6 (V NF) waveform V2 (**) V1 (**) Note No. 10 ms VLIN = 30 V1 (00) − V1 (F8) + V2 (F8) − V2 (00) 2 × [V1 (80) + V2 (80)] 10 ms × 100 2005-08-18 TA1317ANG Test Condition Note No. 11 Parameter Vertical symmetry (V symmetry) change amount Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 OFF B ON OFF B ON A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Set VD (sub-address: 00) to AC-Coupling mode (data: 81). (3) Set V INTEGRAL CORRECTION (sub-address: 08) to center (data: 88). (4) Set V S CORRECTION (sub-address: 09) to center (data: A0). (5) Set V SHIFT (sub-address: 01) data to 82. (6) Set V SYMMETRY (sub-address: 11) to minimum (data: 00) and measure Pin 6 (V NF) voltage VVT (00). (7) Set V SYMMETRY (sub-address: 11) to maximum (data: FF) and measure Pin 6 (V NF) voltage VVT (FF). (8) Calculate change amount VVT using the following formula. Pin 6 (V NF) waveform VVT (FF) VVT (00) 10 ms 10 ms VVT = VVT (FF) − VVT (00) 31 2005-08-18 TA1317ANG Test Condition Vertical S correction (V S correction) change amount Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 OFF B ON OFF B ON A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Set VD (sub-address: 00) to AC-Coupling mode (data: 81). (3) Set V INTEGRAL CORRECTION (sub-address: 08) to center (data: 88). (4) Set V SHIFT (sub-address: 01) to 82. (5) Set V S CORRECTION (sub-address: 09) to minimum (data: 80) and measure VS (80) as shown in the figure below. (6) Set V S CORRECTION (sub-address: 09) to maximum (data: BF) and measure VS (BF) as shown in the figure below. (7) Calculate maximum correction VS using measured result and the following formula. Pin 6 (V NF) waveform VS = 32 VS (BF) 12 Parameter VS (80) Note No. VS (80) − VS (8F) VS (80) + VS (8F) × 100 2005-08-18 TA1317ANG Test Condition Note No. 13 Parameter Vertical integral correction (V ∫ correction) change amount Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 OFF B ON OFF B ON A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Set VD (sub-address: 00) to AC-Coupling mode (data: 81). (3) Set V S CORRECTION (sub-address: 09) to center (data: A0). (4) Set V SHIFT (sub-address: 01) to 82. (5) Set V INTEGRAL CORRECTION (sub-address: 08) to minimum (data: 80) and measure V ∫ (80) as shown in the figure below. (6) Set V INTEGRAL CORRECTION (sub-address: 08) to maximum (data: 8F) and measure V ∫ (8F) as shown in the figure below. (7) Calculate maximum correction V ∫ from measured result using the following formula. Pin 6 (V NF) waveform V∫ (8F) V∫ = 33 V∫ (80) V ∫ (8F) − V ∫ (80) × 100 V ∫ (80) 2005-08-18 TA1317ANG Test Condition Note No. 14 Parameter Vertical EHT compensation (V EHT compensation) change amount Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 OFF B ON OFF B ON A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Set VD (sub-address: 00) to AC-Coupling mode (data: 81). (3) Set V SHIFT (sub-address: 01) data to 82. (4) Connect external power supply (DC voltage = 0 V) to pin 3 (EHT IN). (5) Set V-EHT COMPENSATION (sub-address: 02) to minimum (data: 80) and measure Pin 6 (V NF) amplitude VE (80). (6) Set V-EHT COMPENSATION (sub-address: 02) to maximum (data: 87) and measure Pin 6 (V NF) amplitude VE (87). (7) Calculate change amount VEHT using the following formula. VEHT = 34 VE (80) − VE (87) × 100 VE (87) 2005-08-18 TA1317ANG Test Condition Note No. 15 Parameter EHT input dynamic range Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 OFF B ON OFF B ON A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Set VD (sub-address: 00) to AC-Coupling mode (data: 81). (3) Set V SHIFT (sub-address: 01) data to 82. (4) Connect external power supply V3 to pin 3 (EHT IN). (5) Set V-EHT COMPENSATION (sub-address: 02) to maximum (data: 87). (6) Change external power supply V3 from 1 to 7 V and monitor Pin 6 (V NF) amplitude. Pin 6 (V NF) amplitude (7) When Pin 6 (V NF) amplitude changes, measure V3 voltages VEHL and VEHH. VEHL 16 Horizontal amplitude adjustment (picture width) change amount OFF B ON OFF B ON A A VEHH Voltage applied to pin 3 (EHT IN) (V3) (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Set EW PARABOLA (sub-address: 0A) to minimum (data: 00). (3) Set PICTURE WIDTH to maximum ( (sub-address: 01, data: FC) and (sub-address: 0C, data: 81) ) and measure Pin 10 (EW FD) voltage VEV (FC). (4) Set PICTURE WIDTH to minimum ( (sub-address: 01, data: 00) and (sub-address: 0C, data: 80) ) and measure Pin 10 (EW FD) voltage VEV (00). (5) Calculate change amount VEV using the following formula. VEV = VEV (FC) − VEV (00) 35 2005-08-18 TA1317ANG Test Condition Parabola amplitude adjustment (EW parabola) change amount Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 OFF B ON OFF B ON A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Set PICTURE WIDTH (sub-address: 01) to maximum (data: FC). (3) Apply external power supply (DC voltage = 7 V) to pin 3 (EHT IN). (4) Set EW PARABOLA (sub-address: 0A) to minimum (data: 00) and measure Pin 10 (EW FD) amplitude VPB (00). (5) Set EW PARABOLA (sub-address: 0A) to center (data: 20) and measure Pin 10 (EW FD) amplitude VPB (20). (6) Set EW PARABOLA (sub-address: 0A) to maximum (data: 3F) and measure Pin 10 (EW FD) amplitude VPB (3F). (7) Calculate change amount VPB using the following formula. VPB (3F) 17 Parameter VPB (00) Note No. Pin 10 (EW FD) waveform VPB = VPB (3F) − VPB (00) 36 2005-08-18 TA1317ANG Test Condition EW top corner correction (EW top corner) change amount Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 OFF B ON OFF B ON A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Apply external power supply (DC voltage = 7 V) to pin 3 (EHT IN). (3) Set EW PARABOLA (sub-address: 0A) to center (data: 20). (4) Set EW TOP CORNER (sub-address: 0C) to minimum (data: 00) and measure Pin 10 (EW FD) amplitude VTC (00). (5) Set EW TOP CORNER (sub-address: 0C) to maximum (data: F8) and measure Pin 10 (EW FD) amplitude VTC (F8). (6) Calculate change amounts VTCP and VTCN using the following formulas. VTC (00) 18 Parameter VTC(00) VTC (F8) Note No. VTC(F8) Pin 10 (EW FD) waveform VTCP = VTCN = 37 VTC (00) − VPB (20) × 100 VPB (20) VTC (F8) − VPB (20) × 100 VPB (20) 2005-08-18 TA1317ANG Test Condition EW bottom corner correction (EW bottom corner) change amount Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 OFF B ON OFF B ON A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Apply external power supply (DC voltage = 7 V) to pin 3 (EHT IN). (3) Set EW PARABOLA (sub-address: 0A) to center (data: 20). (4) Set EW BTM CORNER (sub-address: 0D) to minimum (data: 00) and measure Pin 10 (EW FD) amplitude VBC (00). (5) Set EW BTM CORNER (sub-address: 0D) to maximum (data: F8) and measure Pin 10 (EW FD) amplitude VBC (F8). (6) Calculate change amounts VBCP and VBCN using the following formulas. VBC (00) 19 Parameter VTC(00) VBC (F8) Note No. VTC(F8) Pin 10 (EW FD) waveform VBCP = VBCN = 38 VBC (00) − VPB (20) × 100 VPB (20) VBC (F8) − VPB (20) × 100 VPB (20) 2005-08-18 TA1317ANG Test Condition EW corner correction change amount Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 OFF B ON OFF B ON A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Apply external power supply (DC voltage = 7 V) to pin 3 (EHT IN). (3) Set EW PARABOLA (sub-address: 0A) to center (data: 20). (4) Set EW CORNER (sub-address: 0F) to minimum (data: 00) and measure Pin 10 (EW FD) amplitude VM (00). (5) Set EW CORNER (sub-address: 0F) to maximum (data: F8) and measure Pin 10 (EW FD) amplitude VM (F8). (6) Calculate change amounts VMP and VMN using the following formulas. VM (00) 20 Parameter VM (F8) Note No. Pin 10 (EW FD) waveform VMP = VMN = 39 VM (00) − VPB (20) × 100 VPB (20) VM (F8) − VPB (20) × 100 VPB (20) 2005-08-18 TA1317ANG Test Condition EW S correction change amount Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 OFF B ON OFF B ON A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Apply external power supply (DC voltage = 7 V) to pin 3 (EHT IN). (3) Set EW PARABOLA (sub-address: 0A) to center (data: 20). (4) Set S CORRECTION (sub-address: 0E) to minimum (data: 00) and measure Pin 10 (EW FD) amplitude VS (00). (5) Set S CORRECTION (sub-address: 0E) to maximum (data: F8) and measure Pin 10 (EW FD) amplitude VS (F8). (6) Calculate change amounts VSP and VSN using the following formulas. VS (00) 21 Parameter VS (F8) Note No. Pin 10 (EW FD) waveform VSP = VSN = 40 VS (00) − VPB (20) × 100 VPB (20) VS (F8) − VPB (20) × 100 VPB (20) 2005-08-18 TA1317ANG Test Condition Note No. 22 Parameter EW trapezium correction change amount Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 OFF B ON OFF B ON A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Apply external power supply (DC voltage = 7 V) to pin 3 (EHT IN). (3) Set EW PARABOLA (sub-address: 0A) to maximum (data: 3F). (4) Set EW TRAPEZIUM (sub-address: 0B) to minimum (data: 00) and measure Pin 10 (EW FD) phase VET (00). (5) Set EW TRAPEZIUM (sub-address: 0B) to maximum (data: FE) and measure Pin 10 (EW FD) phase VET (FE). (6) Calculate change amounts VETP and VETN using the following formulas. VET (FE) VET (00) Pin 10 (EW FD) waveform VETP = VETN = 41 VET (FE) × 100 20 VET (00) × 100 20 2005-08-18 TA1317ANG Test Condition Note No. 23 Parameter Horizontal EHT compensation (H-EHT compensation) DC change amount Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 OFF B ON OFF B ON A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Apply external power supply (DC voltage = 1 V) to pin 3 (EHT IN). (3) Set H-EHT COMPENSATION (sub-address: 03) to minimum (data: 80) and measure Pin 10 (EW FD) amplitude VHC (80). (4) Set H-EHT COMPENSATION (sub-address: 03) to maximum (data: 87) and measure Pin 10 (EW FD) amplitude VHC (87). (5) Calculate change amount VHC using the following formula. VHC (87) VHC (80) Pin 10 (EW FD) waveform VHC = VHC (87) − VHC (80) 42 2005-08-18 TA1317ANG Test Condition Note No. 24 Parameter Parabola amplitude EHT compensation Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 OFF B ON OFF B ON A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Apply external power supply V3 to pin 3 (EHT IN). (3) Set EW PARABOLA (sub-address: 0A) to center (data: 20). (4) Set external power supply V3 to 7 V and measure Pin 10 (EW FD) amplitude EHT (7). (5) Set external power supply V3 to 1 V and measure Pin 10 (EW FD) amplitude EHT (1). (6) Calculate change amount EHT using the following formula. EHT = EHT (7) − EHT (1) × 100 EHT (7) 25 AGC operating current OFF B ON OFF B ON A B (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) When V AGC (sub-address: 09) is switched, set data to 00, 40, 80, and C0 and measure the following. (3) Connect GND through 200 Ω to pin 24 (AGC FILTER). (4) Monitor pin 24 (AGC FILTER) and measure pulse levels VX (00), VX (40), VX (80), and VX (C0) as shown in the figure below. (5) Calculate output currents (IX (00), IX (40), IX (80), IX (C0) using the following formula. VX Pin 24 (AGC FILTER) waveform IX (**) = 43 VX (**) 200 Ω 2005-08-18 TA1317ANG Test Condition Note No. 26 Parameter Sawtooth correction (cent saw) maximum amplitude Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 OFF B ON OFF B ON A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Set CENTER SAW (sub-address: 10) to maximum (data: 8F) and measure pin 19 (CENT OUT) amplitude VN (8F). (3) Set CENTER SAW (sub-address: 10) to minimum (data: 80) and measure pin 19 (CENT OUT) amplitude VN (80). VN (8F) VN (80) Pin 19 (CENT OUT) waveform Pin 19 (CENT OUT) waveform 27 Parabola correction (cent par) maximum amplitude OFF B ON OFF B ON A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Set CENTER PARABOLA (sub-address: 10) to maximum (data: F8) and measure pin 19 (CENT OUT) amplitude VP (F8). (3) Set CENTER PARABOLA (sub-address: 10) to minimum (data: 08) and measure pin 19 (CENT OUT) amplitude VP (08). VP (08) Pin 19 (CENT OUT) waveform 44 VP (F8) Pin 19 (CENT OUT) waveform 2005-08-18 TA1317ANG Test Condition Horizontal DF amplitude adjustment (H DF amp) Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 OFF B ON OFF B ON A A (1) Input horizontal trigger pulse (figure below) to pin 12 (FBP IN). Pulse level (HT) = 4.0 V 3 µs Pulse level (HT) H cycle = 30 µs (2) Set H-DF CURVE (sub-address: 08) to maximum (data: F0). (3) Set H-DF AMPLITUDE (sub-address: 07) to minimum (data: 80) and measure pin 16 (H-DF OUT) amplitude VHD (80). (4) Set H-DF AMPLITUDE (sub-address: 07) to center (data: 88) and measure pin 16 (H-DF OUT) amplitude VHD (88). (5) Set H-DF AMPLITUDE (sub-address: 07) to maximum (data: 8F) and measure pin 16 (H-DF OUT) amplitude VHD (8F). (6) Calculate change amounts VHDP and VHDN using the following formulas. VHD (8F) 28 Parameter VHD (80) Note No. Pin 16 (H-DF OUT) waveform VHDP = VHDN = 45 VHD (8F) − VHD (88) × 100 VHD (88) VHD (80) − VHD (88) × 100 VHD (88) 2005-08-18 TA1317ANG Test Condition Note No. 29 Parameter Horizontal DF phase adjustment (H DF phase) Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 OFF B ON OFF B ON A A (1) Input horizontal trigger pulse (figure below) to pin 12 (FBP IN). Pulse level (HT) = 4.0 V (2) Set H-DF CURVE (sub-address: 08) to maximum (data: F0). (3) Set H-DF PHASE (sub-address: 07) to minimum (data: 08) and measure pin 16 (H-DF OUT) phase THD (08). (4) Set H-DF PHASE (sub-address: 07) to maximum (data: F8) and measure pin 16 (H-DF OUT) phase THD (F8). (5) Calculate change amount THD using the following formula. THD (08) THD (F8) Pin 16 (H-DF OUT)waveform THD = THD (08) + THD (F8) 46 2005-08-18 TA1317ANG Test Condition Note No. 30 Parameter Horizontal DF bathtub (H DF curve) adjustment Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 OFF B ON OFF B ON A A (1) Input horizontal trigger pulse (figure below) to pin 12 (FBP IN). Pulse level (HT) = 4.0 V (2) Set H-DF AMPLITUDE (sub-address: 07) to maximum (data: 8F). (3) Set H-DF CURVE (sub-address: 08) to minimum (data: 00) and measure pin 16 (H-DF OUT) phase THB (00). (4) Set H-DF CURVE (sub-address: 08) to maximum (data: F0) and measure pin 16 (H-DF OUT) phase THB (F0). (5) Calculate change amount THB using the following formula. 1V THB (F0) THB (00) Pin 16 (H-DF OUT) waveform THB = 47 THB (00) − THB (F0) 2 2005-08-18 TA1317ANG Test Condition Vertical DF amplitude adjustment (V DF amp) Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 OFF B ON OFF B ON A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Set V-DF AMPLITUDE (sub-address: 06) to minimum (data: 80) and measure pin 18 (V-DF OUT) amplitude VVD (80). (3) Set V-DF AMPLITUDE (sub-address: 06) to center (data: 88) and measure pin 18 (V-DF OUT) amplitude VVD (88). (4) Set V-DF AMPLITUDE (sub-address: 06) to maximum (data: 8F) and measure pin 18 (V-DF OUT) amplitude VVD (8F). (5) Calculate change amounts VVDP and VVDN using the following formulas. VVD (80) 31 Parameter VVD (8F) Note No. Pin 18 (V-DF OUT) waveform VVDP = VVDN = 48 VVD (80) − VVD (88) × 100 VVD (88) VVD (8F) − VVD (88) × 100 VVD (88) 2005-08-18 TA1317ANG Test Condition Note No. 32 Parameter Vertical DF phase adjustment (V DF phase) Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 OFF B ON OFF B ON A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Set V-DF PHASE (sub-address: 06) to minimum (data: 08) and measure pin 18 (V-DF OUT) phase TVD (08). (3) Set V-DF PHASE (sub-address: 06) to maximum (data: F8) and measure pin 18 (V-DF OUT) phase TVD (F8). (4) Calculate change amount TVD using the following formula. TVD (08) TVD (F8) Pin 18 (V-DF OUT) waveform TVD = TVD (08) + TVD (F8) 33 LVP detection voltage OFF B ON OFF B ON B A (1) Connect external supply voltage V7 to TP17 (LVP). (2) Decrease external supply voltage V7 from 9 V. When D5 data in Read mode changes from 0 to 1, measure TP17 voltage VLVP. 34 Vertical guard detection voltage OFF C ON OFF B ON A A (1) Connect external supply voltage V6 to TP6 (V NF). (2) Switch to VD (sub-address: 00) to AC-Coupling mode (data: 81). (3) Increase external supply voltage V6 from 5.5 V. When D3 data in Read mode changes from 0 to 1, measure TP6 voltage VVGH. (4) Decrease external supply voltage V6 from 5.5 V. When D3 data in Read mode changes from 0 to 1, measure TP6 voltage VVGL. 49 2005-08-18 TA1317ANG Test Condition Note No. 35 Parameter Vertical guard detection output current (BLK-OUT output current) Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 OFF C ON OFF B ON A A (1) Connect external supply voltage V6 = 8 V to TP6 (V NF). (2) Measure pin 20 (BLK OUT) voltage V20 and calculate output current (I20) using the following formula. I20 = 36 Vertical centering DAC output voltage 1 (V centering) OFF B ON OFF B ON A A V20 10 kΩ (1) Set VD (sub-address: 00) to AC-Coupling mode (data: 81). (2) Set V CENTERING (sub-address: 05) to minimum (data: 00) and measure pin 2 (CENTER DAC) voltage VCA (00). (3) Set V CENTERING (sub-address: 05) to maximum (data: FE) and measure pin 2 (CENTER DAC) voltage VCA (FE). 37 Vertical centering DAC output voltage 2 (V shift) OFF A OFF OFF B ON A A (1) Set VD (sub-address: 00) to DC-Coupling mode (data: 80). (2) Set V SHIFT (sub-address: 01) to minimum (data: 80) and measure pin 2 (CENTER DAC) voltage VCD (80). (3) Set V SHIFT (sub-address: 01) to maximum (data: 83) and measure pin 2 (CENTER DAC) voltage VCD (83). 38 Vertical centering change amount in V STOP mode ON A OFF OFF B ON A A (1) Set VD (sub-address: 00) to DC-Coupling mode (data: 80). (2) Set to V STOP (sub-address: 0B, data: 81). (3) Set V CENTERING (sub-address: 05) to minimum (data: 00) and measure Pin 6 (V NF) voltage VY (00). (4) Set V CENTERING (sub-address: 05) to center (data: 80) and measure Pin 6 (V NF) voltage VY (80). (5) Set V CENTERING (sub-address: 05) to minimum (data: FE) and measure Pin 6 (V NF) voltage VY (FE). 50 2005-08-18 TA1317ANG Test Condition Note No. 39 Parameter Vertical NF signal amplitude at DC coupling Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 ON A OFF OFF B ON A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Set VD (sub-address: 00) to DC-Coupling mode (data: 80). (3) Measure vertical Pin 6 (V NF) sawtooth width VDFB. Pin 6 (V NF) waveform 40 Vertical NF center voltage at DC coupling ON A OFF OFF B ON A A VDFB (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Set VD (sub-address: 00) to DC-Coupling mode (data: 80). (3) Measure center voltage VC as shown in the figure below. Pin 6 V (V NF) waveform C 10 ms 51 10 ms 2005-08-18 TA1317ANG Test Condition SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 ON A OFF OFF B ON A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Set VD (sub-address: 00) to DC-Coupling mode (data: 80). (3) Set V INTEGRAL CORRECTION (sub-address: 08) to center (data: 8F). (4) Set V S CORRECTION (sub-address: 09) to center (data: A0). VT (5) Measure amplitudes VT and VB as shown in the figure below. Pin 6 (V NF) waveform VB Vertical ramp cut level Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode 10 ms 10 ms (6) Set V-RAMP to maximum and measure amplitudes VTH and VBH. Sub-address 04 data: 87 VTH 41 Parameter Pin 6 (V NF) waveform VBL VBH Note No. 10 ms 10 ms Sub-address 05 data: 81 (7) Calculate cut levels using the following formulas. VCHH = VCLH = 52 VT − VTH × 100, VT VB − VBH × 100, VB 2005-08-18 TA1317ANG Test Condition Note No. 42 Parameter Analog blanking phase Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 ON A OFF OFF B ON A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V, 60Hz (2) Set VD (sub-address: 00) to DC-Coupling mode (data: 80). (3) Set V INTEGRAL CORRECTION (sub-address: 08) to center (data: 8F). (4) Set V S CORRECTION (sub-address: 09) to center (data: A0). (5) AS shown in the figure below, measure analog blanking phase in relation to pin 21 (VIN) under the following conditions. (6) Set ANALOG V-BLK STOP PHASE (sub-address: 03) to minimum (data: 00) and measure blanking phase BLHL. (7) Set ANALOG V-BLK STOP PHASE (sub-address: 03) to center (data: 80) and measure blanking phase BLHM. (8) Set ANALOG V-BLK STOP PHASE (sub-address: 03) to maximum (data: F8) and measure blanking phase BLHH. (9) Set ANALOG V-BLK START PHASE (sub-address: 04) to minimum (data: 00) and measure blanking phase BLLL. (10) Set ANALOG V-BLK START PHASE (sub-address: 04) to center (data: 80) and measure blanking phase BLLM. (11) Set ANALOG V-BLK START PHASE (sub-address: 04) to maximum (data: F8) and measure blanking phase BLLH. Vertical trigger pulse Pin 20 (BLK OUT) BLLL BLHL BLLM BLHM BLLH BLHH 53 2005-08-18 TA1317ANG Test Condition Parabola amplitude adjustment (EW parabola) change amount at PWM Test Method (unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values) SW Mode SW5 SW6 SW7 SW8 SW10 SW11 SW17 SW24 OFF B ON ON A OFF A A (1) Input vertical trigger pulse to pin VIN. Pulse level (VT) = 3.0 V (2) Set PICTURE WIDTH (sub-address: 01) to maximum (data: 8C). (3) Apply external power supply (DC voltage = 7 V) to pin 3 (EHT IN). (4) Set EW PARABOLA (sub-address: 0A) to minimum (data: 00) and measure Pin 10 (EW FD) amplitude VPP (00). (5) Set EW PARABOLA (sub-address: 0A) to center (data: 20) and measure Pin 10 (EW FD) amplitude VPP (20). (6) Set EW PARABOLA (sub-address: 0A) to maximum (data: 3F) and measure Pin 10 (EW FD) amplitude VPP (3F). (7) Calculate change amount VPP using the following formula. VPP (3F) 43 Parameter VPP (00) Note No. Pin 10 (EW FD) waveform VPP = VPP (3F) − VPP (00) 54 2005-08-18 SW7 TP6 SW11 1200 pF 55 16 15 1 2 1000 pF 14 3 13 12 4 5 51 kΩ A 10 µF RTC18 SW6 51 kΩ CTC9 12 ＃12 RTC17 11 ＃11 50 kΩ 7.5 kΩ SDA FBP IN DIGITAL GND H-DF OUT 10 ＃10 RTC16 RTC15 SW8 SCL 9 EW FILTER TA1317ANG EW FD ＃9 RTC13 8 14 RTC14 5.1 kΩ 50 kΩ ＃8 15 C11 7 16 ＃14 0.1 µF ＃7 ANALOG GND 17 ＃15 M ○ C LVP IN 18 SW17 B ＃16 Q10 6 A ＃17 470 Ω R13a R14a 470 Ω R17 47 kΩ SCL 1 kΩ R10 ＃6 EW PWM 19 C7A V-DF OUT TP17 C8 AB VCC R20 10 kΩ C22 20 kΩ R22 Vin 1 µF SW5 ＃18 C7B 5 ＃5 220 µF CENTER OUT 20 0.01 µF V NF ＃19 R6a 4 BLK OUT ＃20 1 kΩ ＃4 V-DC REF M ○ C24 200 Ω R24 1 µF C23 0.02 µF ○ M M ○ 1 µF VCC 2.4 kΩ R8f Q6 3 R5a 21 10 kΩ VIN 22 R5b ＃3 ＃21 3.6 kΩ 2 V DRIVE 23 1 kΩ R4 ＃2 ＃22 C4 1 TC FILTER 24 EHT IN SW24 B ＃23 0. 1 µF M ○ ＃1 V-RAMP FILTER AGC FILTER A ＃24 CENTER DAC VREF 470 Ω TA1317ANG Test Circuit VCC LED SDA ＃13 13 M Mylar capacitor ○ Hin SW12 SW10 B CTC8 TC4538BP 11 10 9 CTC7 6 7 8 Pin 2005-08-18 390 kΩ F.B.T. 2.2 MΩ 330 kΩ 7.5 kΩ M 0.047 µF ○ +B TA8427K EW PWM ANALOG GND EW FD CENTER OUT 13 DIGITAL GND BLK OUT 14 H-DF OUT VIN 15 LVP IN TC FILTER 16 V-DF OUT V-RAMP FILTER 17 TA1317ANG 1 2 3 4 5 6 7 8 9 10 33 kΩ +9 V 56 SDA VCC AGC FILTER 18 FBP IN V NF 19 SCL V-DC REF 20 EW FILTER V DRIVE 21 1.2 kΩ EHT IN 22 M 0.01 µF ○ CENTER DAC 23 220 µF VREF 24 0.1 µF M ○ 270 kΩ 130 kΩ 0.01 µF M ○ 1 µF 10 kΩ 20 kΩ 0.02 µF ○ M M ○ 1 µF TA1317ANG Application Circuit 1 (V-AC coupling/EW parabola output) +200 V 400 kΩ 18 kΩ 11 12 M Mylar capacitor ○ +27 V 27 kΩ −27 V H-OUT +21 V 2005-08-18 DY 390 kΩ F.B.T. 2.2 MΩ 330 kΩ 270 kΩ 1 kΩ +B H ramp (Internal signal) 10 kΩ 0.056 µF 1200 pF SCL SDA FBP IN 1 2 3 4 5 6 7 8 9 10 11 12 16 DIGITAL GND H-DF OUT LVP IN V-DF OUT EW FILTER CENTER OUT 17 15 +9 V 57 10 kΩ BLK OUT 18 3900 pF VIN EW FD TC FILTER ANALOG GND V-RAMP FILTER EW PWM AGC FILTER VCC TA1317ANG V NF 19 V-DC REF 20 V DRIVE 21 EHT IN 22 CENTER DAC 23 VREF 24 0.01 µF 220 µF 10 kΩ M 0.047 µF ○ 130 kΩ 0.01 µF M ○ 1 µF 10 kΩ 20 kΩ 0.02 µF ○ M M ○ 1 µF TA1317ANG Application Circuit 2 (V-DC coupling/EW PWM output) +200 V 400 kΩ 18 kΩ 14 13 M Mylar capacitor ○ +25 V G D TA8427K S +21 V H-OUT −B FBP (Pin 12) EW parabola (Pin 11) EW PWM (Pin 8) H ramp 2005-08-18 TA1317ANG Package Dimensions Weight: 1.22 g (typ.) 58 2005-08-18 TA1317ANG 59 2005-08-18