SPANSION MB84VD23180FM

TM
SPANSION MCP
Data Sheet
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION
revisions will occur when appropriate, and changes will be noted in a revision summary.
TM
product. Future routine
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION
solutions.
TM
memory
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50309-1E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
64M (×16) FLASH MEMORY &
4M (×16) STATIC RAM
MB84VD23180FM-70
■ FEATURES
• Power supply voltage of 2.7 V to 3.1 V
• High performance
70 ns maximum access time (Flash)
70 ns maximum access time (SRAM)
• Operating Temperature
–30 °C to +85 °C
• Package 73-ball FBGA
(Continued)
■ PRODUCT LINEUP
Flash Memory
Supply Voltage (V)
VCCr* = 3.0 V
+0.1V
–0.3 V
SRAM
VCCs* = 3.0 V
Max Address Access Time (ns)
70
70
Max CE Access Time (ns)
70
70
Max OE Access Time (ns)
30
35
*: Both VCCf and VCCs must be in recommended operation range when either part is being accessed.
■ PACKAGE
73-ball plastic FBGA
BGA-73P-M03
+0.1V
–0.3 V
MB84VD23180FM-70
(Continued)
 FLASH MEMORY
• Simultaneous Read/Write operations (Dual Bank)
• FlexBankTM*1
Bank A : 8 Mbit (8 KB × 8 and 64 KB × 15)
Bank B : 24 Mbit (64 KB × 48)
Bank C : 24 Mbit (64 KB × 48)
Bank D : 8 Mbit (8 KB × 8 and 64 KB × 15)
Two virtual Banks are chosen from the combination of four physical banks (Refer to “Example of Virtual Banks
Combination table” and “Simultaneous Operation table”) .
Host system can program or erase in one bank, and then read immediately and simultaneously from the other
bank with zero latency between read and write operations.
Read-while-erase
Read-while-program
• Single 3.0 V read, program, and erase
Minimized system level power requirements
• Minimum 100,000 program/erase cycles
• Sector erase architecture
Sixteen 4 Kword and one hundred twenty-six 32 Kword sectors in word.
Any combination of sectors can be concurrently erased. It also supports full chip erase.
• HiddenROM region
256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC input pin
At VIL, allows protection of “outermost” 2 × 8 Kbytes on both ends of boot sectors, regardless of sector protection/
unprotection status
At VIH, allows removal of boot sector protection
At VACC, increases program performance
• Embedded EraseTM*2 Algorithms
Automatically preprograms and erases the chip or any sector
• Embedded ProgramTM* Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, the device automatically switches itself to low power mode.
• Low VCCf write inhibit ≤ 2.5 V
• Program Suspend/Resume
Suspends the program operation to allow a read in another byte
• Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Please refer to “MBM29DL64DF” data sheet in detailed function
(Continued)
2
MB84VD23180FM-70
(Continued)
 SRAM
• Power dissipation
Operating : 40 mA Max
Standby : 10 µA Max
• Power down features using CE1s and CE2s
• Data retention supply voltage: 1.5 V to 3.1 V
• CE1s and CE2s Chip Select
• Byte data control: LB (DQ7 to DQ0), UB (DQ15 to DQ8)
*1 : FlexBankTM is a trademark of Fujitsu Limited, Japan.
*2 : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
3
MB84VD23180FM-70
■ PIN ASSIGNMENT
(Top View)
Marking side
A10
B10
F10
G10
L10
M10
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
D9
E9
F9
G9
H9
J9
A15
A21
N.C.
A16
CIOf
VSS
C8
D8
E8
F8
G8
H8
J8
K8
A11
A12
A13
A14
N.C.
DQ15/A-1
DQ7
DQ14
C7
D7
E7
F7
G7
H7
J7
K7
A8
A19
A9
A10
DQ6
DQ13
DQ12
DQ5
B6
C6
D6
E6
H6
J6
K6
L6
N.C.
WE
CE2s
A20
DQ4
VCCs
N.C.
N.C.
B5
C5
D5
E5
H5
J5
K5
L5
N.C.
WP/ACC
RESET
RY/BY
DQ3
VCCf
DQ11
N.C.
C4
D4
E4
F4
G4
H4
J4
K4
LB
UB
A18
A17
DQ1
DQ9
DQ10
DQ2
C3
D3
E3
F3
G3
H3
J3
K3
A7
A6
A5
A4
VSS
OE
DQ0
DQ8
D2
E2
F2
G2
H2
J2
A3
A2
A1
A0
CEf
CE1s
A1
B1
C1
F1
G1
L1
M1
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
(BGA-73P-M03)
4
MB84VD23180FM-70
■ PIN DESCRIPTION
Pin name
Input/
Output
A17 to A0
I
Address Inputs (Common)
A21 to A18 , A-1
I
Address Inputs (Flash)
DQ15 to DQ0
I/O
CEf
I
Chip Enable (Flash)
CE1s
I
Chip Enable (SRAM)
CE2s
I
Chip Enable (SRAM)
OE
I
Output Enable (Common)
WE
I
Write Enable (Common)
RY/BY
O
Ready/Busy Output (Flash) Open Drain Output
UB
I
Upper Byte Control (SRAM)
LB
I
Lower Byte Control (SRAM)
CIOf
I
I/O Configulation (Flash)
CIOf = Vccf is Word mode (×16), CIOf = Vss is Byte mode (×8)
RESET
I
Hardware Reset Pin/Sector Protection Unlock (Flash)
WP/ACC
I
Write Protect / Acceleration (Flash)
N.C.
—
VSS
Power
Device Ground (Common)
VCCf
Power
Device Power Supply (Flash)
VCCs
Power
Device Power Supply (SRAM)
Description
Data Inputs/Outputs (Common)
No Internal Connection
5
MB84VD23180FM-70
■ BLOCK DIAGRAM
VCCf
VSS
A21 to A0
RY/BY
A21 to A0
A-1
WP/ACC
RESET
CEf
64 M bit
Flash Memory
DQ15/A-1 to DQ0
CIOf
DQ15/A-1 to DQ0
VCCs
VSS
A17 to A0
DQ15 to DQ0
LB
UB
WE
OE
CE1s
CE2s
6
4 M bit
Static RAM
MB84VD23180FM-70
■ DEVICE BUS OPERATIONS
User Bus Operations (Flash=Word mode; CIOf=Vccf)
Operation *1, *3
Full Standby
CEf CE1s CE2s
H
H
Output Disable
L
Read from Flash *2
L
Write to Flash
L
Read from SRAM
Write to SRAM
H
H
Temporary
Sector Group
Unprotection *4
X
Flash Hardware
Reset
X
H
X
X
L
L
H
H
X
X
L
H
X
X
L
H
X
X
L
L
L
H
H
X
X
H
X
X
L
OE
WE
LB
UB
X
X
X
X
High-Z
High-Z
H
H
X
X
High-Z
High-Z
X
X
H
H
High-Z
High-Z
H
H
X
X
High-Z
High-Z
L
H
X
X
DOUT
H
L
X
X
L
L
X
H
L
DQ7 to DQ0 DQ15 to DQ8 RESET
WP/
ACC*5
H
X
H
X
DOUT
H
X
DIN
DIN
H
X
L
DOUT
DOUT
H
L
High-Z
DOUT
H
X
L
H
DOUT
High-Z
L
L
DIN
DIN
H
L
High-Z
DIN
H
X
L
H
DIN
High-Z
X
X
X
X
X
X
VID
X
X
X
X
X
High-Z
High-Z
L
X
X
X
L
Boot Block Sector
X
X
X
X
X
X
X
X
Write Protection
Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.
*1 : Other operations except for indicated this column are inhibited.
*2 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*3 : Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time.
*4 : It is also used for the extended sector group protections.
*5 : Protect of 2 of 8 Kbytes on both ends of each boot sector.
7
MB84VD23180FM-70
Operation *1, *3
Full Standby
User Bus Operations (Flash=Byte mode; CIOf=Vss)
LB UB
DQ0 to
CEf CE1s CE2s DQ15/A–1 OE WE
DQ7
(6)
(6)
H
H
Output Disable
L
H
X
X
L
L
H
H
X
X
L
H
X
X
L
H
X
X
L
RESET
WP/
ACC*5
H
X
H
X
X
X
X
X
X
High-Z
High-Z
X
H
H
X
X
High-Z
High-Z
X
X
X
H
H
High-Z
High-Z
A–1
H
H
X
X
High-Z
High-Z
A–1
L
H
X
X
DOUT
X
H
X
A–1
H
L
X
X
DIN
X
H
X
Read from Flash*2
L
Write to Flash
L
Read from SRAM
H
L
H
X
L
H
X
X
DOUT
High-Z
H
X
Write to SRAM
H
L
H
X
X
L
X
X
DIN
High-Z
H
X
Temporary
Sector Group Unprotection*4
X
X
X
X
X
X
X
X
X
X
VID
X
Flash Hardware
Reset
X
H
X
X
L
X
X
X
X
X
High-Z
High-Z
L
X
X
X
L
Boot Block Sector
X
X
X
X
X
X
X
X
X
Write Protection
Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.
*1 : Other operations except for indicated this column are inhibited.
*2 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*3 : Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time.
*4 : It is also used for the extended sector group protections.
*5 : Protect of 2 of 8 Kbytes on both ends of each boot sector.
8
DQ8 to
DQ14
MB84VD23180FM-70
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Symbol
Unit
Min
Max
Tstg
–55
+125
°C
Ta
–30
+85
°C
VIN, VOUT
–0.3
VCCf +0.3
V
VCCs +0.3
V
VCCf/VCCs Supply *1
VCCf, VCCs
–0.3
+3.3
V
2
VIN
–0.5
+ 13.0
V
VIN
–0.5
+10.5
V
Storage Temperature
Ambient Temperature with Power Applied
Voltage with Respect to Ground All pins
except RESET,WP/ACC *1
RESET *
3
WP/ACC *
*1: Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may undershoot
VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf + 0.3 V or VCCs + 0.3 V.
During voltage transitions, input or I/O pins may overshoot to VCCf + 2.0 V or VCCs + 2.0 V for periods of up to 20 ns.
*2: Minimum DC input voltage on RESET pin is –0.5 V. During voltage transitions, RESET pins may undershoot VSS
to –2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCCf or VCCs) does
not exceed +9.0 V. Maximum DC input voltage on RESET pins is +13.0 V which may overshoot to +14.0 V for
periods of up to 20 ns.
*3: Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may undershoot
Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may
overshoot to +12.0 V for periods of up to 20 ns, when VCCf is applied.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Ambient Temperature
VCCf/VCCs Supply Voltages
Symbol
Value
Unit
Min
Max
Ta
–30
+85
°C
VCCf, VCCs
+2.7
+3.1
V
Note: Operating ranges define those limits between which the functionality of the device is guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
9
MB84VD23180FM-70
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Parameter
Value
Conditions
Symbol
Min
Typ
Max
Unit
Input Leakage Current
ILI
VIN = VSS to VCCf, VCCs
–1.0
—
+1.0
µA
Output Leakage Current
ILO
VOUT = VSS to VCCf, VCCs
–1.0
—
+1.0
µA
RESET Inputs Leakage
Current
ILIT
VCCf = VCCf Max, VCCs = VCCs Max,
RESET = 12.5 V
—
—
35
µA
ACC Input Leakage Current
ILIA
VCCf = VCCf Max, VCCs = VCCs Max,
WP/ACC = VACC Max
—
—
20
mA
Flash VCC Active Current
(Read) *1
ICC1f
CEf = VIL,
OE = VIH
tCYCLE = 5 MHz
Word
—
—
18
tCYCLE = 1 MHz
Word
—
—
4
tCYCLE = 5 MHz
Byte
—
—
16
mA
tCYCLE = 1 MHz
Byte
—
—
4
mA
—
—
30
mA
Word
—
—
48
mA
Byte
—
—
46
mA
Word
—
—
48
mA
Byte
—
—
46
mA
mA
Flash VCC Active Current
(Program/Erase) *2
ICC2f
CEf = VIL, OE = VIH
Flash VCC Active Current
(Read-While-Program) *5
ICC3f
CEf = VIL, OE = VIH
Flash VCC Active Current
(Read-While-Erase) *5
ICC4f
CEf = VIL, OE = VIH
Flash VCC Active Current
(Erase-Suspend-Program)
ICC5f
CEf = VIL, OE = VIH
—
—
30
mA
SRAM VCC Active Current
ICC1s
VCCs = VCCs Max,
CE1s = VIL,
tCYCLE =10 MHz
CE2s = VIH
—
—
40
mA
—
—
40
mA
ICC2s
CE1s = 0.2 V,
CE2s =
VCCs – 0.2 V
tCYCLE = 10 MHz
SRAM VCC Active Current
tCYCLE = 1 MHz
—
—
8
mA
Flash VCC Standby Current
ISB1f
VCCf = VCCf Max, CEf = VCCf ± 0.3 V
RESET = VCCf ± 0.3 V,
WP/ACC = VCCf± 0.3 V
—
1
5
µA
Flash VCC Standby Current
(RESET)
ISB2f
VCCf = VCCf Max, RESET = VSS ± 0.3 V,
WP/ACC = VCCf± 0.3 V
—
1
5
µA
Flash VCC Current
(Automatic Sleep Mode) *3
ISB3f
VCCf = VCCf Max, CEf = VSS ± 0.3 V
RESET = VCCf ± 0.3 V,
WP/ACC = VCCf± 0.3 V,
VIN = VCCf± 0.3 V or VSS ± 0.3 V
—
1
5
µA
SRAM VCC Standby
Current
ISB1s
CE1s > VCCs – 0.2 V, CE2s > VCCs – 0.2 V
LB = UB > VCCs–0.2 V or < 0.2V
—
—
10
µA
SRAM VCC Standby
Current
ISB2s
CE1s > VCCs – 0.2 V or < 0.2V,
CE2s < 0.2 V
LB = UB > VCCs–0.2 V or < 0.2V
—
—
10
µA
(Continued)
10
MB84VD23180FM-70
(Continued)
Symbol
Conditions
Input Low Level
VIL
Input High Level
Voltage for Sector Protection,
and Temporary Sector
Unprotection (RESET) *4
Parameter
Value
Unit
Min
Typ
Max
—
–0.3
—
0.5
V
VIH
—
2.4
—
VCC+0.3
*6
V
VID
—
11.5
12
12.5
V
Voltage for Program
Acceleration (WP/ACC) *4
VACC
—
8.5
9.0
9.5
V
Output Low Voltage Level
VOL
Flash
—
—
0.45
V
VCCs = VCCs Min, IOL=1.0 mA SRAM
—
—
0.4
V
VCCf = VCCf Min, IOH=–0.1 mA Flash
0.85×
VCCf
—
—
V
2.2
—
—
V
2.3
2.4
2.5
V
Output High Voltage Level
VOH
VCCf = VCCf Min, IOL=4.0 mA
VCCs = VCCs Min, IOH=–0.5 mA
Flash Low VCCf Lock-Out
Voltage
VLKO
SRAM
—
*1: The ICC current listed includes both the DC operating current and the frequency dependent component.
*2: ICC active while Embedded Algorithm (program or erase) is in progress.
*3: Automatic sleep mode enables the low power mode when address remains stable for 150 ns.
*4: Applicable for only VCCf applying.
*5: Embedded Algorithm (program or erase) is in progress. (@5 MHz)
*6: VCC indicates lower of VCCf or VCCs.
11
MB84VD23180FM-70
2. AC Characteristics
• CE Timing
Parameter
Symbol
JEDEC
Standard
CE Recover Time
—
tCCR
CE Hold Time
—
tCHOLD
Condition
Value
Max
—
0
—
ns
—
3
—
ns
• Timing Diagram for alternating SRAM to Flash
CEf
tCCR
tCCR
CE1s
WE
tCHOLD
tCCR
CE2s
• Flash characteristics
Please refer to “■ 64M FLASH MEMORY CHARACTERISTICS for MCP” part.
• SRAM characteristics
Please refer to “■ 4M SRAM MEMORY CHARACTERISTICS for MCP” part.
12
Unit
Min
tCHOLD
tCCR
MB84VD23180FM-70
■ 64M FLASH MEMORY FOR MCP
1. Flexible Sector-erase Architecture on Flash Memory
• Sixteen 4K words, and one hundred twenty-six 32 K words.
• Individual-sector, multiple-sector, or bulk-erase capability.
Bank A
Bank B
SA0 : 8KB (4KW)
SA1 : 8KB (4KW)
SA2 : 8KB (4KW)
SA3 : 8KB (4KW)
SA4 : 8KB (4KW)
SA5 : 8KB (4KW)
SA6 : 8KB (4KW)
SA7 : 8KB (4KW)
SA8 : 64KB (32KW)
SA9 : 64KB (32KW)
SA10 : 64KB (32KW)
SA11 : 64KB (32KW)
SA12 : 64KB (32KW)
SA13 : 64KB (32KW)
SA14 : 64KB (32KW)
SA15 : 64KB (32KW)
SA16 : 64KB (32KW)
SA17 : 64KB (32KW)
SA18 : 64KB (32KW)
SA19 : 64KB (32KW)
SA20 : 64KB (32KW)
SA21 : 64KB (32KW)
SA22 : 64KB (32KW)
SA23 : 64KB (32KW)
SA24 : 64KB (32KW)
SA25 : 64KB (32KW)
SA26 : 64KB (32KW)
SA27 : 64KB (32KW)
SA28 : 64KB (32KW)
SA29 : 64KB (32KW)
SA30 : 64KB (32KW)
SA31 : 64KB (32KW)
SA32 : 64KB (32KW)
SA33 : 64KB (32KW)
SA34 : 64KB (32KW)
SA35 : 64KB (32KW)
SA36 : 64KB (32KW)
SA37 : 64KB (32KW)
SA38 : 64KB (32KW)
SA39 : 64KB (32KW)
SA40 : 64KB (32KW)
SA41 : 64KB (32KW)
SA42 : 64KB (32KW)
SA43 : 64KB (32KW)
SA44 : 64KB (32KW)
SA45 : 64KB (32KW)
SA46 : 64KB (32KW)
SA47 : 64KB (32KW)
SA48 : 64KB (32KW)
SA49 : 64KB (32KW)
SA50 : 64KB (32KW)
SA51 : 64KB (32KW)
SA52 : 64KB (32KW)
SA53 : 64KB (32KW)
SA54 : 64KB (32KW)
SA55 : 64KB (32KW)
SA56 : 64KB (32KW)
SA57 : 64KB (32KW)
SA58 : 64KB (32KW)
SA59 : 64KB (32KW)
SA60 : 64KB (32KW)
SA61 : 64KB (32KW)
SA62 : 64KB (32KW)
SA63 : 64KB (32KW)
SA64 : 64KB (32KW)
SA65 : 64KB (32KW)
SA66 : 64KB (32KW)
SA67 : 64KB (32KW)
SA68 : 64KB (32KW)
SA69 : 64KB (32KW)
SA70 : 64KB (32KW)
Word Mode
000000h
001000h
002000h
003000h
004000h
005000h
006000h
007000h
008000h
010000h
018000h
020000h
028000h
030000h
038000h
040000h
048000h
050000h
058000h
060000h
068000h
070000h
078000h
080000h
088000h
090000h
098000h
0A0000h
0A8000h
0B0000h
0B8000h
0C0000h
0C8000h
0D0000h
0D8000h
0E0000h
0E8000h
0F0000h
0F8000h
100000h
108000h
110000h
118000h
120000h
128000h
130000h
138000h
140000h
148000h
150000h
158000h
160000h
168000h
170000h
178000h
180000h
188000h
190000h
198000h
1A0000h
1A8000h
1B0000h
1B8000h
1C0000h
1C8000h
1D0000h
1D8000h
1E0000h
1E8000h
1F0000h
1F8000h
1FFFFFh
Bank C
Bank D
SA71 : 64KB (32KW)
SA72 : 64KB (32KW)
SA73 : 64KB (32KW)
SA74 : 64KB (32KW)
SA75 : 64KB (32KW)
SA76 : 64KB (32KW)
SA77 : 64KB (32KW)
SA78 : 64KB (32KW)
SA79 : 64KB (32KW)
SA80 : 64KB (32KW)
SA81 : 64KB (32KW)
SA82 : 64KB (32KW)
SA83 : 64KB (32KW)
SA84 : 64KB (32KW)
SA85 : 64KB (32KW)
SA86 : 64KB (32KW)
SA87 : 64KB (32KW)
SA88 : 64KB (32KW)
SA89 : 64KB (32KW)
SA90 : 64KB (32KW)
SA91 : 64KB (32KW)
SA92 : 64KB (32KW)
SA93 : 64KB (32KW)
SA94 : 64KB (32KW)
SA95 : 64KB (32KW)
SA96 : 64KB (32KW)
SA97 : 64KB (32KW)
SA98 : 64KB (32KW)
SA99 : 64KB (32KW)
SA100 : 64KB (32KW)
SA101 : 64KB (32KW)
SA102 : 64KB (32KW)
SA103 : 64KB (32KW)
SA104 : 64KB (32KW)
SA105 : 64KB (32KW)
SA106 : 64KB (32KW)
SA107 : 64KB (32KW)
SA108 : 64KB (32KW)
SA109 : 64KB (32KW)
SA110 : 64KB (32KW)
SA111 : 64KB (32KW)
SA112 : 64KB (32KW)
SA113 : 64KB (32KW)
SA114 : 64KB (32KW)
SA115 : 64KB (32KW)
SA116 : 64KB (32KW)
SA117 : 64KB (32KW)
SA118 : 64KB (32KW)
SA119 : 64KB (32KW)
SA120 : 64KB (32KW)
SA121 : 64KB (32KW)
SA122 : 64KB (32KW)
SA123 : 64KB (32KW)
SA124 : 64KB (32KW)
SA125 : 64KB (32KW)
SA126 : 64KB (32KW)
SA127 : 64KB (32KW)
SA128 : 64KB (32KW)
SA129 : 64KB (32KW)
SA130 : 64KB (32KW)
SA131 : 64KB (32KW)
SA132 : 64KB (32KW)
SA133 : 64KB (32KW)
SA134 : 8KB (4KW)
SA135 : 8KB (4KW)
SA136 : 8KB (4KW)
SA137 : 8KB (4KW)
SA138 : 8KB (4KW)
SA139 : 8KB (4KW)
SA140 : 8KB (4KW)
SA141 : 8KB (4KW)
Word Mode
200000h
208000h
210000h
218000h
220000h
228000h
230000h
238000h
240000h
248000h
250000h
258000h
260000h
268000h
270000h
278000h
280000h
288000h
290000h
298000h
2A0000h
2A8000h
2B0000h
2B8000h
2C0000h
2C8000h
2D0000h
2D8000h
2E0000h
2E8000h
2F0000h
2F8000h
300000h
308000h
310000h
318000h
320000h
328000h
330000h
338000h
340000h
348000h
350000h
358000h
360000h
368000h
370000h
378000h
380000h
388000h
390000h
398000h
3A0000h
3A8000h
3B0000h
3B8000h
3C0000h
3C8000h
3D0000h
3D8000h
3E0000h
3E8000h
3F0000h
3F8000h
3F9000h
3FA000h
3FB000h
3FC000h
3FD000h
3FE000h
3FF000h
3FFFFFh
Sector Architecture
13
MB84VD23180FM-70
FlexBankTM Architecture
Bank 1
Bank 2
Bank
Splits
Volume
Combination
Volume
Combination
1
8 Mbit
Bank A
56 Mbit
Remainder (Bank B, C, D)
2
24 Mbit
Bank B
40 Mbit
Remainder (Bank A, C, D)
3
24 Mbit
Bank C
40 Mbit
Remainder (Bank A, B, D)
4
8 Mbit
Bank D
56 Mbit
Remainder (Bank A, B, C)
Example of Virtual Banks Combination
Bank 1
Bank 2
Bank
Splits Volume Combination
Sector Size
Volume Combination
Sector Size
Bank B
8 × 8 Kbyte/4 Kword
+
8 × 8 Kbyte/4 Kword
1
8 Mbit
Bank A
+
56 Mbit
Bank C
+
15 × 64 Kbyte/32 Kword
+
111 × 64 Kbyte/32 Kword
Bank D
Bank A
16 × 8 Kbyte/4 Kword
Bank B
2
16 Mbit
+
+
48 Mbit
+
96 × 64 Kbyte/32 Kword
Bank D
30 × 64 Kbyte/32 Kword
Bank C
Bank A
+
16 × 8 Kbyte/4 Kword
3
24 Mbit
Bank B
48 × 64 Kbyte/32 Kword 40 Mbit
Bank C
+
+
78 × 64 Kbyte/32 Kword
Bank D
Bank A
8 × 8 Kbyte/4 Kword
Bank C
8 × 8 Kbyte/4 Kword
4
32 Mbit
+
+
32 Mbit
+
+
Bank B
63 × 64 Kbyte/32 Kword
Bank D
63 × 64 Kbyte/32 Kword
Note : When multiple sector erase over several banks is operated, the system cannot read out of the bank to which
a sector being erased belongs. For example, suppose that erasing is taking place at both Bank A and Bank B,
neither Bank A nor Bank B is read out (they would output the sequence flag once they were selected.)
Meanwhile the system would get to read from either Bank C or Bank D.
Case
1
2
3
4
5
6
7
Simultaneous Operation
Bank 1 Status
Read mode
Read mode
Read mode
Read mode
Autoselect mode
Program mode
Erase mode *
Bank 2 Status
Read mode
Autoselect mode
Program mode
Erase mode *
Read mode
Read mode
Read mode
* : By writing erase suspend command on the bank address of sector being erased, the erase operation gets
suspended so that it enables reading from or programming the remaining sectors.
Note: Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank
consists of 4 banks, Bank A, Bank B, BankC and Bank D. Bank Address (BA) meant to specify each of the
Banks.
14
MB84VD23180FM-70
Sector Address Tables
Sector Address
Bank
Bank A
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
Bank Address
A21
A20
A19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Address Range
A18
A17
A16
A15
A14
A13
A12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Word Mode
000000h to 000FFFh
001000h to 001FFFh
002000h to 002FFFh
003000h to 003FFFh
004000h to 004FFFh
005000h to 005FFFh
006000h to 006FFFh
007000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
(Continued)
15
MB84VD23180FM-70
(Continued)
Sector Address
Bank
Bank B
Sector
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
Bank Address
A21
A20
A19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Address Range
A18
A17
A16
A15
A14
A13
A12
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Word Mode
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
100000h to 107FFFh
108000h to 10FFFFh
110000h to 117FFFh
118000h to 11FFFFh
120000h to 127FFFh
128000h to 12FFFFh
130000h to 137FFFh
138000h to 13FFFFh
140000h to 147FFFh
148000h to 14FFFFh
150000h to 157FFFh
158000h to 15FFFFh
160000h to 167FFFh
168000h to 16FFFFh
170000h to 177FFFh
178000h to 17FFFFh
180000h to 187FFFh
188000h to 18FFFFh
190000h to 197FFFh
198000h to 19FFFFh
1A0000h to 1A7FFFh
1A8000h to 1AFFFFh
1B0000h to 1B7FFFh
1B8000h to 1BFFFFh
1C0000h to 1C7FFFh
1C8000h to 1CFFFFh
1D0000h to 1D7FFFh
1D8000h to 1DFFFFh
1E0000h to 1E7FFFh
1E8000h to 1EFFFFh
1F0000h to 1F7FFFh
1F8000h to 1FFFFFh
(Continued)
16
MB84VD23180FM-70
(Continued)
Sector Address
Bank
Bank C
Sector
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
Bank Address
A21
A20
A19
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Address Range
A18
A17
A16
A15
A14
A13
A12
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Word Mode
200000h to 207FFFh
208000h to 20FFFFh
210000h to 217FFFh
218000h to 21FFFFh
220000h to 227FFFh
228000h to 22FFFFh
230000h to 237FFFh
238000h to 23FFFFh
240000h to 247FFFh
248000h to 24FFFFh
250000h to 257FFFh
258000h to 25FFFFh
260000h to 267FFFh
268000h to 26FFFFh
270000h to 277FFFh
278000h to 27FFFFh
280000h to 287FFFh
288000h to 28FFFFh
290000h to 297FFFh
298000h to 29FFFFh
2A0000h to 2A7FFFh
2A8000h to 2AFFFFh
2B0000h to 2B7FFFh
2B8000h to 2BFFFFh
2C0000h to 2C7FFFh
2C8000h to 2CFFFFh
2D0000h to 2D7FFFh
2D8000h to 2DFFFFh
2E0000h to 2E7FFFh
2E8000h to 2EFFFFh
2F0000h to 2F7FFFh
2F8000h to 2FFFFFh
300000h to 307FFFh
308000h to 30FFFFh
310000h to 317FFFh
318000h to 31FFFFh
320000h to 327FFFh
328000h to 32FFFFh
330000h to 337FFFh
338000h to 33FFFFh
340000h to 347FFFh
348000h to 34FFFFh
350000h to 357FFFh
358000h to 35FFFFh
360000h to 367FFFh
368000h to 36FFFFh
370000h to 377FFFh
378000h to 37FFFFh
(Continued)
17
MB84VD23180FM-70
(Continued)
Sector Address
Bank
Bank D
18
Sector
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
Bank Address
A21
A20
A19
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Address Range
A18
A17
A16
A15
A14
A13
A12
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
Word Mode
380000h to 387FFFh
388000h to 38FFFFh
390000h to 397FFFh
398000h to 39FFFFh
3A0000h to 3A7FFFh
3A8000h to 3AFFFFh
3B0000h to 3B7FFFh
3B8000h to 3BFFFFh
3C0000h to 3C7FFFh
3C8000h to 3CFFFFh
3D0000h to 3D7FFFh
3D8000h to 3DFFFFh
3E0000h to 3E7FFFh
3E8000h to 3EFFFFh
3F0000h to 3F7FFFh
3F8000h to 3F8FFFh
3F9000h to 3F9FFFh
3FA000h to 3FAFFFh
3FB000h to 3FBFFFh
3FC000h to 3FCFFFh
3FD000h to 3FDFFFh
3FE000h to 3FEFFFh
3FF000h to 3FFFFFh
MB84VD23180FM-70
Sector Group Addresses
Sector Group
SGA0
SGA1
SGA2
SGA3
SGA4
SGA5
SGA6
SGA7
A21
0
0
0
0
0
0
0
0
A20
0
0
0
0
0
0
0
0
A19
0
0
0
0
0
0
0
0
A18
0
0
0
0
0
0
0
0
A17
0
0
0
0
0
0
0
0
SGA8
0
0
0
0
0
SGA9
SGA10
SGA11
SGA12
SGA13
SGA14
SGA15
SGA16
SGA17
SGA18
SGA19
SGA20
SGA21
SGA22
SGA23
SGA24
SGA25
SGA26
SGA27
SGA28
SGA29
SGA30
SGA31
SGA32
SGA33
SGA34
SGA35
SGA36
SGA37
SGA38
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
SGA39
1
1
1
1
1
SGA40
SGA41
SGA42
SGA43
SGA44
SGA45
SGA46
SGA47
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A16
0
0
0
0
0
0
0
0
0
1
1
A15
0
0
0
0
0
0
0
0
1
0
1
A14
0
0
0
0
1
1
1
1
A13
0
0
1
1
0
0
1
1
A12
0
1
0
1
0
1
0
1
Sectors
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
X
X
X
SA8 to SA10
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA11 to SA14
SA15 to SA18
SA19 to SA22
SA23 to SA26
SA27 to SA30
SA31 to SA34
SA35 to SA38
SA39 to SA42
SA43 to SA46
SA47 to SA50
SA51 to SA54
SA55 to SA58
SA59 to SA62
SA63 to SA66
SA67 to SA70
SA71 to SA74
SA75 to SA78
SA79 to SA82
SA83 to SA86
SA87 to SA90
SA91 to SA94
SA95 to SA98
SA99 to SA102
SA103 to SA106
SA107 to SA110
SA111 to SA114
SA115 to SA118
SA119 to SA122
SA123 to SA126
SA127 to SA130
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
X
X
X
SA131 to SA133
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
19
MB84VD23180FM-70
Flash Memory Autoselect Codes
A6
A3
A2
Type
A21 to A12
Manufacture’s Code
BA
L
L
Device Code
BA
L
Extended Device
Code *2
BA
Sector Group Protection
A1
A0
Code (HEX)
L
L
L
04h
L
L
L
H
227Eh
L
H
H
H
L
2202h
BA
L
H
H
H
H
2201h
Sector Group
Addresses
L
L
L
H
L
01h*1
Legend: L = VIL, H = VIH. See DC Characteristics for voltage levels.
*1 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.
*2 : A read cycle at address (BA) 01h outputs device code. When 227Eh was output, this indicates that there will
require two additional codes, called Extended Device Codes. Therefore the system may continue reading out
these Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh.
20
MB84VD23180FM-70
Command
Sequence
Bus
Write
Cycles
Req’d
Flash Memory Command Definitions
Fourth Bus
First Bus
Second Bus Third Bus
Read/Write
Write Cycle Write Cycle Write Cycle
Cycle
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Fifth Bus
Write Cycle
Sixth Bus
Write Cycle
Data Addr. Data Addr. Data
Read/Reset
1
XXXh
F0h
—
—
—
—
—
—
—
—
—
—
Read/Reset
3
555h
AAh
2AAh
55h
555h
F0h
RA
RD
—
—
—
—
Autoselect
3
555h
AAh
2AAh
55h
(BA)
555h
90h
—
—
—
—
—
—
Program
4
555h
AAh
2AAh
55h
555h
A0h
PA
PD
—
—
—
—
Program
Suspend
1
BA
B0h
—
—
—
—
—
—
—
—
—
—
Program Resume
1
BA
30h
—
—
—
—
—
—
—
—
—
—
Chip Erase
6
555h
AAh
2AAh
55h
555h
80h
555h
AAh 2AAh
55h
555h
10h
Sector Erase
6
555h
AAh
2AAh
55h
555h
80h
555h
AAh 2AAh
55h
SA
30h
Erase
Suspend
1
BA
B0h
—
—
—
—
—
—
—
—
—
—
Erase
Resume
1
BA
30h
—
—
—
—
—
—
—
—
—
—
Extended
Sector Group
Protection *2
4
XXXh
60h
SPA
60h
SPA
40h
SPA
SD
—
—
—
—
Set to
Fast Mode
3
555h
AAh
2AAh
55h
555h
20h
—
—
—
—
—
—
Fast
Program *1
2
XXXh
A0h
PA
PD
—
—
—
—
—
—
—
—
Reset from
Fast Mode *1
2
BA
90h
XXXh
*4
F0h
—
—
—
—
—
—
—
—
Query
1
(BA)
55h
98h
—
—
—
—
—
—
—
—
—
—
HiddenROM
Entry
3
555h
AAh
2AAh
55h
555h
88h
—
—
—
—
—
—
HiddenROM
Program *3
4
555h
AAh
2AAh
55h
555h
A0h
PD
—
—
—
—
HiddenROM
Exit *3
4
555h
AAh
2AAh
55h
00h
—
—
—
—
(HRBA)
555h
90h
(HRA)
PA
XXXh
(Continued)
21
MB84VD23180FM-70
(Continued)
*1: This command is valid during Fast Mode.
*2: This command is valid while RESET = VID.
*3: This command is valid during HiddenROM mode.
*4: The data “00h” is also acceptable.
Notes : • Address bits A21 to A11 = X = “H” or “L” for all address commands except or Program Address (PA),
Sector Address (SA), and Bank Address (BA), and Sector Group Address (SPA).
• Bus operations are defined in ■ DEVICE BUS OPERATION.
• RA = Address of the memory location to be read
PA = Address of the memory location to be programmed
Addresses are latched on the falling edge of the write pulse.
SA = Address of the sector to be erased. The combination of A21, A20, A19, A18, A17, A16, A15, A14, A13, and
A12 will uniquely select any sector.
BA = Bank Address (A21, A20, A19)
• RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse.
• SPA = Sector group address to be protected. Set sector group address and (A6, A3, A2, A1, A0) =
(0, 0, 0, 1, 0).
SD = Sector group protection verify data. Output 01h at protected sector group addresses and output
00h at unprotected sector group addresses.
• HRA = Address of the HiddenROM area: 000000h to 00007Fh
• HRBA = Bank Address of the HiddenROM area (A21 = A20 = A19 = VIL)
• The system should generate the following address patterns: 555h or 2AAh to addresses A10 to A0
• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
• The command combinations not described in this table are illegal.
22
MB84VD23180FM-70
2. AC Characteristics
• Read Only Operations Characteristics (Flash)
Symbol
Parameter
JEDEC
Standard
Condition
Value*
Min
Max
Unit
Read Cycle Time
tAVAV
tRC
—
70
—
ns
Address to Output Delay
tAVQV
tACC
CEf = VIL
OE = VIL
—
70
ns
Chip Enable to Output Delay
tELQV
tCEf
OE = VIL
—
70
ns
Output Enable to Output Delay
tGLQV
tOE
—
—
30
ns
Chip Enable to Output High-Z
tEHQZ
tDF
—
—
25
ns
Output Enable to Output High-Z
tGHQZ
tDF
—
—
25
ns
Output Hold Time From Addresses,
CEf or OE, Whichever Occurs First
tAXQX
tOH
—
0
—
ns
—
tREADY
—
—
20
µs
RESET Pin Low to Read Mode
*: Test Conditions– Output Load:1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to VCCf
Timing measurement reference level
Input: 0.5×VCCf
Output: 0.5×VCCf
23
MB84VD23180FM-70
• Read Operation Timing Diagram (Flash)
tRC
Address
Address Stable
tACC
CEf
tOE
tDF
OE
tOEH
WE
tOH
tCE
High-Z
High-Z
Outputs Valid
Outputs
• Hardware Reset/Read Operation Timing Diagram (Flash)
tRC
Address
Address Stable
tACC
CEf
tRH
tRP
tRH
tCE
RESET
tOH
Outputs
24
High-Z
Outputs Valid
MB84VD23180FM-70
• Write/Erase/Program Operations (Flash)
Parameter
Symbol
Value
Unit
JEDEC
Standard
Min
Typ
Max
Write Cycle Time
tAVAV
tWC
70


ns
Address Setup Time
tAVWL
tAS
0


ns

tASO
12


ns
tWLAX
tAH
30


ns

tAHT
0


ns
Data Setup Time
tDVWH
tDS
25


ns
Data Hold Time
tWHDX
tDH
0


ns

0


ns
tOEH
10


ns
CEf High During Toggle Bit Polling

tCEPH
20


ns
OE High During Toggle Bit Polling

tOEPH
20


ns
Read Recover Time Before Write
tGHWL
tGHWL
0


ns
Read Recover Time Before Write
tGHEL
tGHEL
0


ns
CEf Setup Time
tELWL
tCS
0


ns
WE Setup Time
tWLEL
tWS
0


ns
CEf Hold Time
tWHEH
tCH
0


ns
WE Hold Time
tEHWH
tWH
0


ns
Write Pulse Width
tWLWH
tWP
35


ns
CEf Pulse Width
tELEH
tCP
35


ns
Write Pulse Width High
tWHWL
tWPH
20


ns
CEf Pulse Width High
tEHEL
tCPH
20


ns
Programming Operation
tWHWH1
tWHWH1

6

µs
Sector Erase Operation *1
tWHWH2
tWHWH2

0.5

s

tVCS
50


µs
Rise Time to VID *

tVIDR
500


ns
Rise Time to VACC *3

tVACCR
500


ns
Voltage Transition Time *2

tVLHT
4


µs

tWPP
100


µs
Address Setup Time to OE Low During Toggle Bit
Polling
Address Hold Time
Address Hold Time from CEf or OE High During
Toggle Bit Polling
Output
Enable Hold
Time
Read
Toggle and Data Polling
VCCf Setup Time
2
Write Pulse Width *
2
(Continued)
25
MB84VD23180FM-70
(Continued)
Parameter
Symbol
Unit
JEDEC
Standard
Min
Typ
Max

tOESP
4


µs

tCSP
4


µs
Recover Time from RY/BY

tRB
0


ns
RESET Pulse Width

tRP
500


ns
RESET High Level Period Before Read

tRH
200


ns
Program/Erase Valid to RY/BY Delay

tBUSY


90
ns
Delay Time from Embedded Output Enable

tEOE


70
ns
Erase Time-out Time

tTOW
50

µs
Erase Suspend Transition Time

tSPD

20
µs
OE Setup Time to WE Active *2
CEf Setup Time to WE Active *
2
*1: This does not include preprogramming time.
*2: This timing is for Sector Group Protection operation.
*3: This timing is for Accelerated Program operation.
26
Value

MB84VD23180FM-70
• Write Cycle (WE control) (Flash)
3rd Bus Cycle
Data Polling
555h
Address
tWC
PA
tAS
PA
tRC
tAH
CEf
tCS
tCH
tCE
OE
tGHWL
tWP
tOE
tWPH
tWHWH1
WE
Data
A0h
tOH
tDF
tDS tDH
PD
DQ7
DOUT
DOUT
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at word address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles out of four bus cycle sequence.
27
MB84VD23180FM-70
• Write Cycle (CEf control) (Flash)
3rd Bus Cycle
Data Polling
555h
Address
tWC
PA
PA
tAS
tAH
WE
tWS
tWH
OE
tGHEL
tCP
tCPH
tWHWH1
CEf
tDS
Data
A0h
tDH
PD
DQ7
DOUT
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at word address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles out of four bus cycle sequence.
28
MB84VD23180FM-70
• AC Waveforms Chip/Sector Erase Operations (Flash)
555h
Address
tWC
2AAh
tAS
555h
555h
2AAh
SA*
tAH
CEf
tCS
tCH
OE
tGHWL
tWP
tWPH
tDS
tDH
WE
AAh
Data
30h for Sector Erase
55h
80h
AAh
55h
10h/
30h
tVCS
VCCf
* : SA is the sector address for Sector Erase. Addresses = 555h (Word) for Chip Erase.
29
MB84VD23180FM-70
• AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)
CEf
tCH
tDF
tOE
OE
tOEH
WE
tCE
*
DQ7
Data
DQ7
DQ7 =
Valid Data
High-Z
tWHWH1 or 2
DQ6 to DQ0
DQ6 to DQ0 =
Output Flag
Data
tBUSY
DQ6 to DQ0
Valid Data
tEOE
RY/BY
* : DQ7 = Valid Data (the device has completed the Embedded operation) .
30
High-Z
MB84VD23180FM-70
• AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)
Address
tAHT tASO
tAHT tAS
CEf
tCEPH
WE
tOEPH
tOEH
tOEH
OE
tDH
DQ 6/DQ2
tOE
Toggle
Data
Data
tCE
Toggle
Data
Toggle
Data
*
Stop
Toggling
Output
Valid
tBUSY
RY/BY
* : DQ6 stops toggling (the device has completed the Embedded operation).
31
MB84VD23180FM-70
• Bank-to-bank Read/Write Timing Diagram (Flash)
Address
Read
Command
Read
Command
Read
Read
tRC
tWC
tRC
tWC
tRC
tRC
BA1
BA2
(555h)
BA1
BA2
(PA)
BA1
BA2
(PA)
tAS
tACC
tAH
tAS
tAHT
tCE
CEf
tOE
tCEPH
OE
tGHWL
tDF
tOEH
tWP
WE
tDS
DQ
Valid
Output
tDH
Valid
Intput
(A0h)
tDF
Valid
Output
Valid
Intput
(PD)
Valid
Output
Status
Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.
BA1 : Address corresponding to Bank 1
BA2 : Address corresponding to Bank 2
32
MB84VD23180FM-70
• RY/BY Timing Diagram during Write/Erase Operations (Flash)
CEf
Rising edge of the last WE signal
WE
Entire programming
or erase operations
RY/BY
tBUSY
• RESET, RY/BY Timing Diagram (Flash)
WE
RESET
tRP
tRB
RY/BY
tREADY
33
MB84VD23180FM-70
• Temporary Sector Unprotection (Flash)
VCCf
tVIDR
tVCS
tVLHT
VID
VIH
RESET
CEf
WE
tVLHT
Program or Erase Command Sequence
tVLHT
RY/BY
Unprotection period
• Acceleration Mode Timing Diagram (Flash)
VCCf
tVACCR
tVCS
tVLHT
VACC
VIH
WP/ACC
CEf
WE
tVLHT
Program or Erase Command Sequence
RY/BY
Acceleration period
34
tVLHT
MB84VD23180FM-70
• Extended Sector Group Protection (Flash)
VCCf
tVCS
RESET
tVLHT
tVIDR
tWC
Address
tWC
SPAX
SPAX
SPAY
A6, A3,
A2, A0
A1
CEf
OE
TIME-OUT
tWP
WE
Data
60h
60h
40h
01h
60h
tOE
SPAX : Sector Group Address to be protected
SPAY : Next Sector Group Address to be protected
TIME-OUT : Time-Out window = 250 µs (Min)
35
MB84VD23180FM-70
3. Erase and Programming Performance (Flash)
Parameter
Value
Unit
Remarks
Min
Typ
Max
Sector Erase Time
—
0.5
2.0
s
Excludes programming time prior to erasure
Word Programming Time
—
6
100
µs
Excludes system-level overhead
Chip Programming Time
—
—
200
s
Excludes system-level overhead
100,000
—
—
cycle
Erase/Program Cycle
Typical Erase conditions Ta = +25°C, VCCf_1 & VCCf_2 = 2.9 V
Typical Program conditions Ta = +25°C, VCCf_1 & VCCf_2 = 2.9 V
36
Data= Checker
MB84VD23180FM-70
■ 4M SRAM FOR MCP
1. AC Characteristics
• Read Cycle (SRAM)
Parameter
Symbol
Value
Min
Max
Unit
Read Cycle Time
tRC
70
—
ns
Address Access Time
tAA
—
70
ns
Chip Enable (CE1s) Access Time
tCO1
—
70
ns
Chip Enable (CE2s) Access Time
tCO2
—
70
ns
Output Enable Access Time
tOE
—
35
ns
LB, UB to Output Valid
tBA
—
70
ns
Chip Enable (CE1s Low and CE2s High) to Output Active
tCOE
5
—
ns
Output Enable Low to Output Active
tOEE
0
—
ns
UB, LB Enable Low to Output Active
tBE
0
—
ns
Chip Enable (CE1s High or CE2s Low) to Output High-Z
tOD
—
25
ns
Output Enable High to Output High-Z
tODO
—
25
ns
UB, LB Output Enable to Output High-Z
tBD
—
25
ns
Output Data Hold Time
tOH
10
—
ns
Note: Test Conditions– Output Load:1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to VCCs
Timing measurement reference level
Input: 0.5×VCCs
Output: 0.5×VCCs
37
MB84VD23180FM-70
• Read Cycle (SRAM)
tRC
Address
tAA
tOH
tCO1
CE1s
tCOE
tOD
tCO2
CE2s
tOD
tOE
OE
tODO
tOEE
LB, UB
tBD
tBA
tBE
tCOE
DQ
Note: WE remains HIGH for the read cycle.
38
Valid Data Out
MB84VD23180FM-70
• Write Cycle (SRAM)
Parameter
Symbol
Value
Min
Max
Unit
Write Cycle Time
tWC
70
—
ns
Write Pulse Width
tWP
50
—
ns
Chip Enable to End of Write
tCW
55
—
ns
Address valid to End of Write
tAW
55
—
ns
UB, LB to End of Write
tBW
55
—
ns
Address Setup Time
tAS
0
—
ns
Write Recovery Time
tWR
0
—
ns
WE Low to Output High-Z
tODW
—
25
ns
WE High to Output Active
tOEW
0
—
ns
Data Setup Time
tDS
30
—
ns
Data Hold Time
tDH
0
—
ns
39
MB84VD23180FM-70
• Write Cycle *1 (WE control) (SRAM)
tWC
Address
tAS
tWP
tWR
WE
tAW
tCW
CE1s
CE2s
tCW
tBW
LB, UB
tOEW
tODW
DOUT
*2
*3
tDS
DIN
*4
tDH
Valid Data In
*4
*1 : If OE is HIGH during the write cycle, the outputs will remain at high impedance.
*2 : If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the output
will remain at high impedance.
*3 : If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the output
will remain at high impedance.
*4 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity
must not be applied.
40
MB84VD23180FM-70
• Write Cycle *1 (CE1s control) (SRAM)
tWC
Address
tAS
tWP
tWR
WE
tAW
tCW
CE1s
CE2s
tCW
tBW
LB, UB
tBE
tCOE
tODW
DOUT
tDS
DIN
*2
tDH
Valid Data In
*2
*1 : If OE is HIGH during the write cycle, the outputs will remain at high impedance.
*2 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity
must not be applied.
41
MB84VD23180FM-70
• Write Cycle *1 (CE2s Control) (SRAM)
tWC
Address
tAS
tWP
tWR
WE
tCW
CE1s
tAW
CE2s
tCW
tBW
LB, UB
tBE
tCOE
tODW
DOUT
tDS
DIN
*2
tDH
Valid Data In
*2
*1 : If OE is HIGH during the write cycle, the outputs will remain at high impedance.
*2 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity
must not be applied.
42
MB84VD23180FM-70
• Write Cycle *1 (LB, UB Control) (SRAM)
tWC
Address
tWP
tWR
WE
tCW
CE1s
tCW
CE2s
tAW
tAS
tBW
LB, UB
tBE
tCOE
tODW
DOUT
tDS
DIN
*2
tDH
Valid Data In
*2
*1 : If OE is HIGH during the write cycle, the outputs will remain at high impedance.
*2 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity
must not be applied.
43
MB84VD23180FM-70
2. Data Retention Characteristics (SRAM)
Parameter
Symbol
Data Retention Supply Voltage
Standby Current
VDH = 3.0 V
Chip Deselect to Data Retention Mode Time
Recovery Time
Value
Unit
Min
Typ
Max
VDH
1.5
—
3.1
V
IDDS2
—
—
10
µA
tCDR
0
—
—
ns
tR
tRC
—
—
ns
Note : tRC: Read cycle time
• CE1s Controlled Data Retention Mode *1
VCCs
Data Retention Mode
2.7 V
VIH
VDH
*2
*2
VCCs – 0.2 V
CE1s
tR
tCDR
GND
*1 : In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs–0.2 V or Vss
to 0.2 V during data retention mode. Other input and input/output pins can be used between –0.3 V to
Vccs+0.3 V.
*2 : When CE1s is operating at the VIH Min level, the standby current is given by ISB1s during the transition
of VCCs from VCCs MAX to VIH Min level.
• CE2s Controlled Data Retention Mode*
VCCs
Data Retention Mode
2.7 V
VDH
VIH
tCDR
tR
CE2s
VIL
0.2 V
GND
* : In CE2s controlled data retention mode, input and input/output pins can be used between
–0.3 V to Vccs+0.3V.
44
MB84VD23180FM-70
■ PIN CAPACITANCE
Parameter
Symbol
Input Capacitance
CIN
Test Setup
Value
Unit
Typ
Max
VIN = 0
11
14
pF
Output Capacitance
COUT
VOUT = 0
12
16
pF
Control Pin Capacitance
CIN2
VIN = 0
14
16
pF
WP/ACC Pin Capacitance
CIN3
VIN = 0
21.5
26
pF
Note: Test conditions Ta = +25°C, f = 1.0 MHz
■ HANDLING OF PACKAGE
Please handle this package carefully since the sides of packages are acute angle.
■ CAUTION
(1) The high voltage (VID) can not apply to address pins and control pins except RESET. Therefore, it can not
use autoselect and sector protect function by applying the high voltage (VID) to specific pins.
(2) For the sector protection, since the high voltage (VID) can be applied to the RESET, it can be protected the
sector useing “Extended sector protect” command.
45
MB84VD23180FM-70
■ ORDERING INFORMATION
MB84VD23180
FM
-70
PBS
PACKAGE TYPE
PBS = 73-ball BGA
SPEED OPTION
See Product Selector Guide
Device Revision
DEVICE NUMBER/DESCRIPTION
64Mega-bit (4M × 16-bit) Dual Operation Flash Memory
3.0V-only Read, Program, and Erase
4Mega-bit(256K × 16-bit) SRAM
46
MB84VD23180FM-70
■ PACKAGE DIMENSION
73-ball plastic FBGA
(BGA-73P-M03)
11.60±0.10(.457±.004)
0.20(.008) S B
B
+0.15
+.006
1.19 –0.10 .047 –.004
(Seated height)
0.80(.031)
REF
0.40(.016)
REF
10
9
0.80(.031)
REF
8
7
A
6
8.00±0.10
(.315±.004)
5
0.40(.016)
REF
4
3
0.10(.004) S
2
1
INDEX-MARK AREA
0.39±0.10
(Stand off)
(.015±.004)
M
L
K
J
H
G
F
E
D
S
C
B
A
INDEX BALL
0.20(.008) S A
73-ø0.45
73-ø0.18
+0.10
–.005
+.004
–.002
ø0.08(.003)
M
S AB
0.10(.004) S
C
2003 FUJITSU LIMITED B73003S-c-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
47
MB84VD23180FM-70
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
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circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
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assumes no liability for any damages whatsoever arising out of
the use of the information.
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function and schematic diagrams, shall not be construed as license
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If any products described in this document represent goods or
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F0310
 FUJITSU LIMITED Printed in Japan