SPANSION MB84VD21184EM

FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50307-1E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
16M (×8/×16) FLASH MEMORY &
4M (×8/×16) STATIC RAM
MB84VD2118XEM-70/MB84VD2119XEM-70
■ FEATURES
• Power Supply Voltage of 2.7 V to 3.3 V
• High Performance
70 ns maximum access time (Flash)
70 ns maximum access time (SRAM)
• Operating Temperature
–40 °C to +85 °C
• Package 56-ball FBGA
(Continued)
■ PRODUCT LINE-UP
Part No.
Supply Voltage(V)
MB84VD2118XEM/MB84VD2119XEM
VCCf*= 3.0 V
+0.3 V
–0.3 V
VCCs*= 3.0 V +0.3V
–0.3 V
Max Address Access Time (ns)
70
70
Max CE Access Time (ns)
70
70
Max OE Access Time (ns)
30
35
*: Both VCCf and VCCs must be in recommended operation range when either part is being accessed.
■ PACKAGE
56-ball plastic FBGA
(BGA-56P-M02)
MB84VD2118XEM/2119XEM-70
(Continued)
• FLASH MEMORY
• Simultaneous Read/Write Operations (Dual Bank)
Miltiple devices available with different bank sizes (Please refer to ORDERING INFORMATION)
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
Zero latency between read and write operations
Read-while-erase
Read-while-program
• Minimum 100,000 Write/Erase Cycles
• Sector Erase Architecture
Eight 4 K words and thirty one 32 K words.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
MB84VD2118XEM: Top sector
MB84VD2119XEM: Bottom sector
• Embedded EraseTM* Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM* Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion
• Ready-Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic Sleep Mode
When addresses remain stable, automatically switch themselves to low power mode.
• Low VCC Write Inhibit ≤ 2.5 V
• HiddenROM Region
64K byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC Input Pin
At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status
(MB84VD2118XEM:SA37,SA38 MB84VD2119XEM:SA0,SA1)
At VIH, allows removal of boot sector protection
At VACC, program time will reduse by 40%.
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Please refer to “MBM29DL16XTE/BE” Datasheet in Detailed Function
• SRAM
• Power Dissipation
Operating : 40 mA Max
Standby : 10 µA Max
• Power Down Features using CE1s and CE2s
• Data Retention Supply Voltage: 1.5 V to 3.3 V
• CE1s and CE2s Chip Select
• Byte Data Control: LB (DQ7 to DQ0), UB (DQ15 to DQ8)
* : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
2
MB84VD2118XEM/2119XEM-70
■ PIN ASSIGNMENT
(Top View)
Marking side
B8
C8
D8
E8
F8
G8
A15
N.C.
N.C.
A16
CIOf
Vss
A7
B7
C7
D7
E7
F7
G7
H7
A11
A12
A13
A14
SA
DQ15/A-1
DQ7
DQ14
A6
B6
C6
D6
E6
F6
G6
H6
A8
A19
A9
A10
DQ6
DQ13
DQ12
DQ5
A5
B5
C5
F5
G5
H5
WE
CE2s
N.C.
DQ4
Vccs
CIOs
A4
B4
C4
F4
G4
H4
RY/BY
DQ3
Vccf
DQ11
WP/ACC RESET
INDEX
LAND*
A3
B3
C3
D3
E3
F3
G3
H3
LB
UB
A18
A17
DQ1
DQ9
DQ10
DQ2
A2
B2
C2
D2
E2
F2
G2
H2
A7
A6
A5
A4
VSS
OE
DQ0
DQ8
B1
C1
D1
E1
F1
G1
A3
A2
A1
A0
CEf
CE1s
* : There is no solder ball. This land should be open electrically.
(BGA-56P-M02)
3
MB84VD2118XEM/2119XEM-70
■ PIN DESCRIPTION
Pin Name
A17 to A0
I/O
Address Inputs (Common)
I
A19, A18, A-1
Address Input (Flash)
I
SA
Address Input (SRAM)
I
DQ15 to DQ0
Data Inputs / Outputs (Common)
I/O
CEf
Chip Enable (Flash)
I
CE1s
Chip Enable (SRAM)
I
CE2s
Chip Enable (SRAM)
I
OE
Output Enable (Common)
I
WE
Write Enable (Common)
I
Ready/Busy Outputs (Flash) Open Drain
Output
O
UB
Upper Byte Control (SRAM)
I
LB
Lower Byte Control (SRAM)
I
CIOf
I/O Configuration (Flash)
CIOf=VCCf is Word mode ( ×16),
CIOf=VSS is Byte mode ( × 8)
I
CIOs
I/O Configuration (SRAM)
CIOs=VCCs is Word mode ( ×16),
CIOs=VSS is Byte mode ( × 8)
I
Hardware Reset Pin / Sector Protection
Unlock (Flash)
I
Write Protect / Acceleration (Flash)
I
RY/BY
RESET
WP/ACC
4
Function
N.C.
No Internal Connection
—
VSS
Device Ground (Common)
Power
VCCf
Device Power Supply (Flash)
Power
VCCs
Device Power Supply (SRAM)
Power
MB84VD2118XEM/2119XEM-70
■ BLOCK DIAGRAM
VCCf
VSS
A19 to A0
RY/BY
A19 to A0
A-1
WP/ACC
RESET
CEf
CIOf
16 M bit
Flash Memory
DQ15/A-1 to DQ0
DQ15/A-1 to DQ0
VCCs
VSS
A17 to A0
SA
LB
UB
WE
OE
CE1s
CE2s
CIOs
4 M bit
Static RAM
DQ15 to DQ0
5
MB84VD2118XEM/2119XEM-70
■ DEVICE BUS OPERATIONS
User Bus Operations Table (Flash=Word mode; CIOf=VCCf, SRAM=Word mode; CIOs=VCCs)
Operation *1, *3
Full Standby
CEf CE1s CE2s OE
H
H
Output Disable
L
Read from Flash *2
L
Write to Flash
L
Read from SRAM
Write to SRAM
H
H
Temporary Sector
Group
Unprotection *4
X
Flash Hardware
Reset
X
Boot Block Sector
Write Protection
X
H
X
X
L
L
H
H
X
X
L
H
X
X
L
H
X
X
L
L
L
H
H
X
X
H
X
X
L
X
X
WP/
DQ7 to DQ0 DQ15 to DQ8 RESET ACC
*5
WE
SA
LB
UB
X
X
X
X
X
High-Z
High-Z
H
H
X
X
X
High-Z
High-Z
X
X
X
H
H
High-Z
High-Z
H
H
X
X
X
High-Z
High-Z
L
H
X
X
X
DOUT
H
L
X
X
X
L
L
X
H
L
X
X
H
X
H
X
DOUT
H
X
DIN
DIN
H
X
L
DOUT
DOUT
H
L
High-Z
DOUT
H
X
L
H
DOUT
High-Z
L
L
DIN
DIN
H
L
High-Z
DIN
H
X
L
H
DIN
High-Z
X
X
X
X
X
X
X
VID
X
X
X
X
X
X
High-Z
High-Z
L
X
X
X
X
X
X
X
X
X
L
Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.
*1 : Other operations except for indicated this column are inhibited.
*2 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*3 : Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time.
*4 : It is also used for the extended sector group protections.
*5 : WP/ACC = VIL; protection of boot sectors.
WP/ACC = VIH; removal of boot sectors protection.
WP/ACC = VACC (9 V) ; Program time will reduce by 40%.
6
MB84VD2118XEM/2119XEM-70
User Bus Operations Table (Flash=Word mode; CIOf=VCCf, SRAM=Byte mode; CIOs=VSS)
Operation *1, *3
Full Standby
CEf CE1s CE2s OE
H
H
Output Disable
L
H
X
X
L
L
H
H
X
X
L
H
X
X
L
H
X
X
L
WP/
DQ7 to DQ0 DQ15 to DQ8 RESET ACC
*5
WE
SA
LB
UB
X
X
X
X
X
High-Z
High-Z
H
H
X
X
X
High-Z
High-Z
X
X
X
H
H
High-Z
High-Z
H
H
X
X
X
High-Z
High-Z
L
H
X
X
X
DOUT
H
L
X
X
X
H
X
H
X
DOUT
H
X
DIN
DIN
H
X
Read from Flash *2
L
Write to Flash
L
Read from SRAM
H
L
H
L
H
SA
X
X
DOUT
High-Z
H
X
Write to SRAM
H
L
H
X
L
SA
X
X
DIN
High-Z
H
X
Temporary Sector
Group
Unprotection *4
X
X
X
X
X
X
X
X
X
X
VID
X
Flash Hardware
Reset
X
H
X
X
L
X
X
X
X
X
High-Z
High-Z
L
X
Boot Block Sector
Write Protection
X
X
X
X
X
X
X
X
X
X
X
L
Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.
*1 : Other operations except for indicated this column are inhibited.
*2 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*3 : Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time.
*4 : It is also used for the extended sector group protections.
*5 : WP/ACC = VIL; protection of boot sectors.
WP/ACC = VIH; removal of boot sectors protection.
WP/ACC = VACC (9 V); Program time will reduce by 40%.
7
MB84VD2118XEM/2119XEM-70
User Bus Operations Table (Flash=Byte mode; CIOf=VSS, SRAM=Byte mode; CIOs=VSS)
Operation *1,*3
Full Standby
CEf CE1s CE2s DQ15/A–1 OE WE SA
H
H
Output Disable
L
H
X
X
L
L
H
H
X
X
L
H
X
X
L
H
X
X
L
LB
UB
DQ7 to
DQ0
WP/
DQ14 to
RESET ACC
DQ8
*5
X
X
X
X
X
X
High-Z
High-Z
H
X
X
H
H
X
X
X
High-Z
High-Z
X
X
X
X
H
H
High-Z
High-Z
H
X
A–1
H
H
X
X
X
High-Z
High-Z
A–1
L
H
X
X
X
DOUT
High-Z
H
X
A–1
H
L
X
X
X
DIN
High-Z
H
X
Read from Flash
*2
L
Write to Flash
L
Read from SRAM
H
L
H
X
L
H
SA
X
X
DOUT
High-Z
H
X
Write to SRAM
H
L
H
X
X
L
SA
X
X
DIN
High-Z
H
X
Temporary
Sector Group
Unprotection *4
X
X
X
X
X
X
X
X
X
X
X
VID
X
Flash Hardware
Reset
X
H
X
X
L
X
X
X
X
X
X
High-Z
High-Z
L
X
X
X
L
Boot Block Sector
X
X
X
X
X
X
X
X
X
X
Write Protection
Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.
*1 : Other operations except for indicated this column are inhibited.
*2 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*3 : Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time.
*4 : It is also used for the extended sector group protections.
*5 : WP/ACC = VIL; protection of boot sectors.
WP/ACC = VIH; removal of boot sectors protection.
WP/ACC = VACC (9 V); Program time will reduce by 40%.
8
MB84VD2118XEM/2119XEM-70
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Symbol
Unit
Min
Max
Tstg
–55
+125
°C
TA
–40
+85
°C
Voltage with Respect to Ground All pins
except RESET, WP/ACC *1
VIN, VOUT
–0.3
VCCf +0.4
V
VCCs +0.4
V
VCCf/VCCs Supply *1
VCCf,VCCs
–0.3
+4.0
V
2
VIN
–0.5
+ 13.0
V
VIN
–0.5
+10.5
V
Storage Temperature
Ambient Temperature with Power Applied
RESET *
3
WP/ACC *
*1 : Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may undershoot
VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf+0.4 V or VCCs+0.4 V.
During voltage transitions, input or I/O pins may overshoot to VCCf+2.0 V or VCCs+2.0 V for periods of up to 20 ns.
*2 : Minimum DC input voltage on RESET pin is –0.5 V. During voltage transitions, RESET pins may undershoot
VSS to –2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCCf or VCCs)
does not exceed +9.0 V. Maximum DC input voltage on RESET pins is +13.0 V which may overshoot to +14.0 V
for periods of up to 20 ns.
*3 : Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may undershoot
Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may
overshoot to +12.0 V for periods of up to 20 ns, when VCCf is applied.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Ambient Temperature
VCCf/VCCs Supply Voltages
Symbol
Value
Unit
Min
Max
TA
–40
+85
°C
Vccf, Vccs
+2.7
+3.3
V
Note : Operating ranges define those limits between which the functionality of the device is guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
9
MB84VD2118XEM/2119XEM-70
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Parameter
Value
Test Conditions
Symbol
Min
Typ
Max
Unit
Input Leakage Current
ILI
VIN = VSS to VCCf, VCCs
–1.0
—
+1.0
µA
Output Leakage Current
ILO
VOUT = VSS to VCCf, VCCs
–1.0
—
+1.0
µA
RESET Inputs Leakage
Current
ILIT
VCCf = VCCf Max,VCCs = VCCs Max,
RESET = 12.5 V
—
—
35
µA
tCYCLE = 5 MHz Byte
—
—
13
tCYCLE = 5 MHz Word
—
—
15
tCYCLE = 1 MHz Byte
—
—
7
tCYCLE = 1 MHz Word
—
—
7
—
—
35
Byte
—
—
48
Word
—
—
50
Byte
—
—
48
Word
—
—
50
Flash VCC Active Current
(Read) *1
ICC1f
CEf = VIL,
OE = VIH
mA
mA
Flash VCC Active Current
(Program/Erase) *2
ICC2f
CEf = VIL, OE = VIH
Flash VCC Active Current
(Read-While-Program) *5
ICC3f
CEf = VIL, OE = VIH
Flash VCC Active Current
(Read-While-Erase) *5
ICC4f
CEf = VIL, OE = VIH
Flash VCC Active Current
(Erase-Suspend-Program)
ICC5f
CEf = VIL, OE = VIH
—
—
35
mA
ACC Input Leakage
Current
ILIA
VCCf = VCCf Max,VCCs = VCCs Max,
WP/ACC = VACC Max
—
—
20
mA
mA
mA
mA
SRAM VCC Active Current
ICC1s
VCCs = VCCs Max,
CE1s = VIL,
CE2s = VIH
tCYCLE =10 MHz
—
—
40
mA
SRAM VCC Active Current
ICC2s
tCYCLE = 10 MHz
CE1s = 0.2 V,
CE2s = VCCs – 0.2 V tCYCLE = 1 MHz
—
—
40
mA
—
—
8
mA
Flash VCC Standby Current
ISB1f
VCCf = VCCf Max, CEf = VCCf ± 0.3 V,
RESET = VCCf ± 0.3 V,
WP/ACC = VCCf ± 0.3 V
—
1
5
µA
Flash VCC Standby Current
(RESET)
ISB2f
VCCf = VCCf Max, RESET = VSS ± 0.3 V,
WP/ACC = VCCf ± 0.3 V
—
1
5
µA
Flash VCC Current
(Automatic Sleep Mode) *3
ISB3f
VCCf = VCCf Max, CEf = VSS ± 0.3 V,
RESET = VCCf ± 0.3 V,
WP/ACC = VCCf ± 0.3 V,
VIN = VCCf ± 0.3 V or VSS ± 0.3 V
—
1
5
µA
SRAM VCC Standby
Current
ISB1s
CE1s > VCCs – 0.2 V, CE2s > VCCs – 0.2 V,
LB = UB > VCCs–0.2 V or < 0.2 V
—
—
10
µA
SRAM VCC Standby
Current
ISB2s
CE1s > VCCs – 0.2 V or < 0.2 V,
CE2s < 0.2 V,
LB = UB > VCCs – 0.2 V or < 0.2 V
—
—
10
µA
(Continued)
10
MB84VD2118XEM/2119XEM-70
(Continued)
Parameter
Symbol
Test Conditions
Input Low Level
VIL
Input High Level
Value
Unit
Min
Typ
Max
—
–0.3
—
0.5
V
VIH
—
2.4
—
VCC+0.3
V
Voltage for Sector
Protection, and Temporary
Sector Unprotection
(RESET) *4
VID
—
11.5
—
12.5
V
Voltage for Program
Acceleration (WP/ACC) *4
VACC
—
8.5
9.0
9.5
V
SRAM Output Low Level
VOL
VCCs = VCCs Min, IOL=4.0 mA
—
—
0.45
V
SRAM Output High Level
VOH
VCCs = VCCs Min, IOH=–0.5 mA
2.4
—
—
V
Flash Output Low Level
VOL
VCCf = VCCf Min, IOL=4.0 mA
—
—
0.4
V
Flash Output High Level
VOH
VCCf = VCCf Min, IOH=–0.5 mA
2.4
—
—
V
Flash Low VCCf Lock-Out
Voltage
VLKO
2.3
—
2.5
V
—
* 1 : The ICC current listed includes both the DC operating current and the frequency dependent component.
*2 : ICC active while Embedded Algorithm (program or erase) is in progress.
*3 : Automatic sleep mode enables the low power mode when address remain stable for 150 ns.
*4 : Applicable for only VCCf applying.
*5 : Embedded Alogorithm (program or erase) is in progress. (@5 MHz)
11
MB84VD2118XEM/2119XEM-70
2. AC Characteristics
• CE Timing
Symbol
JEDEC
Standard
Test
Setup
—
tCCR
—
Parameter
CE Recover Time
Value
Unit
• Timing Diagram for alternating SRAM to Flash
CEf
tCCR
tCCR
tCCR
tCCR
CE1s
CE2s
• Flash Characteristics
Please refer to “■16M FLASH MEMORY CHARACTERISTICS for MCP“ part.
• SRAM Characteristics,
Please refer to “■4M SRAM CHARACTERISTICS for MCP“ part.
12
Min
Max
0
—
ns
MB84VD2118XEM/2119XEM-70
■ 16M FLASH MEMORY CHARACTERISTICS for MCP
1. Flexible Sector-erase Architecture on Flash Memory
• Eight 4 K words, and thirty one 32 K words.
• Individual-sector, multiple-sector, or bulk-erase capability.
Bank size 4
Bank size 3
Bank size 2
Bank size 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 2
Bank 2
Bank 2
Bank 2
SA38 : 8KB (4KW)
SA37 : 8KB (4KW)
SA36 : 8KB (4KW)
SA35 : 8KB (4KW)
SA34 : 8KB (4KW)
SA33 : 8KB (4KW)
SA32 : 8KB (4KW)
SA31 : 8KB (4KW)
SA30 : 64KB (32KW)
SA29 : 64KB (32KW)
SA28 : 64KB (32KW)
SA27 : 64KB (32KW)
SA26 : 64KB (32KW)
SA25 : 64KB (32KW)
SA24 : 64KB (32KW)
SA23 : 64KB (32KW)
SA22 : 64KB (32KW)
SA21 : 64KB (32KW)
SA20 : 64KB (32KW)
SA19 : 64KB (32KW)
SA18 : 64KB (32KW)
SA17 : 64KB (32KW)
SA16 : 64KB (32KW)
SA15 : 64KB (32KW)
SA14 : 64KB (32KW)
SA13 : 64KB (32KW)
SA12 : 64KB (32KW)
SA11 : 64KB (32KW)
SA10 : 64KB (32KW)
SA9 : 64KB (32KW)
SA8 : 64KB (32KW)
SA7 : 64KB (32KW)
SA6 : 64KB (32KW)
SA5 : 64KB (32KW)
SA4 : 64KB (32KW)
SA3 : 64KB (32KW)
SA2 : 64KB (32KW)
SA1 : 64KB (32KW)
SA0 : 64KB (32KW)
Word mode
Byte mode
0FFFFFh
0FF000h
0FE000h
0FD000h
0FC000h
0FB000h
0FA000h
0F9000h
0F8000h
0F0000h
0E8000h
0E0000h
0D8000h
0D0000h
0C8000h
0C0000h
0B8000h
0B0000h
0A8000h
0A0000h
098000h
090000h
088000h
080000h
078000h
070000h
068000h
060000h
058000h
050000h
048000h
040000h
038000h
030000h
028000h
020000h
018000h
010000h
008000h
000000h
1FFFFFh
1FE000h
1FC000h
1FA000h
1F8000h
1F6000h
1F4000h
1F2000h
1F0000h
1E0000h
1D0000h
1C0000h
1B0000h
1A0000h
190000h
180000h
170000h
160000h
150000h
140000h
130000h
120000h
110000h
100000h
0F0000h
0E0000h
0D0000h
0C0000h
0B0000h
0A0000h
090000h
080000h
070000h
060000h
050000h
040000h
030000h
020000h
010000h
000000h
Sector Architecture (Top Boot Block)
(Continued)
13
MB84VD2118XEM/2119XEM-70
(Continued)
Bank size 4
Bank size 3
Bank size 2
Bank size 1
Bank 2
Bank 2
Bank 2
Bank 2
Bank 1
Bank 1
Bank 1
Bank 1
SA38 : 64KB (32KW)
SA37 : 64KB (32KW)
SA36 : 64KB (32KW)
SA35 : 64KB (32KW)
SA34 : 64KB (32KW)
SA33 : 64KB (32KW)
SA32 : 64KB (32KW)
SA31 : 64KB (32KW)
SA30 : 64KB (32KW)
SA29 : 64KB (32KW)
SA28 : 64KB (32KW)
SA27 : 64KB (32KW)
SA26 : 64KB (32KW)
SA25 : 64KB (32KW)
SA24 : 64KB (32KW)
SA23 : 64KB (32KW)
SA22 : 64KB (32KW)
SA21 : 64KB (32KW)
SA20 : 64KB (32KW)
SA19 : 64KB (32KW)
SA18 : 64KB (32KW)
SA17 : 64KB (32KW)
SA16 : 64KB (32KW)
SA15 : 64KB (32KW)
SA14 : 64KB (32KW)
SA13 : 64KB (32KW)
SA12 : 64KB (32KW)
SA11 : 64KB (32KW)
SA10 : 64KB (32KW)
SA9 : 64KB (32KW)
SA8 : 64KB (32KW)
SA7 : 8KB (4KW)
SA6 : 8KB (4KW)
SA5 : 8KB (4KW)
SA4 : 8KB (4KW)
SA3 : 8KB (4KW)
SA2 : 8KB (4KW)
SA1 : 8KB (4KW)
SA0 : 8KB (4KW)
Sector Architecture (Bottom Boot Block)
14
Word mode
0FFFFFh
0F8000h
0F0000h
0E8000h
0E0000h
0D8000h
0D0000h
0C8000h
0C0000h
0B8000h
0B0000h
0A8000h
0A0000h
098000h
090000h
088000h
080000h
078000h
070000h
068000h
060000h
058000h
050000h
048000h
040000h
038000h
030000h
028000h
020000h
018000h
010000h
008000h
007000h
006000h
005000h
004000h
003000h
002000h
001000h
000000h
Byte mode
1FFFFFh
1F0000h
1E0000h
1D0000h
1C0000h
1B0000h
1A0000h
190000h
180000h
170000h
160000h
150000h
140000h
130000h
120000h
110000h
100000h
0F0000h
0E0000h
0D0000h
0C0000h
0B0000h
0A0000h
090000h
080000h
070000h
060000h
050000h
040000h
030000h
020000h
010000h
00E000h
00C000h
00A000h
008000h
006000h
004000h
002000h
000000h
MB84VD2118XEM/2119XEM-70
Sector Address Table (Top Boot Block, Bank Size=1)
Sector Address
Bank
Bank 2
Bank 1
Sector
Bank Address
Address Range
(Byte mode)
Address Range
(Word mode)
A19
A18
A17
A16
A15
A14
A13
A12
SA0
0
0
0
0
0
X
X
X
000000h to 00FFFFh
000000h to 007FFFh
SA1
0
0
0
0
1
X
X
X
010000h to 01FFFFh
008000h to 00FFFFh
SA2
0
0
0
1
0
X
X
X
020000h to 02FFFFh
010000h to 017FFFh
SA3
0
0
0
1
1
X
X
X
030000h to 03FFFFh
018000h to 01FFFFh
SA4
0
0
1
0
0
X
X
X
040000h to 04FFFFh
020000h to 027FFFh
SA5
0
0
1
0
1
X
X
X
050000h to 05FFFFh
028000h to 02FFFFh
SA6
0
0
1
1
0
X
X
X
060000h to 06FFFFh
030000h to 037FFFh
SA7
0
0
1
1
1
X
X
X
070000h to 07FFFFh
038000h to 03FFFFh
SA8
0
1
0
0
0
X
X
X
080000h to 08FFFFh
040000h to 047FFFh
SA9
0
1
0
0
1
X
X
X
090000h to 09FFFFh
048000h to 04FFFFh
SA10
0
1
0
1
0
X
X
X
0A0000h to 0AFFFFh
050000h to 057FFFh
SA11
0
1
0
1
1
X
X
X
0B0000h to 0BFFFFh
058000h to 05FFFFh
SA12
0
1
1
0
0
X
X
X
0C0000h to 0CFFFFh
060000h to 067FFFh
SA13
0
1
1
0
1
X
X
X
0D0000h to 0DFFFFh 068000h to 06FFFFh
SA14
0
1
1
1
0
X
X
X
0E0000h to 0EFFFFh
070000h to 077FFFh
SA15
0
1
1
1
1
X
X
X
0F0000h to 0FFFFFh
078000h to 07FFFFh
SA16
1
0
0
0
0
X
X
X
100000h to 10FFFFh
080000h to 087FFFh
SA17
1
0
0
0
1
X
X
X
110000h to 11FFFFh
088000h to 08FFFFh
SA18
1
0
0
1
0
X
X
X
120000h to 12FFFFh
090000h to 097FFFh
SA19
1
0
0
1
1
X
X
X
130000h to 13FFFFh
098000h to 09FFFFh
SA20
1
0
1
0
0
X
X
X
140000h to 14FFFFh
0A0000h to 0A7FFFh
SA21
1
0
1
0
1
X
X
X
150000h to 15FFFFh
0A8000h to 0AFFFFh
SA22
1
0
1
1
0
X
X
X
160000h to 16FFFFh
0B0000h to 0B7FFFh
SA23
1
0
1
1
1
X
X
X
170000h to 17FFFFh
0B8000h to 0BFFFFh
SA24
1
1
0
0
0
X
X
X
180000h to 18FFFFh
0C0000h to 0C7FFFh
SA25
1
1
0
0
1
X
X
X
190000h to 19FFFFh 0C8000h to 0CFFFFh
SA26
1
1
0
1
0
X
X
X
1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
SA27
1
1
0
1
1
X
X
X
1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
SA28
1
1
1
0
0
X
X
X
1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
SA29
1
1
1
0
1
X
X
X
1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
SA30
1
1
1
1
0
X
X
X
1E0000h to 1EFFFFh
0F0000h to 0F7FFFh
SA31
1
1
1
1
1
0
0
0
1F0000h to 1F1FFFh
0F8000h to 0F8FFFh
SA32
1
1
1
1
1
0
0
1
1F2000h to 1F3FFFh
0F9000h to 0F9FFFh
SA33
1
1
1
1
1
0
1
0
1F4000h to 1F5FFFh 0FA000h to 0FAFFFh
SA34
1
1
1
1
1
0
1
1
1F6000h to 1F7FFFh 0FB000h to 0FBFFFh
SA35
1
1
1
1
1
1
0
0
1F8000h to 1F9FFFh 0FC000h to 0FCFFFh
SA36
1
1
1
1
1
1
0
1
1FA000h to 1FBFFFh 0FD000h to 0FDFFFh
SA37
1
1
1
1
1
1
1
0
1FC000h to 1FDFFFh 0FE000h to 0FEFFFh
SA38
1
1
1
1
1
1
1
1
1FE000h to 1FFFFFh 0FF000h to 0FFFFFh
15
MB84VD2118XEM/2119XEM-70
Sector Address Table (Bottom Boot Block, Bank Size=1)
Sector Address
Bank
Bank 1
Bank 2
16
Sector
Bank Address
Address Range
(BYTE mode)
Address Range
(WORD mode)
A19
A18
A17
A16
A15
A14
A13
A12
SA0
0
0
0
0
0
0
0
0
000000h to 001FFFh
000000h to 000FFFh
SA1
0
0
0
0
0
0
0
1
002000h to 003FFFh
001000h to 001FFFh
SA2
0
0
0
0
0
0
1
0
004000h to 005FFFh
002000h to 002FFFh
SA3
0
0
0
0
0
0
1
1
006000h to 007FFFh
003000h to 003FFFh
SA4
0
0
0
0
0
1
0
0
008000h to 009FFFh
004000h to 004FFFh
SA5
0
0
0
0
0
1
0
1
00A000h to 00BFFFh
005000h to 005FFFh
SA6
0
0
0
0
0
1
1
0
00C000h to 00DFFFh
006000h to 006FFFh
SA7
0
0
0
0
0
1
1
1
00E000h to 00FFFFh
007000h to 007FFFh
SA8
0
0
0
0
1
X
X
X
010000h to 01FFFFh
008000h to 00FFFFh
SA9
0
0
0
1
0
X
X
X
020000h to 02FFFFh
010000h to 017FFFh
SA10
0
0
0
1
1
X
X
X
030000h to 03FFFFh
018000h to 01FFFFh
SA11
0
0
1
0
0
X
X
X
040000h to 04FFFFh
020000h to 027FFFh
SA12
0
0
1
0
1
X
X
X
050000h to 05FFFFh
028000h to 02FFFFh
SA13
0
0
1
1
0
X
X
X
060000h to 06FFFFh
030000h to 037FFFh
SA14
0
0
1
1
1
X
X
X
070000h to 07FFFFh
038000h to 03FFFFh
SA15
0
1
0
0
0
X
X
X
080000h to 08FFFFh
040000h to 047FFFh
SA16
0
1
0
0
1
X
X
X
090000h to 09FFFFh
048000h to 04FFFFh
SA17
0
1
0
1
0
X
X
X
0A0000h to 0AFFFFh
050000h to 057FFFh
SA18
0
1
0
1
1
X
X
X
0B0000h to 0BFFFFh
058000h to 05FFFFh
SA19
0
1
1
0
0
X
X
X
0C0000h to 0CFFFFh
060000h to 067FFFh
SA20
0
1
1
0
1
X
X
X
0D0000h to 0DFFFFh 068000h to 06FFFFh
SA21
0
1
1
1
0
X
X
X
0E0000h to 0EFFFFh
070000h to 077FFFh
SA22
0
1
1
1
1
X
X
X
0F0000h to 0FFFFFh
078000h to 07FFFFh
SA23
1
0
0
0
0
X
X
X
100000h to 10FFFFh
080000h to 087FFFh
SA24
1
0
0
0
1
X
X
X
110000h to 11FFFFh
088000h to 08FFFFh
SA25
1
0
0
1
0
X
X
X
120000h to 12FFFFh
090000h to 097FFFh
SA26
1
0
0
1
1
X
X
X
130000h to 13FFFFh
098000h to 09FFFFh
SA27
1
0
1
0
0
X
X
X
140000h to 14FFFFh
0A0000h to 0A7FFFh
SA28
1
0
1
0
1
X
X
X
150000h to 15FFFFh
0A8000h to 0AFFFFh
SA29
1
0
1
1
0
X
X
X
160000h to 16FFFFh
0B0000h to 0B7FFFh
SA30
1
0
1
1
1
X
X
X
170000h to 17FFFFh
0B8000h to 0BFFFFh
SA31
1
1
0
0
0
X
X
X
180000h to 18FFFFh
0C0000h to 0C7FFFh
SA32
1
1
0
0
1
X
X
X
190000h to 19FFFFh 0C8000h to 0CFFFFh
SA33
1
1
0
1
0
X
X
X
1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
SA34
1
1
0
1
1
X
X
X
1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
SA35
1
1
1
0
0
X
X
X
1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
SA36
1
1
1
0
1
X
X
X
1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
SA37
1
1
1
1
0
X
X
X
1E0000h to 1EFFFFh
0F0000h to 0F7FFFh
SA38
1
1
1
1
1
X
X
X
1F0000h to 1FFFFFh
0F8000h to 0FFFFFh
MB84VD2118XEM/2119XEM-70
Sector Address Table (Top Boot Block, Bank Size=2)
Sector Address
Bank
Bank 2
Bank 1
Sector
Bank Address
Address Range
(BYTE mode)
Address Range
(WORD mode)
A19
A18
A17
A16
A15
A14
A13
A12
SA0
0
0
0
0
0
X
X
X
000000h to 00FFFFh
000000h to 007FFFh
SA1
0
0
0
0
1
X
X
X
010000h to 01FFFFh
008000h to 00FFFFh
SA2
0
0
0
1
0
X
X
X
020000h to 02FFFFh
010000h to 017FFFh
SA3
0
0
0
1
1
X
X
X
030000h to 03FFFFh
018000h to 01FFFFh
SA4
0
0
1
0
0
X
X
X
040000h to 04FFFFh
020000h to 027FFFh
SA5
0
0
1
0
1
X
X
X
050000h to 05FFFFh
028000h to 02FFFFh
SA6
0
0
1
1
0
X
X
X
060000h to 06FFFFh
030000h to 037FFFh
SA7
0
0
1
1
1
X
X
X
070000h to 07FFFFh
038000h to 03FFFFh
SA8
0
1
0
0
0
X
X
X
080000h to 08FFFFh
040000h to 047FFFh
SA9
0
1
0
0
1
X
X
X
090000h to 09FFFFh
048000h to 04FFFFh
SA10
0
1
0
1
0
X
X
X
0A0000h to 0AFFFFh
050000h to 057FFFh
SA11
0
1
0
1
1
X
X
X
0B0000h to 0BFFFFh
058000h to 05FFFFh
SA12
0
1
1
0
0
X
X
X
0C0000h to 0CFFFFh 060000h to 067FFFh
SA13
0
1
1
0
1
X
X
X
0D0000h to 0DFFFFh 068000h to 06FFFFh
SA14
0
1
1
1
0
X
X
X
0E0000h to 0EFFFFh
070000h to 077FFFh
SA15
0
1
1
1
1
X
X
X
0F0000h to 0FFFFFh
078000h to 07FFFFh
SA16
1
0
0
0
0
X
X
X
100000h to 10FFFFh
080000h to 087FFFh
SA17
1
0
0
0
1
X
X
X
110000h to 11FFFFh
088000h to 08FFFFh
SA18
1
0
0
1
0
X
X
X
120000h to 12FFFFh
090000h to 097FFFh
SA19
1
0
0
1
1
X
X
X
130000h to 13FFFFh
098000h to 09FFFFh
SA20
1
0
1
0
0
X
X
X
140000h to 14FFFFh
0A0000h to 0A7FFFh
SA21
1
0
1
0
1
X
X
X
150000h to 15FFFFh
0A8000h to 0AFFFFh
SA22
1
0
1
1
0
X
X
X
160000h to 16FFFFh
0B0000h to 0B7FFFh
SA23
1
0
1
1
1
X
X
X
170000h to 17FFFFh
0B8000h to 0BFFFFh
SA24
1
1
0
0
0
X
X
X
180000h to 18FFFFh 0C0000h to 0C7FFFh
SA25
1
1
0
0
1
X
X
X
190000h to 19FFFFh 0C8000h to 0CFFFFh
SA26
1
1
0
1
0
X
X
X
1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
SA27
1
1
0
1
1
X
X
X
1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
SA28
1
1
1
0
0
X
X
X
1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
SA29
1
1
1
0
1
X
X
X
1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
SA30
1
1
1
1
0
X
X
X
1E0000h to 1EFFFFh 0F0000h to 0F7FFFh
SA31
1
1
1
1
1
0
0
0
1F0000h to 1F1FFFh
0F8000h to 0F8FFFh
SA32
1
1
1
1
1
0
0
1
1F2000h to 1F3FFFh
0F9000h to 0F9FFFh
SA33
1
1
1
1
1
0
1
0
1F4000h to 1F5FFFh 0FA000h to 0FAFFFh
SA34
1
1
1
1
1
0
1
1
1F6000h to 1F7FFFh 0FB000h to 0FBFFFh
SA35
1
1
1
1
1
1
0
0
1F8000h to 1F9FFFh 0FC000h to 0FCFFFh
SA36
1
1
1
1
1
1
0
1
1FA000h to 1FBFFFh 0FD000h to 0FDFFFh
SA37
1
1
1
1
1
1
1
0
1FC000h to 1FDFFFh 0FE000h to 0FEFFFh
SA38
1
1
1
1
1
1
1
1
1FE000h to 1FFFFFh 0FF000h to 0FFFFFh
17
MB84VD2118XEM/2119XEM-70
Sector Address Table (Bottom Boot Block, Bank Size=2)
Sector Address
Bank
Bank 1
Bank 2
18
Sector
Bank Address
Address Range
(BYTE mode)
Address Range
(WORD mode)
A19
A18
A17
A16
A15
A14
A13
A12
SA0
0
0
0
0
0
0
0
0
000000h to 001FFFh
000000h to 000FFFh
SA1
0
0
0
0
0
0
0
1
002000h to 003FFFh
001000h to 001FFFh
SA2
0
0
0
0
0
0
1
0
004000h to 005FFFh
002000h to 002FFFh
SA3
0
0
0
0
0
0
1
1
006000h to 007FFFh
003000h to 003FFFh
SA4
0
0
0
0
0
1
0
0
008000h to 009FFFh
004000h to 004FFFh
SA5
0
0
0
0
0
1
0
1
00A000h to 00BFFFh
005000h to 005FFFh
SA6
0
0
0
0
0
1
1
0
00C000h to 00DFFFh
006000h to 006FFFh
SA7
0
0
0
0
0
1
1
1
00E000h to 00FFFFh
007000h to 007FFFh
SA8
0
0
0
0
1
X
X
X
010000h to 01FFFFh
008000h to 00FFFFh
SA9
0
0
0
1
0
X
X
X
020000h to 02FFFFh
010000h to 017FFFh
SA10
0
0
0
1
1
X
X
X
030000h to 03FFFFh
018000h to 01FFFFh
SA11
0
0
1
0
0
X
X
X
040000h to 04FFFFh
020000h to 027FFFh
SA12
0
0
1
0
1
X
X
X
050000h to 05FFFFh
028000h to 02FFFFh
SA13
0
0
1
1
0
X
X
X
060000h to 06FFFFh
030000h to 037FFFh
SA14
0
0
1
1
1
X
X
X
070000h to 07FFFFh
038000h to 03FFFFh
SA15
0
1
0
0
0
X
X
X
080000h to 08FFFFh
040000h to 047FFFh
SA16
0
1
0
0
1
X
X
X
090000h to 09FFFFh
048000h to 04FFFFh
SA17
0
1
0
1
0
X
X
X
0A0000h to 0AFFFFh
050000h to 057FFFh
SA18
0
1
0
1
1
X
X
X
0B0000h to 0BFFFFh
058000h to 05FFFFh
SA19
0
1
1
0
0
X
X
X
0C0000h to 0CFFFFh 060000h to 067FFFh
SA20
0
1
1
0
1
X
X
X
0D0000h to 0DFFFFh 068000h to 06FFFFh
SA21
0
1
1
1
0
X
X
X
0E0000h to 0EFFFFh
070000h to 077FFFh
SA22
0
1
1
1
1
X
X
X
0F0000h to 0FFFFFh
078000h to 07FFFFh
SA23
1
0
0
0
0
X
X
X
100000h to 10FFFFh
080000h to 087FFFh
SA24
1
0
0
0
1
X
X
X
110000h to 11FFFFh
088000h to 08FFFFh
SA25
1
0
0
1
0
X
X
X
120000h to 12FFFFh
090000h to 097FFFh
SA26
1
0
0
1
1
X
X
X
130000h to 13FFFFh
098000h to 09FFFFh
SA27
1
0
1
0
0
X
X
X
140000h to 14FFFFh
0A0000h to 0A7FFFh
SA28
1
0
1
0
1
X
X
X
150000h to 15FFFFh
0A8000h to 0AFFFFh
SA29
1
0
1
1
0
X
X
X
160000h to 16FFFFh
0B0000h to 0B7FFFh
SA30
1
0
1
1
1
X
X
X
170000h to 17FFFFh
0B8000h to 0BFFFFh
SA31
1
1
0
0
0
X
X
X
180000h to 18FFFFh 0C0000h to 0C7FFFh
SA32
1
1
0
0
1
X
X
X
190000h to 19FFFFh 0C8000h to 0CFFFFh
SA33
1
1
0
1
0
X
X
X
1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
SA34
1
1
0
1
1
X
X
X
1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
SA35
1
1
1
0
0
X
X
X
1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
SA36
1
1
1
0
1
X
X
X
1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
SA37
1
1
1
1
0
X
X
X
1E0000h to 1EFFFFh 0F0000h to 0F7FFFh
SA38
1
1
1
1
1
X
X
X
1F0000h to 1FFFFFh
0F8000h to 0FFFFFh
MB84VD2118XEM/2119XEM-70
Sector Address Table (Top Boot Block, Bank Size=3)
Sector Address
Bank
Bank 2
Bank 1
Sector
Bank Address
Address Range
(BYTE mode)
Address Range
(WORD mode)
A19
A18
A17
A16
A15
A14
A13
A12
SA0
0
0
0
0
0
X
X
X
000000h to 00FFFFh
000000h to 007FFFh
SA1
0
0
0
0
1
X
X
X
010000h to 01FFFFh
008000h to 00FFFFh
SA2
0
0
0
1
0
X
X
X
020000h to 02FFFFh
010000h to 017FFFh
SA3
0
0
0
1
1
X
X
X
030000h to 03FFFFh
018000h to 01FFFFh
SA4
0
0
1
0
0
X
X
X
040000h to 04FFFFh
020000h to 027FFFh
SA5
0
0
1
0
1
X
X
X
050000h to 05FFFFh
028000h to 02FFFFh
SA6
0
0
1
1
0
X
X
X
060000h to 06FFFFh
030000h to 037FFFh
SA7
0
0
1
1
1
X
X
X
070000h to 07FFFFh
038000h to 03FFFFh
SA8
0
1
0
0
0
X
X
X
080000h to 08FFFFh
040000h to 047FFFh
SA9
0
1
0
0
1
X
X
X
090000h to 09FFFFh
048000h to 04FFFFh
SA10
0
1
0
1
0
X
X
X
0A0000h to 0AFFFFh
050000h to 057FFFh
SA11
0
1
0
1
1
X
X
X
0B0000h to 0BFFFFh
058000h to 05FFFFh
SA12
0
1
1
0
0
X
X
X
0C0000h to 0CFFFFh 060000h to 067FFFh
SA13
0
1
1
0
1
X
X
X
0D0000h to 0DFFFFh 068000h to 06FFFFh
SA14
0
1
1
1
0
X
X
X
0E0000h to 0EFFFFh
070000h to 077FFFh
SA15
0
1
1
1
1
X
X
X
0F0000h to 0FFFFFh
078000h to 07FFFFh
SA16
1
0
0
0
0
X
X
X
100000h to 10FFFFh
080000h to 087FFFh
SA17
1
0
0
0
1
X
X
X
110000h to 11FFFFh
088000h to 08FFFFh
SA18
1
0
0
1
0
X
X
X
120000h to 12FFFFh
090000h to 097FFFh
SA19
1
0
0
1
1
X
X
X
130000h to 13FFFFh
098000h to 09FFFFh
SA20
1
0
1
0
0
X
X
X
140000h to 14FFFFh
0A0000h to 0A7FFFh
SA21
1
0
1
0
1
X
X
X
150000h to 15FFFFh
0A8000h to 0AFFFFh
SA22
1
0
1
1
0
X
X
X
160000h to 16FFFFh
0B0000h to 0B7FFFh
SA23
1
0
1
1
1
X
X
X
170000h to 17FFFFh
0B8000h to 0BFFFFh
SA24
1
1
0
0
0
X
X
X
180000h to 18FFFFh 0C0000h to 0C7FFFh
SA25
1
1
0
0
1
X
X
X
190000h to 19FFFFh 0C8000h to 0CFFFFh
SA26
1
1
0
1
0
X
X
X
1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
SA27
1
1
0
1
1
X
X
X
1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
SA28
1
1
1
0
0
X
X
X
1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
SA29
1
1
1
0
1
X
X
X
1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
SA30
1
1
1
1
0
X
X
X
1E0000h to 1EFFFFh 0F0000h to 0F7FFFh
SA31
1
1
1
1
1
0
0
0
1F0000h to 1F1FFFh
0F8000h to 0F8FFFh
SA32
1
1
1
1
1
0
0
1
1F2000h to 1F3FFFh
0F9000h to 0F9FFFh
SA33
1
1
1
1
1
0
1
0
1F4000h to 1F5FFFh 0FA000h to 0FAFFFh
SA34
1
1
1
1
1
0
1
1
1F6000h to 1F7FFFh 0FB000h to 0FBFFFh
SA35
1
1
1
1
1
1
0
0
1F8000h to 1F9FFFh 0FC000h to 0FCFFFh
SA36
1
1
1
1
1
1
0
1
1FA000h to 1FBFFFh 0FD000h to 0FDFFFh
SA37
1
1
1
1
1
1
1
0
1FC000h to 1FDFFFh 0FE000h to 0FEFFFh
SA38
1
1
1
1
1
1
1
1
1FE000h to 1FFFFFh 0FF000h to 0FFFFFh
19
MB84VD2118XEM/2119XEM-70
Sector Address Table (Bottom Boot Block, Bank Size=3)
Sector Address
Bank
Bank 1
Bank 2
20
Sector
Bank Address
Address Range
(BYTE mode)
Address Range
(WORD mode)
A19
A18
A17
A16
A15
A14
A13
A12
SA0
0
0
0
0
0
0
0
0
000000h to 001FFFh
000000h to 000FFFh
SA1
0
0
0
0
0
0
0
1
002000h to 003FFFh
001000h to 001FFFh
SA2
0
0
0
0
0
0
1
0
004000h to 005FFFh
002000h to 002FFFh
SA3
0
0
0
0
0
0
1
1
006000h to 007FFFh
003000h to 003FFFh
SA4
0
0
0
0
0
1
0
0
008000h to 009FFFh
004000h to 004FFFh
SA5
0
0
0
0
0
1
0
1
00A000h to 00BFFFh
005000h to 005FFFh
SA6
0
0
0
0
0
1
1
0
00C000h to 00DFFFh
006000h to 006FFFh
SA7
0
0
0
0
0
1
1
1
00E000h to 00FFFFh
007000h to 007FFFh
SA8
0
0
0
0
1
X
X
X
010000h to 01FFFFh
008000h to 00FFFFh
SA9
0
0
0
1
0
X
X
X
020000h to 02FFFFh
010000h to 017FFFh
SA10
0
0
0
1
1
X
X
X
030000h to 03FFFFh
018000h to 01FFFFh
SA11
0
0
1
0
0
X
X
X
040000h to 04FFFFh
020000h to 027FFFh
SA12
0
0
1
0
1
X
X
X
050000h to 05FFFFh
028000h to 02FFFFh
SA13
0
0
1
1
0
X
X
X
060000h to 06FFFFh
030000h to 037FFFh
SA14
0
0
1
1
1
X
X
X
070000h to 07FFFFh
038000h to 03FFFFh
SA15
0
1
0
0
0
X
X
X
080000h to 08FFFFh
040000h to 047FFFh
SA16
0
1
0
0
1
X
X
X
090000h to 09FFFFh
048000h to 04FFFFh
SA17
0
1
0
1
0
X
X
X
0A0000h to 0AFFFFh
050000h to 057FFFh
SA18
0
1
0
1
1
X
X
X
0B0000h to 0BFFFFh
058000h to 05FFFFh
SA19
0
1
1
0
0
X
X
X
0C0000h to 0CFFFFh
060000h to 067FFFh
SA20
0
1
1
0
1
X
X
X
0D0000h to 0DFFFFh
068000h to 06FFFFh
SA21
0
1
1
1
0
X
X
X
0E0000h to 0EFFFFh
070000h to 077FFFh
SA22
0
1
1
1
1
X
X
X
0F0000h to 0FFFFFh
078000h to 07FFFFh
SA23
1
0
0
0
0
X
X
X
100000h to 10FFFFh
080000h to 087FFFh
SA24
1
0
0
0
1
X
X
X
110000h to 11FFFFh
088000h to 08FFFFh
SA25
1
0
0
1
0
X
X
X
120000h to 12FFFFhh
090000h to 097FFFh
SA26
1
0
0
1
1
X
X
X
130000h to 13FFFFh
098000h to 09FFFFh
SA27
1
0
1
0
0
X
X
X
140000h to 14FFFFh
0A0000h to 0A7FFFh
SA28
1
0
1
0
1
X
X
X
150000h to 15FFFFh
0A8000h to 0AFFFFh
SA29
1
0
1
1
0
X
X
X
160000h to 16FFFFh
0B0000h to 0B7FFFh
SA30
1
0
1
1
1
X
X
X
170000h to 17FFFFh
0B8000h to 0BFFFFh
SA31
1
1
0
0
0
X
X
X
180000h to 18FFFFh
0C0000h to 0C7FFFh
SA32
1
1
0
0
1
X
X
X
190000h to 19FFFFh
0C8000h to 0CFFFFh
SA33
1
1
0
1
0
X
X
X
1A0000h to 1AFFFFh
0D0000h to 0D7FFFh
SA34
1
1
0
1
1
X
X
X
1B0000h to 1BFFFFh
0D8000h to 0DFFFFh
SA35
1
1
1
0
0
X
X
X
1C0000h to 1CFFFFh
0E0000h to 0E7FFFh
SA36
1
1
1
0
1
X
X
X
1D0000h to 1DFFFFh
0E8000h to 0EFFFFh
SA37
1
1
1
1
0
X
X
X
1E0000h to 1EFFFFh
0F0000h to 0F7FFFh
SA38
1
1
1
1
1
X
X
X
1F0000h to 1FFFFFh
0F8000h to 0FFFFFh
MB84VD2118XEM/2119XEM-70
Sector Address Table (Top Boot Block, Bank Size=4)
Sector Address
Bank
Bank 2
Bank 1
Sector
Bank Address
Address Range
(BYTE mode)
Address Range
(WORD mode)
A19
A18
A17
A16
A15
A14
A13
A12
SA0
0
0
0
0
0
X
X
X
000000h to 00FFFFh
000000h to 007FFFh
SA1
0
0
0
0
1
X
X
X
010000h to 01FFFFh
008000h to 00FFFFh
SA2
0
0
0
1
0
X
X
X
020000h to 02FFFFh
010000h to 017FFFh
SA3
0
0
0
1
1
X
X
X
030000h to 03FFFFh
018000h to 01FFFFh
SA4
0
0
1
0
0
X
X
X
040000h to 04FFFFh
020000h to 027FFFh
SA5
0
0
1
0
1
X
X
X
050000h to 05FFFFh
028000h to 02FFFFh
SA6
0
0
1
1
0
X
X
X
060000h to 06FFFFh
030000h to 037FFFh
SA7
0
0
1
1
1
X
X
X
070000h to 07FFFFh
038000h to 03FFFFh
SA8
0
1
0
0
0
X
X
X
080000h to 08FFFFh
040000h to 047FFFh
SA9
0
1
0
0
1
X
X
X
090000h to 09FFFFh
048000h to 04FFFFh
SA10
0
1
0
1
0
X
X
X
0A0000h to 0AFFFFh
050000h to 057FFFh
SA11
0
1
0
1
1
X
X
X
0B0000h to 0BFFFFh
058000h to 05FFFFh
SA12
0
1
1
0
0
X
X
X
0C0000h to 0CFFFFh
060000h to 067FFFh
SA13
0
1
1
0
1
X
X
X
0D0000h to 0DFFFFh
068000h to 06FFFFh
SA14
0
1
1
1
0
X
X
X
0E0000h to 0EFFFFh
070000h to 077FFFh
SA15
0
1
1
1
1
X
X
X
0F0000h to 0FFFFFh
078000h to 07FFFFh
SA16
1
0
0
0
0
X
X
X
100000h to 10FFFFh
080000h to 087FFFh
SA17
1
0
0
0
1
X
X
X
110000h to 11FFFFh
088000h to 08FFFFh
SA18
1
0
0
1
0
X
X
X
120000h to 12FFFFh
090000h to 097FFFh
SA19
1
0
0
1
1
X
X
X
130000h to 13FFFFh
098000h to 09FFFFh
SA20
1
0
1
0
0
X
X
X
140000h to 14FFFFh
0A0000h to 0A7FFFh
SA21
1
0
1
0
1
X
X
X
150000h to 15FFFFh
0A8000h to 0AFFFFh
SA22
1
0
1
1
0
X
X
X
160000h to 16FFFFh
0B0000h to 0B7FFFh
SA23
1
0
1
1
1
X
X
X
170000h to 17FFFFh
0B8000h to 0BFFFFh
SA24
1
1
0
0
0
X
X
X
180000h to 18FFFFh
0C0000h to 0C7FFFh
SA25
1
1
0
0
1
X
X
X
190000h to 19FFFFh
0C8000h to 0CFFFFh
SA26
1
1
0
1
0
X
X
X
1A0000h to 1AFFFFh
0D0000h to 0D7FFFh
SA27
1
1
0
1
1
X
X
X
1B0000h to 1BFFFFh
0D8000h to 0DFFFFh
SA28
1
1
1
0
0
X
X
X
1C0000h to 1CFFFFh
0E0000h to 0E7FFFh
SA29
1
1
1
0
1
X
X
X
1D0000h to 1DFFFFh
0E8000h to 0EFFFFh
SA30
1
1
1
1
0
X
X
X
1E0000h to 1EFFFFh
0F0000h to 0F7FFFh
SA31
1
1
1
1
1
0
0
0
1F0000h to 1F1FFFh
0F8000h to 0F8FFFh
SA32
1
1
1
1
1
0
0
1
1F2000h to 1F3FFFh
0F9000h to 0F9FFFh
SA33
1
1
1
1
1
0
1
0
1F4000h to 1F5FFFh
0FA000h to 0FAFFFh
SA34
1
1
1
1
1
0
1
1
1F6000h to 1F7FFFh
0FB000h to 0FBFFFh
SA35
1
1
1
1
1
1
0
0
1F8000h to 1F9FFFh
0FC000h to 0FCFFFh
SA36
1
1
1
1
1
1
0
1
1FA000h to 1FBFFFh 0FD000h to 0FDFFFh
SA37
1
1
1
1
1
1
1
0
1FC000h to 1FDFFFh 0FE000h to 0FEFFFh
SA38
1
1
1
1
1
1
1
1
1FE000h to 1FFFFFh
0FF000h to 0FFFFFh
21
MB84VD2118XEM/2119XEM-70
Sector Address Table (Bottom Boot Block, Bank Size=4)
Sector Address
Bank
Bank 1
Bank 2
22
Sector
Bank Address
Address Range
(BYTE mode)
Address Range
(WORD mode)
A19
A18
A17
A16
A15
A14
A13
A12
SA0
0
0
0
0
0
0
0
0
000000h to 001FFFh
000000h to 000FFFh
SA1
0
0
0
0
0
0
0
1
002000h to 003FFFh
001000h to 001FFFh
SA2
0
0
0
0
0
0
1
0
004000h to 005FFFh
002000h to 002FFFh
SA3
0
0
0
0
0
0
1
1
006000h to 007FFFh
003000h to 003FFFh
SA4
0
0
0
0
0
1
0
0
008000h to 009FFFh
004000h to 004FFFh
SA5
0
0
0
0
0
1
0
1
00A000h to 00BFFFh
005000h to 005FFFh
SA6
0
0
0
0
0
1
1
0
00C000h to 00DFFFh
006000h to 006FFFh
SA7
0
0
0
0
0
1
1
1
00E000h to 00FFFFh
007000h to 007FFFh
SA8
0
0
0
0
1
X
X
X
010000h to 01FFFFh
008000h to 00FFFFh
SA9
0
0
0
1
0
X
X
X
020000h to 02FFFFh
010000h to 017FFFh
SA10
0
0
0
1
1
X
X
X
030000h to 03FFFFh
018000h to 01FFFFh
SA11
0
0
1
0
0
X
X
X
040000h to 04FFFFh
020000h to 027FFFh
SA12
0
0
1
0
1
X
X
X
050000h to 05FFFFh
028000h to 02FFFFh
SA13
0
0
1
1
0
X
X
X
060000h to 06FFFFh
030000h to 037FFFh
SA14
0
0
1
1
1
X
X
X
070000h to 07FFFFh
038000h to 03FFFFh
SA15
0
1
0
0
0
X
X
X
080000h to 08FFFFh
040000h to 047FFFh
SA16
0
1
0
0
1
X
X
X
090000h to 09FFFFh
048000h to 04FFFFh
SA17
0
1
0
1
0
X
X
X
0A0000h to 0AFFFFh
050000h to 057FFFh
SA18
0
1
0
1
1
X
X
X
0B0000h to 0BFFFFh
058000h to 05FFFFh
SA19
0
1
1
0
0
X
X
X
0C0000h to 0CFFFFh
060000h to 067FFFh
SA20
0
1
1
0
1
X
X
X
0D0000h to 0DFFFFh
068000h to 06FFFFh
SA21
0
1
1
1
0
X
X
X
0E0000h to 0EFFFFh
070000h to 077FFFh
SA22
0
1
1
1
1
X
X
X
0F0000h to 0FFFFFh
078000h to 07FFFFh
SA23
1
0
0
0
0
X
X
X
100000h to 10FFFFh
080000h to 087FFFh
SA24
1
0
0
0
1
X
X
X
110000h to 11FFFFh
088000h to 08FFFFh
SA25
1
0
0
1
0
X
X
X
120000h to 12FFFFh
090000h to 097FFFh
SA26
1
0
0
1
1
X
X
X
130000h to 13FFFFh
098000h to 09FFFFh
SA27
1
0
1
0
0
X
X
X
140000h to 14FFFFh
0A0000h to 0A7FFFh
SA28
1
0
1
0
1
X
X
X
150000h to 15FFFFh
0A8000h to 0AFFFFh
SA29
1
0
1
1
0
X
X
X
160000h to 16FFFFh
0B0000h to 0B7FFFh
SA30
1
0
1
1
1
X
X
X
170000h to 17FFFFh
0B8000h to 0BFFFFh
SA31
1
1
0
0
0
X
X
X
180000h to 18FFFFh
0C0000h to 0C7FFFh
SA32
1
1
0
0
1
X
X
X
190000h to 19FFFFh
0C8000h to 0CFFFFh
SA33
1
1
0
1
0
X
X
X
1A0000h to 1AFFFFh
0D0000h to 0D7FFFh
SA34
1
1
0
1
1
X
X
X
1B0000h to 1BFFFFh
0D8000h to 0DFFFFh
SA35
1
1
1
0
0
X
X
X
1C0000h to 1CFFFFh
0E0000h to 0E7FFFh
SA36
1
1
1
0
1
X
X
X
1D0000h to 1DFFFFh
0E8000h to 0EFFFFh
SA37
1
1
1
1
0
X
X
X
1E0000h to 1EFFFFh
0F0000h to 0F7FFFh
SA38
1
1
1
1
1
X
X
X
1F0000h to 1FFFFFh
0F8000h to 0FFFFFh
MB84VD2118XEM/2119XEM-70
Sector Group Addresses Table (Top Boot Block)
Sector Group
SGA0
SGA1
SGA2
SGA3
SGA4
SGA5
SGA6
SGA7
SGA8
SGA9
SGA10
SGA11
SGA12
SGA13
SGA14
SGA15
SGA16
A19
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A18
0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
A17
0
0
0
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
A16
0
0
1
1
X
X
X
X
X
X
0
0
1
1
1
1
1
1
1
1
1
A15
0
1
0
1
X
X
X
X
X
X
0
1
0
1
1
1
1
1
1
1
1
A14
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
A13
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
A12
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
Sectors
SA0
SA1 to SA3
SA4 to SA7
SA8 to SA11
SA12 to SA15
SA16 to SA19
SA20 to SA23
SA24 to SA27
SA28 to SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
Sector Group Addresses Table (Bottom Boot Block)
Sector Group
SGA0
SGA1
SGA2
SGA3
SGA4
SGA5
SGA6
SGA7
SGA8
SGA9
SGA10
SGA11
SGA12
SGA13
SGA14
SGA15
SGA16
A19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
A18
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
1
A17
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
1
1
A16
0
0
0
0
0
0
0
0
0
1
1
X
X
X
X
X
X
0
0
1
1
A15
0
0
0
0
0
0
0
0
1
0
1
X
X
X
X
X
X
0
1
0
1
A14
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
A13
0
0
1
1
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
A12
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
Sectors
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8 to SA10
SA11 to SA14
SA15 to SA18
SA19 to SA22
SA23 to SA26
SA27 to SA30
SA31 to SA34
SA35 to SA37
SA38
23
MB84VD2118XEM/2119XEM-70
Flash Memory Autoselect Codes Table
Type
Manufacturer’s Code
Top Boot Block
Bank Size=1
Bottom Boot Block
Bank Size=1
Top Boot Block
Bank Size=2
Device
Code
Bottom Boot Block
Bank Size=2
Top Boot Block
Bank Size=3
Bottom Boot Block
Bank Size=3
Top Boot Block
Bank Size=4
Bottom Boot Block
Bank Size=4
Sector Group protect
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
A12 to A19
A6
A1
A0
A–1*1
Code (HEX)
X
VIL
VIL
VIL
VIL
04h
X
VIL
VIL
VIH
VIL
36h
X
2236h
X
VIL
VIL
VIH
VIL
39
X
2239h
X
VIL
VIL
VIH
VIL
2D
X
222Dh
X
VIL
VIL
VIH
VIL
2E
X
222Eh
X
VIL
VIL
VIH
VIL
28h
X
2228h
X
VIL
VIL
VIH
VIL
2Bh
X
222Bh
X
VIL
VIL
VIH
VIL
33h
X
2233h
X
VIL
VIL
VIH
VIL
35
X
2235h
Sector
Group
Address
VIL
VIH
VIL
VIL
01h*2
*1: A–1 is for Byte mode.
*2: Output 01h at protected sector address and output 00h at unprotected sector address.
24
MB84VD2118XEM/2119XEM-70
Flash Memory Command Definitions Table
Bus
First Bus
Second Bus
Write Write Cycle
Write Cycle
Cycles
Req’d Addr. Data Addr.
Data
Command
Sequence
Read/Reset *1
Read/Reset *1
1
Word
Byte
3
Word
Autoselect
Chip Erase
Sector Erase
555h
AAAh
3
Word
Byte
Word
Byte
Word
Byte
F0h
AAh
555h
Byte
Program
XXXh
6
6
2AAh
555h
AAh
555h
AAAh
555h
AAAh
555h
AAAh
—
55h
2AAh
AAAh
4
—
55h
555h
AAh
AAh
AAh
2AAh
555h
2AAh
555h
2AAh
555h
55h
55h
55h
Third Bus
Write Cycle
Addr.
—
555h
AAAh
(BA)
555h
(BA)
AAAh
555h
AAAh
555h
AAAh
555h
AAAh
Fourth Bus
Read/Write
Cycle
Fifth Bus
Write Cycle
Sixth Bus
Write Cycle
Data Addr. Data Addr. Data Addr. Data
—
—
—
—
—
—
—
F0h
RA
RD
—
—
—
—
90h
—
—
—
—
—
—
A0h
PA
PD
—
—
—
—
80h
80h
555h
AAAh
555h
AAAh
AAh
AAh
2AAh
555h
2AAh
555h
55h
555h
AAAh
10h
55h
SA
30h
Sector Erase
Suspend
1
BA
B0h
—
—
—
—
—
—
—
—
—
—
Sector Erase
Resume
1
BA
30h
—
—
—
—
—
—
—
—
—
—
20h
—
—
—
—
—
—
Set to
Fast Mode
Fast Program*2
Word
Byte
Word
Byte
Reset from
Fast Mode *2
Word
Extended
Sector Group
Protection *3
Word
Query *4
Byte
555h
AAAh
AAh
2AAh
555h
55h
555h
AAAh
2
XXXh
A0h
PA
PD
—
—
—
—
—
—
—
—
2
BA
90h
XXXh
F0h
*6
—
—
—
—
—
—
—
—
4
XXXh
60h
SPA
60h
SPA
40h
SPA
SD
—
—
—
—
98h
—
—
—
—
—
—
—
—
—
—
88h
—
—
—
—
—
—
A0h
PA
PD
—
—
—
—
55h
HRA
30h
—
—
—
Byte
Word
Byte
HiddenROM
Entry
Word
HiddenROM
Program *5
Word
HiddenROM
Erase *5
Word
HiddenROM
Exit *5
3
Byte
Byte
Byte
1
3
4
6
Word
55h
AAh
555h
AAAh
555h
AAAh
555h
AAAh
AAh
AAh
555h
4
Byte
AAh
2AAh
555h
2AAh
555h
2AAh
555h
55h
55h
2AAh
AAh
AAAh
55h
55h
555h
555h
AAAh
555h
AAAh
555h
AAAh
(HRBA)
555h
(HRBA)
AAAh
80h
90h
555h
AAAh
XXXh
AAh
00h
2AAh
555h
—
25
MB84VD2118XEM/2119XEM-70
*1: Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
*2: This command is valid while Fast Mode.
*3: This command is valid while RESET=VID.
*4: The valid Address is A6 to A0.
*5: This command is valid while HiddenROM mode.
*6: The data "00h" is also acceptable.
Notes : • Address bits A12 to A19 = X = “H” or “L” for all address commands except for Program Address (PA),
Sector Address (SA),and Bank Address (BA).
Bus operations are defined in "User Bus Operations".
RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed.
Addresses are latched on the falling edge of the write pulse.
• SA = Address of the sector to be erased. The combination of A19, A18, A17, A16, A15, A14, A13, and A12 will
uniquely select any sector.
BA = Bank address (A15 to A19)
SPA = Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (0, 1, 0).
HRA = Address of the HiddenROM area.
Top Boot Block
Word mode : 0F8000h to 0FFFFFh
Byte mode : 1F0000h to 1FFFFFh
Bottom Boot Block Word mode : 000000h to 007FFFh
Byte mode : 000000h to 00FFFFh
HRBA = Bank address of the HiddenROM area.
Top Boot Block
: A15 = A16 = A17 = A18 = A19 = A20 = 1
Bottom Boot Block : A15 = A16 = A17 = A18 = A19 = A20 = 0
RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA.
SD = Sector protection verify data. Output 01h at protected sector addresses and output 00h
at unprotected sector addresses.
• The system should generate the following address patterns;
Word mode : 555h or 2AAh to addresses A10 to A0
Byte mode : AAAh or 555h to addresses A10 to A0 and A–1
26
MB84VD2118XEM/2119XEM-70
• Read Only Operations Characteristics (Flash)
Symbol
Parameter
JEDEC Standard
Test Setup
Value*
Min
Max
Unit
Read Cycle Time
tAVAV
tRC
—
70
—
ns
Address to Output Delay
tAVQV
tACC
CEf = VIL
OE = VIL
—
70
ns
Chip Enable to Output Delay
tELQV
tCEf
OE = VIL
—
70
ns
Output Enable to Output Delay
tGLQV
tOE
—
—
30
ns
Chip Enable to Output High-Z
tEHQZ
tDF
—
—
25
ns
Output Enable to Output High-Z
tGHQZ
tDF
—
—
25
ns
Output Hold Time From Addresses,
CEf or OE, Whichever Occurs First
tAXQX
tOH
—
0
—
ns
—
tREADY
—
—
20
µs
RESET Pin Low to Read Mode
* : Test Conditions
Output Load : 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels : 0.0 V or 3.0 V
Timing measurement reference level
Input : 1.5 V
Output : 1.5 V
27
MB84VD2118XEM/2119XEM-70
• Read Cycle (Flash)
tRC
Address Stable
Address
tACC
CEf
tOE
tDF
OE
tOEH
WE
tCEf
High-Z
DQ
High-Z
Output Valid
tRC
Address
Address Stable
tACC
CEf
tRH
tRP
tRH
tCEf
RESET
tOH
DQ
28
High-Z
Output Valid
MB84VD2118XEM/2119XEM-70
• Erase/Program Operations (Flash)
Parameter
Symbol
JEDEC Standard
Value
Min
Typ
Max
Unit
Write Cycle Time
tAVAV
tWC
70
—
—
ns
Address Setup Time (WE to Addr.)
tAVWL
tAS
0
—
—
ns
—
tASO
12
—
—
ns
tWLAX
tAH
45
—
—
ns
—
tAHT
0
—
—
ns
Data Setup Time
tDVWH
tDS
30
—
—
ns
Data Hold Time
tWHDX
tDH
0
—
—
ns
—
tOES
0
—
—
ns
—
tOEH
0
—
—
ns
10
—
—
ns
CEf High During Toggle Bit Polling
—
tCEPH
20
—
—
ns
OE High During Toggle Bit Polling
—
tOEPH
20
—
—
ns
Read Recover Time Before Write (OE to CEf)
tGHEL
tGHEL
0
—
—
ns
Read Recover Time Before Write (OE to WE)
tGHWL
tGHWL
0
—
—
ns
WE Setup Time (CEf to WE)
tWLEL
tWS
0
—
—
ns
CEf Setup Time (WE to CEf)
tELWL
tCS
0
—
—
ns
WE Hold Time (CEf to WE)
tEHWH
tWH
0
—
—
ns
CEf Hold Time (WE to CEf)
tWHEH
tCH
0
—
—
ns
Write Pulse Width
tWLWH
tWP
35
—
—
ns
CEf Pulse Width
tELEH
tCP
35
—
—
ns
Write Pulse Width High
tWHWL
tWPH
25
—
—
ns
CEf Pulse Width High
tEHEL
tCPH
25
—
—
ns
tWHWH1
tWHWH1
—
8
—
µs
—
16
—
µs
tWHWH2
tWHWH2
—
1
—
s
VCCf Setup Time
—
tVCS
50
—
—
µs
Voltage Transition Time *2
—
tVLHT
4
—
—
µs
Rise Time to VID *2
—
tVIDR
500
—
—
ns
Rise Time to VACC
—
tVACCR
500
—
—
ns
Recover Time from RY/BY
—
tRB
0
—
—
ns
RESET Pulse Width
—
tRP
500
—
—
ns
Delay Time from Embedded Output Enable
—
tEOE
—
—
70
ns
RESET Hold Time Before Read
—
tRH
200
—
—
ns
Program/Erase Valid to RY/BY Delay
—
tBUSY
—
—
90
ns
Erase Time-out Time *3
—
tTOW
50
—
—
µs
Erase Suspend Transition Time *4
—
tSPD
—
—
20
µs
Address Setup Time to CEf Low During Toggle Bit Polling
Address Hold Time (WE to Addr.)
Address Hold Time from CEf or OE High During Toggle Bit
Polling
Output Enable Setup Time
Output Enable Hold Time
Read
Toggle and Data Polling
Byte Programming Operation
Word Programming Operation
Sector Erase Operation *
1
29
MB84VD2118XEM/2119XEM-70
*1 : This does not include the preprogramming time.
*2 : This timing is for Sector Protection Operation.
*3 : The time between writes must be less than "tTOW" otherwise that command will not be accepted and erasure
will start. A time-out or "tTOW" from the rising edge of last CEf or WE whichever happens first will initiate the
execution of the Sector Erase command(s).
*4 : When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of "tSPD" to suspend the erase operation.
30
MB84VD2118XEM/2119XEM-70
• Write Cycle (WE control) (Flash)
3rd Bus Cycle
Data Polling
555h
Address
tWC
PA
tAS
PA
tRC
tAH
CEf
tCH
tCS
tCEf
OE
tGHWL
tWP
tOE
tWHWH1
tWPH
WE
tOH
tDS
tDH
DQ
Notes : •
•
•
•
•
•
A0h
PD
DQ7
DOUT
DOUT
PA is address of the memory location to be programmed.
PD is data to be programmed at byte address.
DQ7 is the output of the complement of the data written to the device.
DOUT is the output of the data written to the device.
Figure indicates last two bus cycles out of four bus cycle sequence.
These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
31
MB84VD2118XEM/2119XEM-70
• Write Cycle (CEf control) (Flash)
3rd Bus Cycle
Address
Data Polling
PA
555h
tWC
tAS
PA
tAH
WE
tWS
tWH
OE
tGHEL
tCP
tWHWH1
tCPH
CEf
tDS
tDH
DQ
Notes : •
•
•
•
•
•
32
A0h
PD
DQ7
DOUT
PA is address of the memory location to be programmed.
PD is data to be programmed at byte address.
DQ7 is the output of the complement of the data written to the device.
DOUT is the output of the data written to the device.
Figure indicates last two bus cycles out of four bus cycle sequence.
These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
MB84VD2118XEM/2119XEM-70
• AC Waveforms Chip/Sector Erase Operations (Flash)
2AAh
555h
Address
tWC
tAS
555h
SA*
2AAh
555h
tAH
CEf
tCS
tCH
OE
tGHWL
tWP
tWPH
WE
tDS
tDH
AAh
DQ
30h for Sector Erase
55h
80h
AAh
55h
10h/
30h
tVCS
VCCf
* : SA is the sector address for Sector Erase. Addresses = 555h for Chip Erase.
Note : These waveform are for the ×16 mode. (The addresses differ from ×8 mode.)
33
MB84VD2118XEM/2119XEM-70
• AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)
CEf
tCH
tDF
tOE
OE
tOEH
WE
tCEf
*
DQ7
DQ7 =
Valid Data
DQ7
Data In
High-Z
tWHWH1 or 2
DQ
(DQ6 to DQ0)
DQ6 to DQ0 = Output Flag
Data In
tBUSY
tEOE
RY/BY
* : DQ7 = Valid Data (The device has completed the Embedded operation.)
34
DQ6 to DQ0
Valid Data
High-Z
MB84VD2118XEM/2119XEM-70
• AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)
Address
tAHT
tASO
tAHT
tAS
CEf
tCEPH
WE
tOEH
tOEH
tOEPH
OE
tDH
DQ6/DQ2
Data
tCEf *
tOE
Toggle
Data
Toggle
Data
Toggle
Data
Stop
Toggling
Output
Valid
tBUSY
RY/BY
* : DQ6 stops toggling (The device has completed the Embedded operation).
35
MB84VD2118XEM/2119XEM-70
• Bank-to-bank Read/Write Timing Diagram (Flash)
Address
Address
Read
Command
Read
Command
Read
Read
tRC
tWC
tRC
tWC
tRC
tRC
BA1
BA2
(555h)
BA1
BA2
(PA)
BA1
BA2
(PA)
tAS
tACC
tAH
tAS
tAHT
tCE
CEf
CEf
tOE
tCEPH
OE
OE
tGHWL
tDF
tOEH
tWP
WE
WE
tDS
DQ
DQ
Valid
Output
tDH
Valid
Intput
(A0h)
tDF
Valid
Output
Valid
Intput
(PD)
Valid
Output
Status
Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.
BA1: Address of Bank 1.
BA2: Address of Bank 2.
36
MB84VD2118XEM/2119XEM-70
• RY/BY Timing Diagram during Write/Erase Operations (Flash)
CEf
Rising edge of the last write pulse
WE
Entire programming
or erase operations
RY/BY
tBUSY
• RESET, RY/BY Timing Diagram (Flash)
WE
RESET
tRP
tRB
RY/BY
tREADY
37
MB84VD2118XEM/2119XEM-70
• Temporary Sector Unprotection (Flash)
VCCf
tVIDR
tVCS
tVLHT
VID
VIH
RESET
CEf
WE
tVLHT
Program or Erase Command Sequence
tVLHT
RY/BY
Unprotection period
• Acceleration Mode Timing Diagram (Flash)
VCCf
tVACCR
tVCS
tVLHT
VACC
VIH
WP/ACC
CEf
WE
tVLHT
tVLHT
RY/BY
Acceleration Mode Period
38
MB84VD2118XEM/2119XEM-70
• Extended Sector Protection (Flash)
VCCf
tVCS
RESET
tVLHT
tVIDR
tWC
Add
tWC
SGAx
SGAx
SGAy
A0
A1
A6
CEf
OE
TIME-OUT
tWP
WE
Data
60h
60h
40h
01h
60h
tOE
SGAx : Sector Group Address to be protected
SGAy : Next Group Sector Address to be protected
TIME-OUT : Time-Out window = 250 µs (Min)
39
MB84VD2118XEM/2119XEM-70
2. Erase and Programming Performance (Flash)
Limit
Parameter
Comment
Typ
Max
Sector Erase Time
—
1
10
s
Excludes programming time
prior to erasure
Byte Programming Time
—
8
300
µs
Excludes system-level
overhead
Word Programming Time
—
16
360
µs
Excludes system-level
overhead
Chip Programming Time
—
—
50
s
Excludes system-level
overhead
100,000
—
—
cycle
Erase/Program Cycle
40
Unit
Min
MB84VD2118XEM/2119XEM-70
■ 4M SRAM CHARACTERISTICS for MCP
1. AC Characteristics
• Read Cycle (SRAM)
Parameter
Symbol
Value
Min
Max
Unit
Read Cycle Time
tRC
70
—
ns
Address Access Time
tAA
—
70
ns
Chip Enable (CE1s) Access Time
tCO1
—
70
ns
Chip Enable (CE2s) Access Time
tCO2
—
70
ns
Output Enable Access Time
tOE
—
35
ns
LB, UB to Output Valid
tBA
—
70
ns
Chip Enable (CE1s Low and CE2s High) to Output Active
tCOE
5
—
ns
Output Enable Low to Output Active
tOEE
0
—
ns
UB, LB Enable Low to Output Active
tBE
0
—
ns
Chip Enable (CE1s High or CE2s Low) to Output High-Z
tOD
—
25
ns
Output Enable High to Output High-Z
tODO
—
25
ns
UB, LB Output Enable to Output High-Z
tBD
—
25
ns
Output Data Hold Time
tOH
10
—
ns
Note: Test Conditions
Output Load:1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to VCCs
Timing measurement reference level
Input: 0.5×VCCs
Output: 0.5×VCCs
41
MB84VD2118XEM/2119XEM-70
• Read Cycle (SRAM)
tRC
Address
tAA
tOH
tCO1
CE1s
tCOE
tOD
tCO2
CE2s
tOD
tOE
OE
tODO
tOEE
LB, UB
tBD
tBA
tBE
tCOE
DQ
Note : WE remains “H” for the read cycle.
42
Valid Data Out
MB84VD2118XEM/2119XEM-70
• Write Cycle (SRAM)
Parameter
Symbol
Value
Min
Max
Unit
Write Cycle Time
tWC
70
—
ns
Write Pulse Width
tWP
50
—
ns
Chip Enable to End of Write
tCW
55
—
ns
Address valid to End of Write
tAW
55
—
ns
UB, LB to End of Write
tBW
55
—
ns
Address Setup Time
tAS
0
—
ns
Write Recovery Time
tWR
0
—
ns
WE Low to Output High-Z
tODW
—
25
ns
WE High to Output Active
tOEW
0
—
ns
Data Setup Time
tDS
30
—
ns
Data Hold Time
tDH
0
—
ns
43
MB84VD2118XEM/2119XEM-70
• Write Cycle *3 (WE control) (SRAM)
tWC
Address
tAS
tWP
tWR
WE
tAW
tCW
CE1s
CE2s
tCW
tBW
LB, UB
tOEW
tODW
DOUT
*1
*2
tDS
DIN
*4
tDH
Valid Data In
*4
*1 : If CE1s goes “L” (or CE2s goes “H”) coincident with or after WE goes “L”, the output will
remain at High-Z.
*2 : If CE1s goes “H” (or CE2s goes “L”) coincident with or before WE goes “H”, the output will
remain at High-Z.
*3 : If OE is “H” during the write cycle, the outputs will remain at High-Z.
*4 : Because I/O signals may be in the output state at this Time, input signals of reverse
polarity must not be applied.
44
MB84VD2118XEM/2119XEM-70
• Write Cycle *1 (CE1s control) (SRAM)
tWC
Address
tAS
tWP
tWR
WE
tAW
tCW
CE1s
CE2s
tCW
tBW
LB, UB
tBE
tCOE
tODW
DOUT
tDS
DIN
*2
tDH
Valid Data In
*1 : If OE is “H” during the write cycle, the outputs will remain at High-Z.
*2 : Because I/O signals may be in the output state at this Time, input signals of reverse
polarity must not be applied.
45
MB84VD2118XEM/2119XEM-70
• Write Cycle *1 (CE2s Control) (SRAM)
tWC
Address
tAS
tWP
tWR
WE
tCW
CE1s
tAW
CE2s
tCW
tBW
LB, UB
tBE
tCOE
tODW
DOUT
tDS
DIN
*2
tDH
Valid Data In
*1 : If OE is “H” during the write cycle, the outputs will remain at High-Z.
*2 : Because I/O signals may be in the output state at this Time, input signals of reverse
polarity must not be applied.
46
MB84VD2118XEM/2119XEM-70
• Write Cycle *1 (LB, UB Control) (SRAM)
tWC
Address
tWP
tWR
WE
tCW
CE1s
tCW
CE2s
tAW
tAS
tBW
LB, UB
tBE
tCOE
tODW
DOUT
tDS
DIN
*2
tDH
Valid Data In
*1 : If OE is “H” during the write cycle, the outputs will remain at High-Z.
*2 : Because I/O signals may be in the output state at this Time, input signals of reverse
polarity must not be applied.
47
MB84VD2118XEM/2119XEM-70
2. Data Retention Characteristics (SRAM)
Parameter
Symbol
Data Retention Supply Voltage
Standby Current
VDH = 1.5 V
Chip Deselect to Data Retention Mode Time
Recovery Time
Value
Unit
Min
Typ
Max
VDH
1.5
—
3.3
V
IDDS2
—
3
10
µA
tCDR
0
—
—
ns
tR
tRC
—
—
ns
Note : tRC: Read cycle time
• CE1s Controlled Data Retention Mode *1
VCCs
DATA RETENTION MODE
2.7 V
*2
*2
VIH
VDH
VCCS –0.2 V
CE1s
tR
tCDR
GND
*1 : In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs–0.2 V or Vss
to 0.2 V during data retention mode. Other input and input/output pins can be used between –0.3 V to
Vccs+0.3 V.
*2 : When CE1s is operating at the VIH Min level (2.2 V), the standby current is given by ISB1s during the
transition of VCCs from 3.3 V to 2.2 V.
• CE2s Controlled Data Retention Mode *
VCCs
DATA RETENTION MODE
2.7 V
VDH
VIH
VIL
CE2s
tCDR
tR
0.2 V
GND
* : In CE2s controlled data retention mode, input and input/output pins can be used between
–0.3 V to Vccs+0.3 V.
48
MB84VD2118XEM/2119XEM-70
■ PIN CAPACITANCE
Value
Parameter
Input Capacitance
Symbol
CIN
Test Setup
Unit
Typ
Max
VIN = 0
11
14
pF
Output Capacitance
COUT
VOUT = 0
12
16
pF
Control Pin Capacitance
CIN2
VIN = 0
14
16
pF
WP/ACC Pin Capacitance
CIN3
VIN = 0
17
20
pF
Note : Test conditions TA = +25°C, f = 1.0 MHz
■ HANDLING OF PACKAGE
Please handle this package carefully since the sides of package create acute angles.
■ CAUTION
• The high voltage (VID) cannot apply to address pins and control pins except RESET.
Exception is when autoselect and sector group protect function are used, then the high voltage (VID) can be
applied to RESET.
• Without the high voltage (VID) , sector group protection can be achieved by using “Extended Sector Group
Protection” command.
49
MB84VD2118XEM/2119XEM-70
■ ORDERING INFORMATION
MB84VD2118
X
EM
-70
PBS
PACKAGE TYPE
PBS = 56-ball FBGA
SPEED OPTION
See Product Selector Guide
Device Revision (Valid Combination)
EM
Bank Size
1 = 0.5 Mbit / 15.5 Mbit
2 = 2 Mbit / 14 Mbit
3 = 4 Mbit / 12 Mbit
4 = 8 Mbit / 8 Mbit
DEVICE NUMBER/DESCRIPTION
16 Mega-bit (2M × 8-bit or 1M × 16-bit) Dual Operation Flash Memory
3.0 V-only Read, Program, and Erase
4 Mega-bit (512K × 8-bit or 256K × 16-bit) SRAM
BOOT CODE SECTOR ARCHITECTURE
84VD2118 = Top sector
84VD2119 = Bottom sector
50
MB84VD2118XEM/2119XEM-70
■ PACKAGE DIMENSION
56-ball plastic FBGA
(BGA-56P-M02)
+0.11
7.20±0.10(.283±.004)
0.20(.008) S B
1.09 –0.10
+.004
B
(Mounting height)
.043 –.004
0.39±0.10
(Stand off)
(.015±.004)
0.40(.016)
REF
0.80(.031)
REF
0.80(.031)
REF
8
7
6
5
4
3
2
1
A
7.00±0.10
(.276±.004)
0.40(.016)
REF
S
INDEX-MARK AREA
H G F E D C B A
0.20(.008) S A
INDEX
56-ø0.45 +0.10
–0.05
56-ø.018 +.004
–.002
0.08(.003)
M
S A B
0.10(.004) S
C
2002 FUJITSU LIMITED B56002S-c-1-1
Dimensions in mm (inches)
Note : The values in parentheses are regerence values.
51
MB84VD2118XEM/2119XEM-70
FUJITSU LIMITED
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representatives before ordering.
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circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
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device based on such information, you must assume any
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If any products described in this document represent goods or
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F0307
 FUJITSU LIMITED Printed in Japan