SPANSION S71GL064A08BFW0F2

S71GL032A Based MCPs
Stacked Multi-Chip Product (MCP) Flash Memory and
RAM
32 Megabit (2 M x 16-bit) CMOS 3.0 Volt-only
Page Mode Flash Memory and
16/8/4 Megabit (1M/512K/256K x 16-bit)
Pseudo Static RAM
Data Sheet
ADVANCE
INFORMATION
Notice to Readers: The Advance Information status indicates that this
document contains information on one or more products under development
at Spansion LLC. The information is intended to help you evaluate this product.
Do not design in this product without contacting the factory. Spansion LLC
reserves the right to change or discontinue work on this proposed product
without notice.
Publication Number S71GL032A_00
Revision A
Amendment 0
Issue Date March 31, 2005
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise
readers of product information or intended specifications throughout the product life cycle, including
development, qualification, initial production, and full production. In all cases, however, readers are
encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence
and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more specific
products, but has not committed any design to production. Information presented in a document
with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion LLC therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion LLC. The
information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the
manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. The Preliminary status of this document indicates that product qualification has been completed,
and that initial production has begun. Due to the phases of the manufacturing process that require
maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.”
Combination
Some data sheets will contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document will distinguish these products and
their designations wherever necessary, typically on the first page, the ordering information page, and
pages with DC Characteristics table and AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes
may include those affecting the number of ordering part numbers available, such as the addition or
deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion LLC applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. Spansion LLC deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification
corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local AMD or
Fujitsu sales office.
S71GL032A Based MCPs
Stacked Multi-Chip Product (MCP) Flash Memory and RAM
32 Megabit (2 M x 16-bit) CMOS 3.0 Volt-only
Page Mode Flash Memory and
16/8/4 Megabit (1M/512K/256K x 16-bit)
Pseudo Static RAM
ADVANCE
INFORMATION
General Description
The S71GL series is a product line of stacked Multi-Chip Product (MCP) packages and consists
of:
One S29PL032A (Simultaneous Read/Write) Flash memory die
pSRAM or SRAM
The products covered by this document are listed in the table below:
Flash Memory Density
32Mb
pSRAM
Density
4Mb
S71GL032A40
8Mb
S71GL032A80/S71GL032A08
Distinctive Characteristics
MCP Features
Power supply voltage of 2.7 V to 3.1 V
High performance
— 100 ns (100 ns Flash, 70 ns pSRAM/SRAM)
Packages
— 7 x 9 x 1.2 mm 56 ball FBGA
Operating Temperature
— –25°C to +85°C
— –40°C to +85°C
Publication Number S71GL032A_00
Revision A
Amendment 0
Issue Date March 31, 2005
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not
design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
Product Selector Guide
32 Mb Flash Memory
Device-Model#
Flash Access time (ns)
S71GL032A40-0B
S71GL032A40-0F
S71GL032A08-0B
S71GL032A08-0F
4
(p)SRAM density
(p)SRAM Access time (ns) pSRAM type
4 M pSRAM
100
pSRAM4
70
8 M pSRAM
S71GL032A Based MCPs
Package
TLC056
SRAM1
S71GL032A_00_A0 March 31, 2005
A d v a n c e
I n f o r m a t i o n
Contents
S71GL032A Based MCPs
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .4
32 Mb Flash Memory ............................................................................................4
Connection Diagram (S71GL032A) . . . . . . . . . . . . .8
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 10
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 12
TLC056—56-ball Fine-Pitch Ball Grid Array (FBGA)
9 x 7 mm Package ............................................................................................... 12
S29GL-A MirrorBit™ Flash Family
General Description . . . . . . . . . . . . . . . . . . . . . . . . 14
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 16
S29GL064A, S29GL032A .................................................................................. 16
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Logic Symbol-S29GL064A (Model R6, R7) ................................................. 20
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 21
Table 1. Device Bus Operations ........................................... 21
Requirements for Reading Array Data ........................................................ 22
Page Mode Read ............................................................................................. 22
Writing Commands/Command Sequences ................................................ 22
Write Buffer .....................................................................................................23
Accelerated Program Operation ...............................................................23
Autoselect Functions .....................................................................................23
Standby Mode .......................................................................................................23
Automatic Sleep Mode ......................................................................................23
RESET#: Hardware Reset Pin ........................................................................ 24
Output Disable Mode ....................................................................................... 24
Table 2. S29GL032M (Models R1, R2) Sector Addresses ......... 24
Table 3. S29GL032M (Models R3) Top Boot Sector Addresses . 25
Table 4. S29GL032M (Models R4) Bottom
Boot Sector Addresses ....................................................... 25
Table 5. S29GL064A (Models R1, R2, R8, R9)
Sector Addresses .............................................................. 26
Table 6. S29GL064A (Model R3) Top Boot Sector Addresses ... 27
Table 7. S29GL064A (Model R4) Bottom Boot Sector Addresses 28
Table 8. S29GL064A (Model R5) Sector Addresses ................. 29
Table 9. S29GL064A (Models R6, R7) Sector Addresses .......... 30
Autoselect Mode ..................................................................................................31
Sector Group Protection and Unprotection ...............................................31
Table 10. S29GL032A (Models R1, R2) Sector Group Protection/
Unprotection Addresses ...................................................... 32
Table 11. S29GL032A (Models R3) Sector Group Protection/
Unprotection Address Table ................................................ 32
Table 12. S29GL032A (Models R4) Sector Group Protection/
Unprotection Address Table ................................................ 32
Table 13. S29GL064A (Models R1, R2, R8, R9) Sector Group
Protection/Unprotection Addresses ...................................... 32
Table 14. S29GL064A (Model R3) Top Boot Sector Protection/
Unprotection Addresses ...................................................... 34
Table 15. S29GL064A (Model R4) Bottom Boot Sector Protection/
Unprotection Addresses ...................................................... 34
Table 16. S29GL064A (Model R5) Sector Group Protection/
Unprotection Addresses ...................................................... 34
Table 17. S29GL064A (Models R6, R7) Sector Group Protection/
Unprotection Addresses ...................................................... 34
March 31, 2005 S71GL032A_00_A0
Figure 1. Temporary Sector Group Unprotect Operation.......... 35
Figure 2. In-System Sector Group
Protect/Unprotect Algorithms .............................................. 36
Secured Silicon Sector Flash Memory Region ........................................... 37
Write Protect (WP#) ....................................................................................... 38
Hardware Data Protection ............................................................................. 38
Low VCC Write Inhibit ................................................................................ 39
Write Pulse “Glitch” Protection ............................................................... 39
Logical Inhibit ................................................................................................... 39
Power-Up Write Inhibit ............................................................................... 39
Common Flash Memory Interface (CFI) . . . . . . . 40
Table 18. CFI Query Identification String .............................. 40
Table 19. System Interface String........................................ 41
Table 20. Device Geometry Definition................................... 42
Table 21. Primary Vendor-Specific Extended Query ................ 43
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 44
Reading Array Data ...........................................................................................44
Reset Command .................................................................................................44
Autoselect Command Sequence .................................................................... 45
Enter Secured Silicon Sector/Exit Secured Silicon
Sector Command Sequence ............................................................................ 45
Word Program Command Sequence ...................................................... 45
Unlock Bypass Command Sequence ........................................................46
Write Buffer Programming ..........................................................................46
Accelerated Program ....................................................................................48
Figure 3. Write Buffer Programming Operation ...................... 49
Figure 4. Program Operation ............................................... 50
Program Suspend/Program Resume Command Sequence ....................50
Figure 5. Program Suspend/Program Resume........................ 51
Chip Erase Command Sequence .................................................................... 51
Sector Erase Command Sequence . . . . . . . . . . . . 53
Figure 6. Erase Operation ................................................... 54
Erase Suspend/Erase Resume Commands .................................................. 54
Table 22. Command Definitions (x16 Mode) .......................... 56
DQ7: Data# Polling ............................................................................................ 57
Figure 7. Data# Polling Algorithm ........................................ 58
RY/BY#: Ready/Busy# .......................................................................................58
Figure 8. Toggle Bit Algorithm ............................................. 60
Reading Toggle Bits DQ6/DQ2 ......................................................................61
DQ5: Exceeded Timing Limits .........................................................................61
DQ3: Sector Erase Timer ................................................................................62
DQ1: Write-to-Buffer Abort ........................................................................... 62
Table 23. Write Operation Status ......................................... 63
Figure 9. Maximum Negative Overshoot Waveform ................ 64
Figure 10. Maximum Positive
Overshoot Waveform ......................................................... 64
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .64
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 65
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 11. Test Setup......................................................... 66
Table 24. Test Specifications ............................................... 66
Key to Switching Waveforms . . . . . . . . . . . . . . . 66
Figure 12. Input Waveforms and Measurement Levels ............ 66
Read-Only Operations-S29GL064A only .................................................... 67
Read-Only Operations-S29GL032A only .................................................... 67
Figure 13. Read Operation Timings ...................................... 68
Figure 14. Page Read Timings ............................................. 68
Hardware Reset (RESET#) ..............................................................................69
Figure 15. Reset Timings .................................................... 69
S71GL032A Based MCPs
5
A d v a n c e
Erase and Program Operations-S29GL064A Only .................................. 70
Figure 16. Program Operation Timings .................................. 72
Figure 17. Accelerated Program Timing Diagram .................... 72
Figure 18. Chip/Sector Erase Operation Timings ..................... 73
Figure 19. Data# Polling Timings
(During Embedded Algorithms) ............................................ 73
Figure 20. Toggle Bit Timings (During Embedded Algorithms) .. 74
Figure 21. DQ2 vs. DQ6 ...................................................... 74
Temporary Sector Unprotect .........................................................................75
Figure 22. Temporary Sector Group Unprotect Timing Diagram 75
Figure 23. Sector Group Protect and Unprotect Timing Diagram 76
Alternate CE# Controlled Erase and
Program Operations-S29GL064A ..................................................................77
Figure 24. Alternate CE# Controlled Write (Erase/Program)
Operation Timings .............................................................. 79
Erase And Programming Performance . . . . . . . .80
Type 4 pSRAM
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Functional Description . . . . . . . . . . . . . . . . . . . . . 81
Product Portfolio ................................................................................................ 81
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . 82
Operating Range ................................................................................................. 82
Table 25. DC Electrical Characteristics
(Over the Operating Range) ............................................... 82
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . 83
AC Test Loads and Waveforms . . . . . . . . . . . . . 83
Figure 25. AC Test Loads and Waveforms .............................. 83
Table 26. Switching Characteristics ...................................... 84
Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 85
Figure 26. Read Cycle 1 (Address Transition Controlled) .......... 85
Figure 27. Read Cycle 2 (OE# Controlled) ............................. 85
Figure 28. Write Cycle 1 (WE# Controlled) ............................ 86
Figure 29. Write Cycle 2 (CE#1 or CE2 Controlled) ................. 87
Figure 30. Write Cycle 3 (WE# Controlled, OE# Low).............. 88
Figure 31. Write Cycle 4 (BHE#/BLE# Controlled, OE# Low) .... 88
Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 27. Truth Table ......................................................... 89
I n f o r m a t i o n
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Functional Description . . . . . . . . . . . . . . . . . . . . . . 91
4M Version F, 4M version G, 8M version C ...........................................91
Byte Mode ..............................................................................................................91
Functional Description . . . . . . . . . . . . . . . . . . . . . 92
8M Version D ..................................................................................................92
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 93
Recommended DC Operating Conditions (Note 1) ............................... 93
Capacitance (f=1MHz, TA=25°C) ................................................................... 93
DC Operating Characteristics ....................................................................... 93
Common ........................................................................................................... 93
DC Operating Characteristics .......................................................................94
4M Version F ...................................................................................................94
DC Operating Characteristics .......................................................................94
4M Version G ..................................................................................................94
DC Operating Characteristics ....................................................................... 95
8M Version C .................................................................................................. 95
DC Operating Characteristics ....................................................................... 95
8M Version D .................................................................................................. 95
AC Operating Conditions . . . . . . . . . . . . . . . . . . . 96
Test Conditions ..................................................................................................96
Figure 32. AC Output Load.................................................. 96
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 96
Read/Write Characteristics (VCC=2.7-3.3V) ..............................................96
Data Retention Characteristics (4M Version F) ....................................... 97
Data Retention Characteristics (4M Version G) ......................................98
Data Retention Characteristics (8M Version C) ......................................98
Data Retention Characteristics (8M Version D) ......................................98
Timing Diagrams .................................................................................................98
Figure 33. Timing Waveform of Read Cycle(1) (Address Controlled,
CS#1=OE#=VIL, CS2=WE#=VIH, UB# and/or LB#=VIL) ........ 98
Figure 34. Timing Waveform of Read Cycle(2) (WE#=VIH, if BYTE#
is Low, Ignore UB#/LB# Timing) ......................................... 99
Figure 35. Timing Waveform of Write Cycle(1) (WE# controlled, if
BYTE# is Low, Ignore UB#/LB# Timing) ............................... 99
Figure 36. Timing Waveform of Write Cycle(2) (CS# controlled, if
BYTE# is Low, Ignore UB#/LB# Timing) ............................. 100
Figure 37. Timing Waveform of Write Cycle(3) (UB#, LB#
controlled)...................................................................... 100
Figure 38. Data Retention Waveform.................................. 101
Type 1 SRAM
Common Features . . . . . . . . . . . . . . . . . . . . . . . . 90
6
S71GL032A Based MCPs
Revision Summary
S71GL032A_00_A0 March 31, 2005
A d v a n c e
I n f o r m a t i o n
MCP Block Diagram
VCCf
VCC
CE#
WP#/ACC
RESET#
Flash-only Address
Flash
Shared Address
OE#
WE#
VSS
RY/BY#
VCCS
DQ15 to DQ0
VCC
pSRAM/SRAM
IO15-IO0
CE#s
CE#
UB#s
UB#
LB#s
LB#
CE2
March 31, 2005 S71GL032A_00_A0
S71GL032A Based MCPs
7
A d v a n c e
I n f o r m a t i o n
Connection Diagram (S71GL032A)
56-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
A2
A3
A4
A5
A6
A7
Legend
A7
LB#
WP/ACC
WE#
A8
A11
B1
B2
B3
B4
B5
B6
B7
B8
A3
A6
UB#
RST#f
CE2s
A19
A12
A15
C1
C2
C3
C4
C5
C6
C7
C8
A2
A5
A18
RY/BY#
A20
A9
A13
RFU
D1
D2
D3
D6
D7
D8
A1
A4
A17
A10
A14
RFU
E1
E2
E3
E6
E7
E8
A0
VSS
DQ1
DQ6
RFU
A16
F1
F2
F3
F4
F5
F6
F7
F8
CE1#f
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
G1
G2
G3
G4
G5
G6
G7
G8
CE1#s
DQ0
DQ10
VCCf
VCCs
DQ12
DQ7
VSS
H2
H3
H4
H5
H6
H7
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
Shared
(Note 1)
Flash only
RAM only
Reserved for
Future Use
Notes:
1. May be shared depending on density.
— A18 is shared for the 8M (p)SRAM and above configurations.
MCP
8
Flash-only Addresses
Shared Addresses
S71GL032A80
A20-A19
A18-A0
S71GL032A08
A20-A19
A18-A0
S71GL032A40
A20-A18
A17-A0
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
A d v a n c e
I n f o r m a t i o n
Pin Description
A20–A0
DQ15–DQ0
CE#f
CE#ps
OE#
WE#
RY/BY#
UB#
LB#
RESET#
WP#/ACC
VCCf
=
=
=
=
=
=
=
=
=
=
=
=
VCCps
VSS
NC
=
=
=
21 Address Inputs (Common and Flash only)
16 Data Inputs/Outputs (Common)
Chip Enable (Flash)
Chip Enable 1 (pSRAM)
Output Enable (Common)
Write Enable (Common)
Ready/Busy Output (Flash 1)
Upper Byte Control (pSRAM/SRAM)
Lower Byte Control (pSRAM/SRAM)
Hardware Reset Pin, Active Low (Flash)
Hardware Write Protect/Acceleration Pin (Flash)
Flash 3.0 volt-only single power supply (see Product
Selector Guide for speed options and voltage supply
tolerances)
pSRAM/SRAM Power Supply
Device Ground (Common)
Pin Not Connected Internally
Logic Symbol
21
A20–A0
16
CE1#f
DQ15–DQ0
CE2#f
CE1#ps
CE2ps
RY/BY#
OE#
WE#
WP#/ACC
RESET#
UB#
LB#
March 31, 2005 S71GL032A_00_A0
S71GL032A Based MCPs
9
A d v a n c e
I n f o r m a t i o n
Ordering Information
The order number is formed by a valid combinations of the following:
S71GL
032
A
80
BA
W
0
F
0
PACKING TYPE
0
= Tray
2
= 7” Tape and Reel
3
= 13” Tape and Reel
MODEL NUMBER
See the Valid Combinations table.
PACKAGE MODIFIER
0
= 7 x 9 mm, 1.2 mm height, 56 balls (TLC056)
TEMPERATURE RANGE
W
= Wireless (-25°C to +85°C)
I
= Industrial (-40°C to +85°C)
PACKAGE TYPE
BA
= Fine-pitch BGA Lead (Pb)-free compliant package
BF
= Fine-pitch BGA Lead (Pb)-free package
pSRAM
80
=
40
=
08
=
04
=
DENSITY
8 Mb pSRAM
4 Mb pSRAM
8 Mb SRAM
4 Mb SRAM
PROCESS TECHNOLOGY
A
= 200 nm, MirrorBit Technology
FLASH DENSITY
064 = 64Mb
032 = 32Mb
PRODUCT FAMILY
S71GL Multi-chip Product (MCP)
3.0-volt Page Mode Flash Memory and RAM
10
S71GL032A_00A0 March 31, 2005
A d v a n c e
I n f o r m a t i o n
S71GL032A Valid Combinations
Base Ordering
Part Number
Package &
Temperature
Package Modifier/
Model Number
Speed Options (ns)/
Boot Sector Option
Packing Type
S71GL032A40
0B
100 / Bottom Boot Sector
S71GL032A40
0F
100 / Top Boot Sector
S71GL032A08
BAW
0B
0, 2, 3 (Note 1)
100 / Bottom Boot Sector
S71GL032A08
0F
S71GL032A40
0B
100 / Bottom Boot Sector
S71GL032A40
0F
100 / Top Boot Sector
S71GL032A08
BFW
0B
100 / Top Boot Sector
0, 2, 3 (Note 1)
100 / Bottom Boot Sector
S71GL032A08
0F
100 / Top Boot Sector
S71GL032A40
0B
100 / Bottom Boot Sector
S71GL032A40
S71GL032A08
BAI
0F
0B
0, 2, 3 (Note 1)
100 / Top Boot Sector
100 / Bottom Boot Sector
S71GL032A08
0F
S71GL032A40
0B
100 / Bottom Boot Sector
S71GL032A40
0F
100 / Top Boot Sector
S71GL032A08
BFI
S71GL032A08
0B
100 / Top Boot Sector
0, 2, 3 (Note 1)
0F
100 / Bottom Boot Sector
100 / Top Boot Sector
(p)SRAM
Type/Access
Time (ns)
Package
Marking
pSRAM4/ 70
SRAM1 / 70
pSRAM4/ 70
SRAM1 / 70
TLC056
pSRAM4/ 70
SRAM1 / 70
pSRAM4/ 70
SRAM1 / 70
Notes:
1. Type 0 is standard. Specify other options as required.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device.
Consult your local sales office to confirm availability of specific valid combinations and to
check on newly released combinations.
March 31, 2005 S71GL032A_00A0
11
A d v a n c e
I n f o r m a t i o n
Physical Dimensions
TLC056—56-ball Fine-Pitch Ball Grid Array (FBGA)
9 x 7 mm Package
D1
A
D
eD
0.15 C
(2X)
8
7
SE 7
6
5
E
E1
4
3
eE
2
1
H
INDEX MARK
PIN A1
CORNER
B
10
TOP VIEW
G
F
E
D
C B
A
PIN A1
CORNER
7
SD
0.15 C
(2X)
BOTTOM VIEW
0.20 C
A A2
A1
C
56X
0.08 C
SIDE VIEW
6
b
0.15 M C A B
0.08 M C
NOTES:
PACKAGE
TLC 056
JEDEC
N/A
DxE
9.00 mm x 7.00 mm
PACKAGE
SYMBOL
MIN
NOM
MAX
A
---
---
1.20
A1
0.20
---
---
A2
0.81
---
0.97
NOTE
PROFILE
9.00 BSC.
BODY SIZE
7.00 BSC.
BODY SIZE
D1
5.60 BSC.
MATRIX FOOTPRINT
E1
5.60 BSC.
MATRIX FOOTPRINT
MD
8
MATRIX SIZE D DIRECTION
ME
8
MATRIX SIZE E DIRECTION
56
0.35
0.40
2.
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
BALL HEIGHT
E
n
DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
BODY THICKNESS
D
φb
1.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
BALL COUNT
0.45
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eE
0.80 BSC.
BALL PITCH
eD
0.80 BSC
BALL PITCH
SD / SE
0.40 BSC.
SOLDER BALL PLACEMENT
A1,A8,D4,D5,E4,E5,H1,H8
DEPOPULATED SOLDER BALLS
8.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9.
N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3348 \ 16-038.22a
12
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
S29GL-A MirrorBit™ Flash Family
S29GL064A, S29GL032A
64 Megabit, 32 Megabit 3.0, Volt-only Page Mode Flash
Memory Featuring 200 nm MirrorBit Process Technology
Data Sheet
ADVANCE
INFORMATION
Distinctive Characteristics
Architectural Advantages

Single power supply operation
— 3 volt read, erase, and program operations

Manufactured on 200 nm MirrorBit process
technology

Secured Silicon Sector region
— 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
— May be programmed and locked at the factory or by
the customer

Software & Hardware Features

Flexible sector architecture
— 64Mb (uniform sector models): 128 32 Kword (64 KB)
sectors
— 64Mb (boot sector models): 127 32 Kword (64 KB)
sectors + 8 4Kword (8KB) boot sectors
— 32Mb (uniform sector models): 64 32Kword (64KB)
sectors
— 32Mb (boot sector models): 63 32Kword (64KB)
sectors + 8 4Kword (8KB) boot sectors

Compatibility with JEDEC standards
— Provides pinout and software compatibility for singlepower supply flash, and superior inadvertent write
protection

100,000 erase cycles typical per sector

20-year data retention typical
Performance Characteristics

High performance
— 90 ns access time
— 4-word/8-byte page read buffer
Publication Number S71GL032A_00
Revision A
— 25 ns page read times
— 16-word/32-byte write buffer which reduces overall
programming time for multiple-word updates
Low power consumption (typical values at 3.0 V, 5
MHz)
— 18 mA typical active read current
— 50 mA typical erase/program current
— 1 µA typical standby mode current
Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
— Unlock Bypass Program command reduces overall
multiple-word programming time

Hardware features
— Sector Group Protection: hardware-level method of
preventing write operations within a sector group
— Temporary Sector Unprotect: VID-level method of
charging code in locked sectors
— WP#/ACC input accelerates programming time
(when high voltage is applied) for greater throughput
during system production. Protects first or last sector
regardless of sector protection settings on uniform
sector models
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) detects program or
erase cycle completion
Amendment 0
Issue Date March 31, 2005
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not
design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
A d v a n c e
I n f o r m a t i o n
General Description
The S29GL-A family of devices are 3.0 V single power Flash memory manufactured using 200 nm MirrorBit technology. The S29GL064A is a 64 Mb, organized
as 4,194,304 words or 8,388,608 bytes. The S29GL032A is a 32 Mb, organized
as 2,097,152 words or 4,194,304 bytes. Depending on the model number, the
devices have an 8-bit wide data bus only, 16-bit wide data bus only, or a 16-bit
wide data bus that can also function as an 8-bit wide data bus by using the BYTE#
input. The devices can be programmed either in the host system or in standard
EPROM programmers.
Access times as fast as 90 ns are available. Note that each access time has a specific operating voltage range (VCC) as specified in the Product Selector Guide and
the Ordering Information sections. Package offerings include 48-pin TSOP, 56-pin
TSOP, 48-ball fine-pitch BGA and 64-ball Fortified BGA, depending on model number. Each device has separate chip enable (CE#), write enable (WE#) and output
enable (OE#) controls.
Each device requires only a single 3.0 volt power supply for both read and
write functions. In addition to a VCC input, a high-voltage accelerated program
(ACC) feature provides shorter programming times through increased current on
the WP#/ACC input. This feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired.
The device is entirely command set compatible with the JEDEC single-powersupply Flash standard. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data
needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through command sequences.
Once a program or erase operation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy#
(RY/BY#) output to determine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces command sequence overhead
by requiring only two write cycles to program data instead of four.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming
equipment.
The Erase Suspend/Erase Resume feature allows the host system to pause an
erase operation in a given sector to read or program any other sector and then
complete the erase operation. The Program Suspend/Program Resume feature enables the host system to pause a program operation in a given sector to
read any other sector and then complete the program operation.
The hardware RESET# pin terminates any operation in progress and resets the
device, after which it is then ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would thus also reset the device,
enabling the host system to read boot-up firmware from the Flash memory
device.
14
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
A d v a n c e
I n f o r m a t i o n
The device reduces power consumption in the standby mode when it detects
specific voltage levels on CE# and RESET#, or when addresses have been stable
for a specified period of time.
The Write Protect (WP#) feature protects the first or last sector by asserting
a logic low on the WP#/ACC pin or WP# pin, depending on model number. The
protected sector will still be protected even during accelerated programming.
The Secured Silicon Sector provides a 128-word/256-byte area for code or
data that can be permanently protected. Once this sector is protected, no further
changes within the sector can occur.
Spansion MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost
effectiveness. The device electrically erases all bits within a sector simultaneously
via hot-hole assisted erase. The data is programmed using hot electron injection.
March 31, 2005 S71GL032A_00_A0
S71GL032A Based MCPs
15
A d v a n c e
I n f o r m a t i o n
Product Selector Guide
S29GL064A, S29GL032A
Part Number
S29GL064A
S29GL032A
Speed Option
90
10
11
90
10
11
Max. Access Time (ns)
90
100
110
90
100
110
Max. CE# Access Time (ns)
90
100
110
90
100
110
Max. Page Access Time (ns)
25
30
30
25
30
30
Max. OE# Access Time (ns)
25
30
30
25
30
30
Block Diagram
VCC
DQ15–DQ0 (A-1)
RY/BY#
Sector Switches
VSS
Erase Voltage
Generator
RESET#
WE#
WP#/ACC
BYTE#
Input/Output
Buffers
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
VCC Detector
AMax**–A0
Timer
Address Latch
STB
STB
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
Note:
**AMAX GL064A = A21.
**AMAX GL032A = A20.
16
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
A d v a n c e
I n f o r m a t i o n
Pin Descriptions
A21–A0
A20–A0
DQ7–DQ0
DQ14–DQ0
DQ15/A-1
=
=
=
=
=
CE#
OE#
WE#
WP#/ACC
=
=
=
=
ACC
WP#
RESET#
RY/BY#
BYTE#
VCC
=
=
=
=
=
=
VSS
NC
VIO
=
=
=
March 31, 2005 S71GL032A_00_A0
22 Address inputs
21 Address inputs
8 Data inputs/outputs
15 Data inputs/outputs
DQ15 (Data input/output, word mode), A-1 (LSB
Address input, byte mode)
Chip Enable input
Output Enable input
Write Enable input
Hardware Write Protect input/Programming
Acceleration input
Acceleration input
Hardware Write Protect input
Hardware Reset Pin input
Ready/Busy output
Selects 8-bit or 16-bit mode
3.0 volt-only single power supply
(see Product Selector Guide for speed options and
voltage supply tolerances)
Device Ground
Pin Not Connected Internally
Output Buffer Power
S71GL032A Based MCPs
17
A d v a n c e
I n f o r m a t i o n
Logic Symbol-S29GL032A (Models R1, R2)
21
A20–A0
CE#
16
DQ15–DQ0
(A-1)
OE#
WE#
WP#/ACC
RESET#
BYTE#
RY/BY#
VIO
Logic Symbol-S29GL032A (Models R3, R4)
21
A20–A0
CE#
16
DQ15–DQ0
(A-1)
OE#
WE#
WP#/ACC
RESET#
RY/BY#
BYTE#
18
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
A d v a n c e
I n f o r m a t i o n
Logic Symbol-S29GL064A (Models R1, R2, R8, R9)
22
A21–A0
CE#
16
DQ15–DQ0
(A-1)
OE#
WE#
WP#/ACC
RESET#
BYTE#
RY/BY#
VIO
Logic Symbol-S29GL064A (Models R3, R4)
22
A21–A0
CE#
16
DQ15–DQ0
(A-1)
OE#
WE#
WP#/ACC
RESET#
BYTE#
March 31, 2005 S71GL032A_00_A0
RY/BY#
S71GL032A Based MCPs
19
A d v a n c e
I n f o r m a t i o n
Logic Symbol-S29GL064A (Model R5)
22
A21–A0
CE#
16
DQ15–DQ0
OE#
WE#
ACC
RESET#
VIO
RY/BY#
Logic Symbol-S29GL064A (Model R6, R7)
22
A21–A0
CE#
16
DQ15–DQ0
OE#
WE#
WP#
ACC
RESET#
VIO
20
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
A d v a n c e
I n f o r m a t i o n
Device Bus Operations
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to
the internal state machine. The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the inputs and control levels they
require, and the resulting output. The following subsections describe each of
these operations in further detail.
Table 1.
Device Bus Operations
DQ8–DQ15
Operation
CE#
OE# WE# RESET#
WP#
ACC
Addresses
(Note 1)
DQ0–
DQ7
BYTE#
= VIH
BYTE#
= VIL
Read
L
L
H
H
X
X
AIN
DOUT
DOUT
Write (Program/Erase)
L
H
L
H
(Note 3)
X
AIN
(Note 4)
(Note
4)
Accelerated Program
L
H
L
H
(Note 3)
VHH
AIN
(Note 4)
(Note
4)
VCC ±
0.3 V
X
X
VCC ±
0.3 V
X
H
X
High-Z
High-Z
High-Z
Output Disable
L
H
H
H
X
X
X
High-Z
High-Z
High-Z
Reset
X
X
X
L
X
X
X
High-Z
High-Z
High-Z
Sector Group Protect
(Note 2)
L
H
L
VID
H
X
SA, A6 =L,
A3=L, A2=L, (Note 4)
A1=H, A0=L
X
X
Sector Group
Unprotect
(Note 2)
L
H
L
VID
H
X
SA, A6=H,
A3=L, A2=L, (Note 4)
A1=H, A0=L
X
X
Temporary Sector
Group Unprotect
X
X
X
VID
H
X
(Note
4)
High-Z
Standby
AIN
(Note 4)
DQ8–DQ14
= High-Z,
DQ15 = A-1
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector
Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are Amax:A0 in word mode; Amax:A-1 in byte mode. Sector addresses are Amax:A15 in both modes.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the
“Sector Group Protection and Unprotection” section.
3. If WP# = VIL, the first or last sector remains protected (for uniform sector devices), and the two outer boot sectors
are protected (for boot sector devices). If WP# = VIH, the first or last sector, or the two outer boot sectors will be
protected or unprotected as determined by the method described in “Sector Group Protection and Unprotection”.
All sectors are unprotected when shipped from the factory (The Secured Silicon Sector may be factory protected
depending on version ordered.)
4. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 7).
March 31, 2005 S71GL032A_00_A0
S71GL032A Based MCPs
21
A d v a n c e
I n f o r m a t i o n
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or
word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ0–DQ15 are active and controlled by CE# and OE#.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE#
pins to VIL. CE# is the power control and selects the device. OE# is the output
control and gates array data to the output pins. WE# should remain at VIH.
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data on the device data
outputs. The device remains enabled for read access until the command register
contents are altered.
See “Reading Array Data” for more information. Refer to the AC Read-Only Operations table for timing specifications and the timing diagram. Refer to the DC
Characteristics table for the active current specification on reading array data.
Page Mode Read
The device is capable of fast page mode read and is compatible with the page
mode Mask ROM read operation. This mode provides faster read access speed for
random locations within a page. The page size of the device is 4 words/8 bytes.
The appropriate page is selected by the higher address bits A(max)–A2. Address
bits A1–A0 in word mode (A1–A-1 in byte mode) determine the specific word
within a page. This is an asynchronous operation; the microprocessor supplies
the specific word location.
The random or initial page access is equal to tACC or tCE and subsequent page
read accesses (as long as the locations specified by the microprocessor falls
within that page) is equivalent to tPACC. When CE# is deasserted and reasserted
for a subsequent access, the access time is tACC or tCE. Fast page mode accesses
are obtained by keeping the “read-page addresses” constant and changing the
“intra-read page” addresses.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data
to the device and erasing sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facilitate faster programming.
Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. The “Word Program Command
Sequence” section has details on programming data to the device using both
standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device.
Table 2-Table 17 indicates the address space that each sector occupies.
Refer to the DC Characteristics table for the active current specification for the
write mode. The AC Characteristics section contains timing specification tables
and timing diagrams for write operations.
22
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
A d v a n c e
I n f o r m a t i o n
Write Buffer
Write Buffer Programming allows the system write to a maximum of 16 in one
programming operation. This results in faster effective programming time than
the standard programming algorithms. See “Write Buffer” for more information.
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This
is one of two functions provided by the WP#/ACC or ACC pin, depending on model
number. This function is primarily intended to allow faster manufacturing
throughput at the factory.
If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sector
groups, and uses the higher voltage on the pin to reduce the time required for
program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/
ACC or ACC pin, depending on model number, returns the device to normal operation. Note that the WP#/ACC or ACC pin must not be at VHH for operations
other than accelerated programming, or device damage may result. WP# has an
internal pullup; when unconnected, WP# is at VIH.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal
register (which is separate from the memory array) on DQ7–DQ0. Standard read
cycle timings apply in this mode. Refer to the “Autoselect Mode” section on page
31 and “Autoselect Command Sequence” section on page 45 sections for more
information.
Standby Mode
When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
the outputs are placed in the high impedance state, independent of the OE#
input.
The device enters the CMOS standby mode when the CE# and RESET# pins are
both held at VIO ± 0.3 V. (Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within VIO ± 0.3 V, the device
will be in the standby mode, but the standby current will be greater. The device
requires standard access time (tCE) for read access when the device is in either
of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation is completed.
Refer to the “DC Characteristics” section on page 65 for the standby current
specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC +
30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses
are changed. While in sleep mode, output data is latched and always available to
March 31, 2005 S71GL032A_00_A0
S71GL032A Based MCPs
23
A d v a n c e
I n f o r m a t i o n
the system. Refer to the “DC Characteristics” section on page 65 for the
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the RESET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in progress, tristates all output
pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to
accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at VSS±0.3 V, the device draws CMOS standby current (ICC5). If RESET# is held
at VIL but not within VSS±0.3 V, the standby current will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
Refer to the AC Characteristics tables for RESET# parameters and to Figure 15
for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins
are placed in the high impedance state.
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
24
A20-A15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
S29GL032M (Models R1, R2) Sector Addresses
16-bit
Address
Range
Sector
Sector
Table 2.
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
A20-A15
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
S71GL032A Based MCPs
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
16-bit
Address
Range
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
S71GL032A_00_A0 March 31, 2005
A d v a n c e
A20–A12
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
000000xxx
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
001011xxx
001100xxx
001101xxx
001101xxx
001111xxx
010000xxx
010001xxx
010010xxx
010011xxx
010100xxx
010101xxx
010110xxx
010111xxx
011000xxx
011001xxx
011010xxx
011011xxx
011000xxx
011101xxx
011110xxx
011111xxx
100000xxx
100001xxx
100010xxx
101011xxx
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
S29GL032M (Models R3) Top Boot Sector Addresses
16-bit
Address
Range
Sector
Sector
Table 3.
I n f o r m a t i o n
A20–A12
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
F8000h–FFFFFh
F9000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
100100xxx
100101xxx
100110xxx
100111xxx
101000xxx
101001xxx
101010xxx
101011xxx
101100xxx
101101xxx
101110xxx
101111xxx
110000xxx
110001xxx
110010xxx
110011xxx
100100xxx
110101xxx
110110xxx
110111xxx
111000xxx
111001xxx
111010xxx
111011xxx
111100xxx
111101xxx
111110xxx
111111000
111111001
111111010
111111011
111111100
111111101
111111110
111111111
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
16-bit
Address
Range
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1F8FFFh
1F9000h–1F9FFFh
1FA000h–1FAFFFh
1FB000h–1FBFFFh
1FC000h–1FCFFFh
1FD000h–1FDFFFh
1FE000h–1FEFFFh
1FF000h–1FFFFFh
A20–A12
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
000000000
000000001
000000010
000000011
000000100
000000101
000000110
000000111
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
001011xxx
March 31, 2005 S71GL032A_00_A0
Sector
Size
(KB/
Kwords)
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
16-bit
Address
Range
Sector
Sector
Table 4. S29GL032M (Models R4) Bottom Boot Sector Addresses (Sheet 1 of 2)
A20–A12
00000h–00FFFh
01000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–04FFFh
05000h–05FFFh
06000h–06FFFh
07000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
001100xxx
001101xxx
001101xxx
001111xxx
010000xxx
010001xxx
010010xxx
010011xxx
010100xxx
010101xxx
010110xxx
010111xxx
011000xxx
011001xxx
011010xxx
011011xxx
011000xxx
011101xxx
011110xxx
S71GL032A Based MCPs
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
16-bit
Address
Range
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
25
A d v a n c e
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
011111xxx
100000xxx
100001xxx
100010xxx
101011xxx
100100xxx
100101xxx
100110xxx
100111xxx
101000xxx
101001xxx
101010xxx
101011xxx
101100xxx
101101xxx
101110xxx
101111xxx
26
Sector
Table 5.
A21–A15
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
0010100
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011100
0011101
0011110
0011111
0100000
0100001
0100010
0100011
0100100
16-bit
Address
Range
Sector
A20–A12
S29GL032M (Models R4) Bottom Boot Sector Addresses (Sheet 2 of 2)
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
A20–A12
F8000h–FFFFFh
F9000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
110000xxx
110001xxx
110010xxx
110011xxx
100100xxx
110101xxx
110110xxx
110111xxx
111000xxx
111001xxx
111010xxx
111011xxx
111100xxx
111101xxx
111110xxx
111111xxx
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
16-bit
Address
Range
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1FFFFFh
S29GL064A (Models R1, R2, R8, R9) Sector Addresses (Sheet 1 of 2)
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
16-bit
Address
Range
Sector
Sector
Table 4.
I n f o r m a t i o n
A21–A15
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
0100101
0100110
0100111
0101000
0101001
0101010
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
S71GL032A Based MCPs
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
16-bit
Address
Range
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
200000–207FFF
208000–20FFFF
210000–217FFF
218000–21FFFF
220000–227FFF
228000–22FFFF
230000–237FFF
238000–23FFFF
240000–247FFF
248000–24FFFF
S71GL032A_00_A0 March 31, 2005
A d v a n c e
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
1001010
1001011
1001100
1001101
1001110
1001111
1010000
1010001
1010010
1010011
1010100
1010101
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
1100000
1100001
1100010
1100011
1100100
Sector
Table 6.
A21–A15
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
0000000xxx
0000001xxx
0000010xxx
0000011xxx
0000100xxx
0000101xxx
0000110xxx
0000111xxx
0001000xxx
0001001xxx
0001010xxx
0001011xxx
0001100xxx
0001101xxx
0001101xxx
0001111xxx
0010000xxx
0010001xxx
0010010xxx
0010011xxx
0010100xxx
0010101xxx
0010110xxx
0010111xxx
0011000xxx
0011001xxx
0011010xxx
0011011xxx
0011000xxx
0011101xxx
0011110xxx
0011111xxx
0100000xxx
0100001xxx
March 31, 2005 S71GL032A_00_A0
16-bit
Address
Range
Sector
A21–A15
S29GL064A (Models R1, R2, R8, R9) Sector Addresses (Sheet 2 of 2)
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
A21–A15
250000–257FFF
258000–25FFFF
260000–267FFF
268000–26FFFF
270000–277FFF
278000–27FFFF
280000–287FFF
288000–28FFFF
290000–297FFF
298000–29FFFF
2A0000–2A7FFF
2A8000–2AFFFF
2B0000–2B7FFF
2B8000–2BFFFF
2C0000–2C7FFF
2C8000–2CFFFF
2D0000–2D7FFF
2D8000–2DFFFF
2E0000–2E7FFF
2E8000–2EFFFF
2F0000–2F7FFF
2F8000–2FFFFF
300000–307FFF
308000–30FFFF
310000–317FFF
318000–31FFFF
320000–327FFF
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
16-bit
Address
Range
328000–32FFFF
330000–337FFF
338000–33FFFF
340000–347FFF
348000–34FFFF
350000–357FFF
358000–35FFFF
360000–367FFF
368000–36FFFF
370000–377FFF
378000–37FFFF
380000–387FFF
388000–38FFFF
390000–397FFF
398000–39FFFF
3A0000–3A7FFF
3A8000–3AFFFF
3B0000–3B7FFF
3B8000–3BFFFF
3C0000–3C7FFF
3C8000–3CFFFF
3D0000–3D7FFF
3D8000–3DFFFF
3E0000–3E7FFF
3E8000–3EFFFF
3F0000–3F7FFF
3F8000–3FFFFF
S29GL064A (Model R3) Top Boot Sector Addresses (Sheet 1 of 2)
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
16-bit
Address
Range
Sector
Sector
Table 5.
I n f o r m a t i o n
A21–A15
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
F8000h–FFFFFh
F9000h–107FFFh
108000h–10FFFFh
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
0100010xxx
0101011xxx
0100100xxx
0100101xxx
0100110xxx
0100111xxx
0101000xxx
0101001xxx
0101010xxx
0101011xxx
0101100xxx
0101101xxx
0101110xxx
0101111xxx
0110000xxx
0110001xxx
0110010xxx
0110011xxx
0100100xxx
0110101xxx
0110110xxx
0110111xxx
0111000xxx
0111001xxx
0111010xxx
0111011xxx
0111100xxx
0111101xxx
0111110xxx
0111111xxx
1000000xxx
1000001xxx
1000010xxx
1000011xxx
S71GL032A Based MCPs
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
16-bit
Address
Range
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1FFFFFh
200000h–207FFFh
208000h–20FFFFh
210000h–217FFFh
218000h–21FFFFh
27
A d v a n c e
A21–A15
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
1000100xxx
1000101xxx
1000110xxx
1000111xxx
1001000xxx
1001001xxx
1001010xxx
1001011xxx
1001100xxx
1001101xxx
1001110xxx
1001111xxx
1010000xxx
1010001xxx
1010010xxx
1010011xxx
1010100xxx
1010101xxx
1010110xxx
1010111xxx
1011000xxx
1011001xxx
1011010xxx
1011011xxx
1011100xxx
1011101xxx
1011110xxx
1011111xxx
1100000xxx
1100001xxx
1100010xxx
1100011xxx
1100100xxx
1100101xxx
S29GL064A (Model R3) Top Boot Sector Addresses (Sheet 2 of 2)
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
16-bit
Address
Range
Sector
Sector
Table 6.
I n f o r m a t i o n
A21–A15
220000h–227FFFh
228000h–22FFFFh
230000h–237FFFh
238000h–23FFFFh
240000h–247FFFh
248000h–24FFFFh
250000h–257FFFh
258000h–25FFFFh
260000h–267FFFh
268000h–26FFFFh
270000h–277FFFh
278000h–27FFFFh
280000h–28FFFFh
288000h–28FFFFh
290000h–297FFFh
298000h–29FFFFh
2A0000h–2A7FFFh
2A8000h–2AFFFFh
2B0000h–2B7FFFh
2B8000h–2BFFFFh
2C0000h–2C7FFFh
2C8000h–2CFFFFh
2D0000h–2D7FFFh
2D8000h–2DFFFFh
2E0000h–2E7FFFh
2E8000h–2EFFFFh
2F0000h–2FFFFFh
2F8000h–2FFFFFh
300000h–307FFFh
308000h–30FFFFh
310000h–317FFFh
318000h–31FFFFh
320000h–327FFFh
328000h–32FFFFh
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
1100110xxx
1100111xxx
1101000xxx
1101001xxx
1101010xxx
1101011xxx
1101100xxx
1101101xxx
1101110xxx
1101111xxx
1110000xxx
1110001xxx
1110010xxx
1110011xxx
1110100xxx
1110101xxx
1110110xxx
1110111xxx
1111000xxx
1111001xxx
1111010xxx
1111011xxx
1111100xxx
1111101xxx
1111110xxx
1111111000
1111111001
1111111010
1111111011
1111111100
1111111101
1111111110
1111111111
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
16-bit
Address
Range
330000h–337FFFh
338000h–33FFFFh
340000h–347FFFh
348000h–34FFFFh
350000h–357FFFh
358000h–35FFFFh
360000h–367FFFh
368000h–36FFFFh
370000h–377FFFh
378000h–37FFFFh
380000h–387FFFh
388000h–38FFFFh
390000h–397FFFh
398000h–39FFFFh
3A0000h–3A7FFFh
3A8000h–3AFFFFh
3B0000h–3B7FFFh
3B8000h–3BFFFFh
3C0000h–3C7FFFh
3C8000h–3CFFFFh
3D0000h–3D7FFFh
3D8000h–3DFFFFh
3E0000h–3E7FFFh
3E8000h–3EFFFFh
3F0000h–3F7FFFh
3F8000h–3F8FFFh
3F9000h–3F9FFFh
3FA000h–3FAFFFh
3FB000h–3FBFFFh
3FC000h–3FCFFFh
3FD000h–3FDFFFh
3FE000h–3FEFFFh
3FF000h–3FFFFFh
A21–A15
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
0000001xxx
0000010xxx
0000011xxx
0000100xxx
0000101xxx
0000110xxx
0000111xxx
0001000xxx
0001001xxx
0001010xxx
0001011xxx
0001100xxx
0001101xxx
0001101xxx
0001111xxx
0010000xxx
0010001xxx
0010010xxx
0010011xxx
28
Sector
Size
(KB/
Kwords)
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
16-bit
Address
Range
Sector
Sector
Table 7. S29GL064A (Model R4) Bottom Boot Sector Addresses (Sheet 1 of 2)
A21–A15
00000h–00FFFh
01000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–04FFFh
05000h–05FFFh
06000h–06FFFh
07000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
0010100xxx
0010101xxx
0010110xxx
0010111xxx
0011000xxx
0011001xxx
0011010xxx
0011011xxx
0011000xxx
0011101xxx
0011110xxx
0011111xxx
0100000xxx
0100001xxx
0100010xxx
0101011xxx
0100100xxx
0100101xxx
0100110xxx
0100111xxx
0101000xxx
0101001xxx
0101010xxx
0101011xxx
0101100xxx
0101101xxx
0101110xxx
S71GL032A Based MCPs
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
16-bit
Address
Range
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
F8000h–FFFFFh
F9000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
S71GL032A_00_A0 March 31, 2005
A d v a n c e
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
0101111xxx
0110000xxx
0110001xxx
0110010xxx
0110011xxx
0100100xxx
0110101xxx
0110110xxx
0110111xxx
0111000xxx
0111001xxx
0111010xxx
0111011xxx
0111100xxx
0111101xxx
0111110xxx
0111111xxx
1000000xxx
1000001xxx
1000010xxx
1000011xxx
1000100xxx
1000101xxx
1000110xxx
1000111xxx
1001000xxx
1001001xxx
1001010xxx
1001011xxx
1001100xxx
1001101xxx
1001110xxx
1001111xxx
1010000xxx
1010001xxx
1010010xxx
1010011xxx
1010100xxx
1010101xxx
1010110xxx
1010111xxx
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
Sector
Table 8.
A21–A15
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
0010100
March 31, 2005 S71GL032A_00_A0
16-bit
Address
Range
Sector
A21–A15
S29GL064A (Model R4) Bottom Boot Sector Addresses (Sheet 2 of 2)
A21–A15
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1FFFFFh
200000h–207FFFh
208000h–20FFFFh
210000h–217FFFh
218000h–21FFFFh
220000h–227FFFh
228000h–22FFFFh
230000h–237FFFh
238000h–23FFFFh
240000h–247FFFh
248000h–24FFFFh
250000h–257FFFh
258000h–25FFFFh
260000h–267FFFh
268000h–26FFFFh
270000h–277FFFh
278000h–27FFFFh
280000h–28FFFFh
288000h–28FFFFh
290000h–297FFFh
298000h–29FFFFh
2A0000h–2A7FFFh
2A8000h–2AFFFFh
2B0000h–2B7FFFh
2B8000h–2BFFFFh
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
1011000xxx
1011001xxx
1011010xxx
1011011xxx
1011100xxx
1011101xxx
1011110xxx
1011111xxx
1100000xxx
1100001xxx
1100010xxx
1100011xxx
1100100xxx
1100101xxx
1100110xxx
1100111xxx
1101000xxx
1101001xxx
1101010xxx
1101011xxx
1101100xxx
1101101xxx
1101110xxx
1101111xxx
1110000xxx
1110001xxx
1110010xxx
1110011xxx
1110100xxx
1110101xxx
1110110xxx
1110111xxx
1111000xxx
1111001xxx
1111010xxx
1111011xxx
1111100xxx
1111101xxx
1111110xxx
1111111000
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
16-bit
Address
Range
2C0000h–2C7FFFh
2C8000h–2CFFFFh
2D0000h–2D7FFFh
2D8000h–2DFFFFh
2E0000h–2E7FFFh
2E8000h–2EFFFFh
2F0000h–2FFFFFh
2F8000h–2FFFFFh
300000h–307FFFh
308000h–30FFFFh
310000h–317FFFh
318000h–31FFFFh
320000h–327FFFh
328000h–32FFFFh
330000h–337FFFh
338000h–33FFFFh
340000h–347FFFh
348000h–34FFFFh
350000h–357FFFh
358000h–35FFFFh
360000h–367FFFh
368000h–36FFFFh
370000h–377FFFh
378000h–37FFFFh
380000h–387FFFh
388000h–38FFFFh
390000h–397FFFh
398000h–39FFFFh
3A0000h–3A7FFFh
3A8000h–3AFFFFh
3B0000h–3B7FFFh
3B8000h–3BFFFFh
3C0000h–3C7FFFh
3C8000h–3CFFFFh
3D0000h–3D7FFFh
3D8000h–3DFFFFh
3E0000h–3E7FFFh
3E8000h–3EFFFFh
3F0000h–3F7FFFh
3F8000h–3FFFFFh
S29GL064A (Model R5) Sector Addresses (Sheet 1 of 2)
16-bit
Address
Range
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
Sector
Sector
Table 7.
I n f o r m a t i o n
A21–A15
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011100
0011101
0011110
0011111
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
S71GL032A Based MCPs
16-bit
Address
Range
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
200000–207FFF
208000–20FFFF
210000–217FFF
218000–21FFFF
220000–227FFF
228000–22FFFF
230000–237FFF
238000–23FFFF
240000–247FFF
248000–24FFFF
29
A d v a n c e
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
0101010
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
1010000
1010001
1010010
1010011
1010100
30
Sector
Table 9.
A21–A15
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
0010100
16-bit
Address
Range
250000–257FFF
258000–25FFFF
260000–267FFF
268000–26FFFF
270000–277FFF
278000–27FFFF
280000–287FFF
288000–28FFFF
290000–297FFF
298000–29FFFF
2A0000–2A7FFF
2A8000–2AFFFF
2B0000–2B7FFF
2B8000–2BFFFF
2C0000–2C7FFF
2C8000–2CFFFF
2D0000–2D7FFF
2D8000–2DFFFF
2E0000–2E7FFF
2E8000–2EFFFF
2F0000–2F7FFF
2F8000–2FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
Sector
A21–A15
S29GL064A (Model R5) Sector Addresses (Sheet 2 of 2)
A21–A15
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
1010101
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
1100000
1100001
1100010
1100011
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
16-bit
Address
Range
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
300000–307FFF
308000–30FFFF
310000–317FFF
318000–31FFFF
320000–327FFF
328000–32FFFF
330000–337FFF
338000–33FFFF
340000–347FFF
348000–34FFFF
350000–357FFF
358000–35FFFF
360000–367FFF
368000–36FFFF
370000–377FFF
378000–37FFFF
380000–387FFF
388000–38FFFF
390000–397FFF
398000–39FFFF
3A0000–3A7FFF
3A8000–3AFFFF
3B0000–3B7FFF
3B8000–3BFFFF
3C0000–3C7FFF
3C8000–3CFFFF
3D0000–3D7FFF
3D8000–3DFFFF
3E0000–3E7FFF
3E8000–3EFFFF
3F0000–3F7FFF
3F8000–3FFFFF
S29GL064A (Models R6, R7) Sector Addresses (Sheet 1 of 2)
16-bit
Address
Range
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
Sector
Sector
Table 8.
I n f o r m a t i o n
A21–A15
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011100
0011101
0011110
0011111
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
S71GL032A Based MCPs
16-bit
Address
Range
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
200000–207FFF
208000–20FFFF
210000–217FFF
218000–21FFFF
220000–227FFF
228000–22FFFF
230000–237FFF
238000–23FFFF
240000–247FFF
248000–24FFFF
S71GL032A_00_A0 March 31, 2005
A d v a n c e
A21–A15
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
0101010
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
1010000
1010001
1010010
1010011
1010100
S29GL064A (Models R6, R7) Sector Addresses (Sheet 2 of 2)
16-bit
Address
Range
250000–257FFF
258000–25FFFF
260000–267FFF
268000–26FFFF
270000–277FFF
278000–27FFFF
280000–287FFF
288000–28FFFF
290000–297FFF
298000–29FFFF
2A0000–2A7FFF
2A8000–2AFFFF
2B0000–2B7FFF
2B8000–2BFFFF
2C0000–2C7FFF
2C8000–2CFFFF
2D0000–2D7FFF
2D8000–2DFFFF
2E0000–2E7FFF
2E8000–2EFFFF
2F0000–2F7FFF
2F8000–2FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
Sector
Sector
Table 9.
I n f o r m a t i o n
A21–A15
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
1010101
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
1100000
1100001
1100010
1100011
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
16-bit
Address
Range
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
300000–307FFF
308000–30FFFF
310000–317FFF
318000–31FFFF
320000–327FFF
328000–32FFFF
330000–337FFF
338000–33FFFF
340000–347FFF
348000–34FFFF
350000–357FFF
358000–35FFFF
360000–367FFF
368000–36FFFF
370000–377FFF
378000–37FFFF
380000–387FFF
388000–38FFFF
390000–397FFF
398000–39FFFF
3A0000–3A7FFF
3A8000–3AFFFF
3B0000–3B7FFF
3B8000–3BFFFF
3C0000–3C7FFF
3C8000–3CFFFF
3D0000–3D7FFF
3D8000–3DFFFF
3E0000–3E7FFF
3E8000–3EFFFF
3F0000–3F7FFF
3F8000–3FFFFF
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector
group protection verification, through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment to automatically match a
device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command
register.
To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 22. Refer to the
Autoselect Command Sequence section for more information.
Sector Group Protection and Unprotection
The hardware sector group protection feature disables both program and erase
operations in any sector group (see Table 9-Table 17). The hardware sector group
unprotection feature re-enables both program and erase operations in previously
March 31, 2005 S71GL032A_00_A0
S71GL032A Based MCPs
31
A d v a n c e
I n f o r m a t i o n
protected sector groups. Sector group protection/unprotection can be implemented via two methods.
Sector protection/unprotection requires VID on the RESET# pin only, and can be
implemented either in-system or via programming equipment. Figure 2 shows
the algorithms and Figure 24 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector group unprotect, all unprotected
sector groups must first be protected prior to the first sector group unprotect
write cycle.
The device is shipped with all sector groups unprotected. Spansion offers the option of programming and protecting sector groups at its factory prior to shipping
the device through Spansion Programming Service. Contact a Spansion representative for details.
It is possible to determine whether a sector group is protected or unprotected.
See the Autoselect Mode section for details.
Table 10.
Sector Group
SA0
SA1
SA2
SA3
SA4–SA7
SA8–SA11
S29GL032A (Models R1, R2) Sector Group Protection/Unprotection Addresses
A20–A15
000000
000001
000010
000011
0001xx
0010xx
Sector Group
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
SA32–SA35
A20–A15
0011xx
0100xx
0101xx
0110xx
0111xx
1000xx
Sector Group
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
A20–A15
1001xx
1010xx
1011xx
1100xx
1101xx
Sector Group
SA56–SA59
SA60
SA61
SA62
SA63
A20–A15
1110xx
111100
111101
111110
111111
Table 11. S29GL032A (Models R3) Sector Group Protection/Unprotection Address Table
Sector
A20–A12
SA0-SA3
SA4-SA7
SA8-SA11
SA12-SA15
SA16-SA19
SA20-SA23
SA24-SA27
SA28-SA31
SA32–SA35
0000XXXXXh
0001XXXXXh
0010XXXXXh
0011XXXXXh
0100XXXXXh
0101XXXXXh
0110XXXXXh
0111XXXXXh
1000XXXXXh
Sector/Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
Sector
A20–A12
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52-SA55
SA56-SA59
1001XXXXXh
1010XXXXXh
1011XXXXXh
1100XXXXXh
1101XXXXXh
1110XXXXXh
111100XXXh
111101XXXh
111110XXXh
SA60-SA62
Sector/Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
192 (3x64)
Sector
A20–A12
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
111111000h
111111001h
111111010h
111111011h
111111100h
111111101h
111111110h
111111111h
Sector/Sector
Block Size
(Kbytes)
8
8
8
8
8
8
8
8
Table 12. S29GL032A (Models R4) Sector Group Protection/Unprotection Address Table
Sector
A20–A12
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
000000000h
000000001h
000000010h
000000011h
000000100h
000000101h
000000110h
000000111h
Sector/Sector
Block Size
(Kbytes)
8
8
8
8
8
8
8
8
Sector
SA8–SA10
SA11–SA14
SA15–SA18
SA19–SA22
SA23–SA26
SA27-SA30
SA31-SA34
A20–A12
000001XXXh
000010XXXh
000011XXXh
0001XXXXXh
0010XXXXXh
0011XXXXXh
0100XXXXXh
0101XXXXXh
0110XXXXXh
Sector/Sector
Block Size
(Kbytes)
192 (3x64)
256
256
256
256
256
256
(4x64)
(4x64)
(4x64)
(4x64)
(4x64)
(4x64)
Sector
A20–A12
SA35-SA38
SA39-SA42
SA43-SA46
SA47-SA50
SA51-SA54
SA55–SA58
SA59–SA62
SA63–SA66
SA67–SA70
0111XXXXXh
1000XXXXXh
1001XXXXXh
1010XXXXXh
1011XXXXXh
1100XXXXXh
1101XXXXXh
1110XXXXXh
1111XXXXXh
Sector/Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
Table 13. S29GL064A (Models R1, R2, R8, R9) Sector Group Protection/Unprotection Addresses
Sector Group
SA0
SA1
SA2
SA3
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
32
A21–A15
0000000
0000001
0000010
0000011
00001xx
00010xx
00011xx
00100xx
00101xx
00110xx
Sector Group
SA28–SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
SA64–SA67
A21–A15
00111xx
01000xx
01001xx
01010xx
01011xx
01100xx
01101xx
01110xx
01111xx
10000xx
Sector Group
SA68–SA71
SA72–SA75
SA76–SA79
SA80–SA83
SA84–SA87
SA88–SA91
SA92–SA95
SA96–SA99
SA100–SA103
SA104–SA107
S71GL032A Based MCPs
A21–A15
10001xx
10010xx
10011xx
10100xx
10101xx
10110xx
10111xx
11000xx
11001xx
11010xx
Sector Group
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124
SA125
SA126
SA127
A21–A15
11011xx
11100xx
11101xx
11110xx
1111100
1111101
1111110
1111111
S71GL032A_00_A0 March 31, 2005
A d v a n c e
March 31, 2005 S71GL032A_00_A0
I n f o r m a t i o n
S71GL032A Based MCPs
33
A d v a n c e
I n f o r m a t i o n
Table 14. S29GL064A (Model R3) Top Boot Sector Protection/Unprotection Addresses
Sector/Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
Sector
A20–A12
SA56-SA59
SA60-SA63
SA64-SA67
SA12-SA15 00011XXXXX
256 (4x64)
SA16-SA19
SA20-SA23
SA24-SA27
SA28-SA31
SA32-SA35
SA36-SA39
SA40-SA43
SA44-SA47
SA48-SA51
SA52-SA55
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
Sector
A21–A12
SA0-SA3
SA4-SA7
SA8-SA11
00000XXXXX
00001XXXXX
00010XXXXX
00100XXXXX
00101XXXXX
00110XXXXX
00111XXXXX
01000XXXXX
01001XXXXX
01010XXXXX
01011XXXXX
01100XXXXX
01101XXXXX
Table 15.
A21–A12
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
0000001XXX,
0000010XXX,
0000011XXX,
00001XXXXX
00010XXXXX
00011XXXXX
00100XXXXX
00101XXXXX
SA11–SA14
SA15–SA18
SA19–SA22
SA23–SA26
SA27-SA30
A20–A12
SA112-SA115
SA116-SA119
SA120-SA123
SA68-SA71
10001XXXXX
256 (4x64)
SA124-SA126
SA72-SA75
SA76-SA79
SA80-SA83
SA84-SA87
SA88-SA91
SA92-SA95
SA96-SA99
SA100-SA103
SA104-SA107
SA108-SA111
10010XXXXX
10011XXXXX
10100XXXXX
10101XXXXX
10110XXXXX
10111XXXXX
11000XXXXX
11001XXXXX
11010XXXXX
11011XXXXX
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
11100XXXXX
11101XXXXX
11110XXXXX
1111100XXX
1111101XXX
1111110XXX
1111111000
1111111001
1111111010
1111111011
1111111100
1111111101
1111111110
1111111111
Sector/Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
192 (3x64)
8
8
8
8
8
8
8
8
S29GL064A (Model R4) Bottom Boot Sector Protection/Unprotection Addresses
Sector
SA8–SA10
Sector
01110XXXXX
01111XXXXX
10000XXXXX
Sector/Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
Sector/Sector
Block Size
(Kbytes)
8
8
8
8
8
8
8
8
Sector
A20–A12
SA31-SA34
SA35-SA38
SA39-SA42
SA43-SA46
SA47-SA50
SA51-SA54
SA55–SA58
SA59–SA62
00110XXXXX
00111XXXXX
01000XXXXX
01001XXXXX
01010XXXXX
01011XXXXX
01100XXXXX
01101XXXXX
Sector/Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
192 (3x64)
SA63–SA66
01110XXXXX
256 (4x64)
SA119–SA122 11100XXXXX
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA67–SA70
SA71–SA74
SA75–SA78
SA79–SA82
SA83–SA86
01111XXXXX
10000XXXXX
10001XXXXX
10010XXXXX
10011XXXXX
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA123–SA126 11101XXXXX
SA127–SA130 11110XXXXX
SA131–SA134 11111XXXXX
256 (4x64)
256 (4x64)
256 (4x64)
Sector
A20–A12
SA87–SA90
SA91–SA94
SA95–SA98
SA99–SA102
SA103–SA106
SA107–SA110
SA111–SA114
SA115–SA118
10100XXXXX
10101XXXXX
10110XXXXX
10111XXXXX
11000XXXXX
11001XXXXX
11010XXXXX
11011XXXXX
Sector/Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
Table 16. S29GL064A (Model R5) Sector Group Protection/Unprotection Addresses
Sector Group
SA0–SA3
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
A21–A15
00000
00001
00010
00011
00100
00101
00110
00111
Sector Group
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
A21–A15
01000
01001
01010
01011
01100
01101
01110
01111
Sector Group
SA64–SA67
SA68–SA71
SA72–SA75
SA76–SA79
SA80–SA83
SA84–SA87
SA88–SA91
SA92–SA95
A21–A15
10000
10001
10010
10011
10100
10101
10110
10111
Sector Group
SA96–SA99
SA100–SA103
SA104–SA107
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124–SA127
A21–A15
11000
11001
11010
11011
11100
11101
11110
11111
Note: All sector groups are 128 Kwords in size.
Table 17. S29GL064A (Models R6, R7) Sector Group Protection/Unprotection Addresses
Sector Group
SA0–SA3
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
A21–A15
00000
00001
00010
00011
00100
00101
00110
00111
Sector Group
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
A21–A15
01000
01001
01010
01011
01100
01101
01110
01111
Sector Group
SA64–SA67
SA68–SA71
SA72–SA75
SA76–SA79
SA80–SA83
SA84–SA87
SA88–SA91
SA92–SA95
A21–A15
10000
10001
10010
10011
10100
10101
10110
10111
Sector Group
SA96–SA99
SA100–SA103
SA104–SA107
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124–SA127
A21–A15
11000
11001
11010
11011
11100
11101
11110
11111
Note: All sector groups are 128 Kwords in size.
34
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
A d v a n c e
I n f o r m a t i o n
Temporary Sector Group Unprotect
This feature allows temporary unprotection of previously protected sector groups
to change data in-system. The Sector Group Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sector groups
can be programmed or erased by selecting the sector group addresses. Once VID
is removed from the RESET# pin, all the previously protected sector groups are
protected again. Figure 1 shows the algorithm, and Figure 22 shows the timing
diagrams, for this feature.
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Group Unprotect Completed
(Note 2)
Notes:
1. All protected sector groups unprotected (If WP# = VIL, the highest or lowest address sector will remain protected for
uniform sector devices; the top or bottom two address sectors will remain protected for boot sector devices).
2. All previously protected sector groups are protected once again.
Figure 1.
March 31, 2005 S71GL032A_00_A0
Temporary Sector Group Unprotect Operation
S71GL032A Based MCPs
35
A d v a n c e
I n f o r m a t i o n
START
START
PLSCNT = 1
RESET# = VID
Wait 1 µs
Temporary Sector
Group Unprotect
Mode
No
PLSCNT = 1
Protect all sector
groups: The indicated
portion of the sector
group protect algorithm
must be performed for all
unprotected sector
groups prior to issuing
the first sector group
unprotect address
RESET# = VID
Wait 1 µs
Temporary Sector
Group Unprotect
Mode
Yes
Yes
Set up sector
group address
No
All sector
groups
protected?
Yes
Sector Group Protect:
Write 60h to sector
group address with
A6–A0 = 0xx0010
Set up first sector
group address
Sector Group
Unprotect:
Write 60h to sector
group address with
A6–A0 = 1xx0010
Wait 150 µs
Verify Sector Group
Protect: Write 40h
to sector group
address with
A6–A0 = 0xx0010
Increment
PLSCNT
No
First Write
Cycle = 60h?
First Write
Cycle = 60h?
Reset
PLSCNT = 1
Read from
sector group address
with A6–A0
= 0xx0010
Wait 15 ms
Verify Sector Group
Unprotect: Write
40h to sector group
address with
A6–A0 = 1xx0010
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector group
address with
A6–A0 = 1xx0010
Data = 01h?
Yes
No
Yes
Device failed
Protect
another
sector group?
Yes
PLSCNT
= 1000?
No
Yes
Remove VID
from RESET#
Device failed
Write reset
command
Sector Group
Protect
Algorithm
Set up
next sector group
address
No
Data = 00h?
Yes
Last sector
group
verified?
No
Yes
Sector Group
Protect complete
Sector Group
Unprotect
Algorithm
Remove VID
from RESET#
Write reset
command
Sector Group
Unprotect complete
Figure 2.
36
In-System Sector Group Protect/Unprotect Algorithms
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Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector feature provides a Flash memory region that enables
permanent part identification through an Electronic Serial Number (ESN). The
Secured Silicon Sector is 256 bytes in length, and uses a Secured Silicon Sector
Indicator Bit (DQ7) to indicate whether or not the Secured Silicon Sector is locked
when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the
security of the ESN once the product is shipped to the field.
The factory offers the device with the Secured Silicon Sector either customer
lockable (standard shipping option) or factory locked (contact a Spansion sales
representative for ordering information). The customer-lockable version is
shipped with the Secured Silicon Sector unprotected, allowing customers to program the sector after receiving the device. The customer-lockable version also
has the Secured Silicon Sector Indicator Bit permanently set to a “0.” The factorylocked version is always protected when shipped from the factory, and has the
Secured Silicon Sector Indicator Bit permanently set to a “1.” Thus, the Secured
Silicon Sector Indicator Bit prevents customer-lockable devices from being used
to replace devices that are factory locked. Note that the ACC function and unlock
bypass modes are not available when the Secured Silicon Sector is enabled.
The Secured Silicon sector address space in this device is allocated as follows:
Secured Silicon Sector
Address Range
x16
Standard Factory
Locked
ExpressFlash Factory
Locked
000000h–000007h
ESN
ESN or determined by
customer
000008h–00007Fh
Unavailable
Determined by customer
Customer Lockable
Determined by customer
The system accesses the Secured Silicon Sector through a command sequence
(see “Write Protect (WP#)”). After the system has written the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using
the addresses normally occupied by the first sector (SA0). This mode of operation
continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device. On power-up, or following a
hardware reset, the device reverts to sending commands to sector SA0.
Customer Lockable: Secured Silicon Sector NOT Programmed or
Protected At the Factory
Unless otherwise specified, the device is shipped such that the customer may
program and protect the 256-byte Secured Silicon sector.
The system may program the Secured Silicon Sector using the write-buffer, accelerated and/or unlock bypass methods, in addition to the standard
programming command sequence. See “Command Definitions” .
Programming and protecting the Secured Silicon Sector must be used with caution since, once protected, there is no procedure available for unprotecting the
Secured Silicon Sector area and none of the bits in the Secured Silicon Sector
memory space can be modified in any way.
The Secured Silicon Sector area can be protected using one of the following
procedures:
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Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in
Figure 2, except that RESET# may be at either VIH or VID. This allows in-system protection of the Secured Silicon Sector without raising any device pin to
a high voltage. Note that this method is only applicable to the Secured Silicon
Sector.
Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then use the alternate method of sector protection described in
the “Sector Group Protection and Unprotection” section.
Once the Secured Silicon Sector is programmed, locked and verified, the system
must write the Exit Secured Silicon Sector Region command sequence to return
to reading and writing within the remainder of the array.
Factory Locked: Secured Silicon Sector Programmed and
Protected At the Factory
In devices with an ESN, the Secured Silicon Sector is protected when the device
is shipped from the factory. The Secured Silicon Sector cannot be modified in any
way. An ESN Factory Locked device has an 16-byte random ESN at addresses
000000h–000007h. Please contact your sales representative for details on ordering ESN Factory Locked devices.
Customers may opt to have their code programmed by the factory through the
Spansion programming service (Customer Factory Locked). The devices are then
shipped from the factory with the Secured Silicon Sector permanently locked.
Contact your sales representative for details on using the Spansion programming
service.
Write Protect (WP#)
The Write Protect function provides a hardware method of protecting the first or
last sector group without using VID. Write Protect is one of two functions provided
by the WP#/ACC input.
If the system asserts VIL on the WP#/ACC pin, the device disables program and
erase functions in the first or last sector group independently of whether those
sector groups were protected or unprotected. Note that if WP#/ACC is at VIL
when the device is in the standby mode, the maximum input load current is increased. See the table in “DC Characteristics” section on page 65.
If the system asserts VIH on the WP#/ACC pin, the device reverts to
whether the first or last sector was previously set to be protected or unprotected using the method described in “Sector Group Protection and
Unprotection”. Note that WP# has an internal pullup; when unconnected, WP# is at VIH.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing
provides data protection against inadvertent writes (refer to Table 22 for command definitions). In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might otherwise be caused by
spurious system level signals during VCC power-up and power-down transitions,
or from system noise.
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Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all
internal program/erase circuits are disabled, and the device resets to the read
mode. Subsequent writes are ignored until VCC is greater than VLKO. The system
must provide the proper signals to the control pins to prevent unintentional writes
when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write
cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# =
VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept
commands on the rising edge of WE#. The internal state machine is automatically
reset to the read mode on power-up.
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Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system
software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can
standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query
command, 98h, to address 55h, any time the device is ready to read array data.
The system can read CFI information at the addresses given in Table 18-Table 21.
To terminate reading CFI data, the system must write the reset command.
The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read
CFI data at the addresses given in Table 18-Table 21. The system must write the
reset command to return the device to reading array data.
For further information, please refer to the CFI Specification and CFI Publication
100. Alternatively, contact your sales representative for copies of these
documents.
Table 18. CFI Query Identification String
40
Addresses
(x16)
Data
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
Description
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Table 19.
System Interface String
Addresses
(x16)
Data
1Bh
0027h
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
0036h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh
0000h
VPP Min. voltage (00h = no VPP pin present)
1Eh
0000h
VPP Max. voltage (00h = no VPP pin present)
1Fh
0007h
Reserved for future use
20h
0007h
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h
000Ah
Typical timeout per individual block erase 2N ms
22h
0000h
Typical timeout for full chip erase 2N ms (00h = not supported)
23h
0001h
Reserved for future use
24h
0005h
Max. timeout for buffer write 2N times typical
25h
0004h
Max. timeout per individual block erase 2N times typical
26h
0000h
Max. timeout for full chip erase 2N times typical (00h = not supported)
Description
Note: CFI data related to VCC and time-outs may differ from actual VCC and time-outs of the product. Please consult the Ordering
Information tables to obtain the VCC range for particular part numbers. Please consult the Erase and Programming Performance table
for typical timeout specifications.
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Table 20. Device Geometry Definition
Addresses
(x16)
Data
Description
Device Size = 2 byte
N
27h
00xxh
0017h = 64 Mb, 0016h = 32Mb
Flash Device Interface description (refer to CFI publication 100)
28h
29h
000xh
0000h
0000h = x8-only bus devices
0001h = x16-only bus devices
0002h = x8/x16 bus devices
42
2Ah
2Bh
0005h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
00xxh
Number of Erase Block Regions within device (01h = uniform device,
02h = boot device)
2Dh
2Eh
2Fh
30h
00xxh
000xh
00x0h
000xh
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
007Fh, 0000h, 0020h, 0000h = 32 Mb (-R1, -R2)
003Fh, 0000h, 0001h = 32 Mb (-R3, R4)
007Fh, 0000h, 0020h, 0000h = 64 Mb (-R1, -R2, -R8, -R9)
007Fh, 0000h, 0000h, 0001h = 64 Mb (-R3, -R4, -R5, -R6, -R7)
31h
32h
33h
34h
00xxh
0000h
0000h
000xh
Erase Block Region 2 Information (refer to CFI publication 100)
003Eh, 0000h, 0000h, 0001h = 32 Mb (-R1, -R2)
007Eh, 0000h, 0000h, 0001h = 64 Mb (-R1, -R2, -R8, -R9)
0000h, 0000h, 0000h, 0000h = all others
35h
36h
37h
38h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information (refer to CFI publication 100)
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
Erase Block Region 4 Information (refer to CFI publication 100)
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Table 21. Primary Vendor-Specific Extended Query
Addresses
(x16)
Data
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
0031h
Major version number, ASCII
44h
0033h
Minor version number, ASCII
Description
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
000xh
46h
0002h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h
0001h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h
0001h
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h
0004h
Sector Protect/Unprotect scheme
0004h = Standard Mode (Refer to Text)
4Ah
0000h
Simultaneous Operation
00 = Not Supported, X = Number of Sectors in Bank
4Bh
0000h
Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch
0001h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
4Dh
00B5h
4Eh
00C5h
4Fh
00xxh
50h
0001h
Process Technology (Bits 7-2) 0010b = 200 nm MirrorBit
0009h = x8-only bus devices
0008h = all other devices
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
March 31, 2005 S71GL032A_00_A0
02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Uniform
sectors bottom WP# protect, 05h = Uniform sectors top WP# protect
Program Suspend
00h = Not Supported, 01h = Supported
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Command Definitions
Writing specific address and data commands or sequences into the command
register initiates device operations. Table 22 defines the valid register command
sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is
then required to return the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens
later. All data is latched on the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing diagrams.
Reading Array Data
The device is automatically set to reading array data after device power-up. No
commands are required to retrieve data. The device is ready to read array data
after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the
erase-suspend-read mode, after which the system can read data from any nonerase-suspended sector. After completing a programming operation in the Erase
Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more
information.
The system must issue the reset command to return the device to the read (or
erase-suspend-read) mode if DQ5 goes high during an active program or erase
operation, or if the device is in the autoselect mode. See the next section, Reset
Command, for more information.
See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations–“AC Characteristics”
section on page 67 provides the read parameters, and Figure 13 shows the timing
diagram.
Reset Command
Writing the reset command resets the device to the read or erase-suspend-read
mode. Address bits are don’t cares for this command.
The reset command may be written between the sequence cycles in an erase
command sequence before erasing begins. This resets the device to the read
mode. Once erasure begins, however, the device ignores reset commands until
the operation is complete.
The reset command may be written between the sequence cycles in a program
command sequence before programming begins. This resets the device to the
read mode. If the program command sequence is written while the device is in
the Erase Suspend mode, writing the reset command returns the device to the
erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect
command sequence. Once in the autoselect mode, the reset command must be
written to return to the read mode. If the device entered the autoselect mode
while in the Erase Suspend mode, writing the reset command returns the device
to the erase-suspend-read mode.
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If DQ5 goes high during a program or erase operation, writing the reset command
returns the device to the read mode (or erase-suspend-read mode if the device
was in Erase Suspend).
Note that if DQ1 goes high during a Write Buffer Programming operation, the system must write the Write-to-Buffer-Abort Reset command sequence to reset the
device for the next operation.
Autoselect Command Sequence
The autoselect command sequence allows the host system to read several identifier codes at specific addresses:
Identifier Code
A7:A0
(x16)
A6:A-1
(x8)
Manufacturer ID
00h
00h
Device ID, Cycle 1
01h
02h
Device ID, Cycle 2
0Eh
1Ch
Device ID, Cycle 3
0Fh
1Eh
Secured Silicon Sector Factory Protect
03h
06h
Sector Protect Verify
(SA)02h
(SA)04h
Note: The device ID is read over three cycles. SA = Sector Address
The autoselect command sequence is initiated by first writing two unlock cycles.
This is followed by a third write cycle that contains the autoselect command. The
device then enters the autoselect mode. The system may read at any address any
number of times without initiating another autoselect command sequence:
The system must write the reset command to return to the read mode (or erasesuspend-read mode if the device was previously in Erase Suspend).
Enter Secured Silicon Sector/Exit Secured Silicon
Sector Command Sequence
The Secured Silicon Sector region provides a secured data area containing an 8word random Electronic Serial Number (ESN). The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon
Sector command sequence. The device continues to access the Secured Silicon
Sector region until the system issues the four-cycle Exit Secured Silicon Sector
command sequence. The Exit Secured Silicon Sector command sequence returns
the device to normal operation. Table 22 shows the address and data requirements for both command sequences. See also “Secured Silicon Sector Flash
Memory Region” for further information. Note that the ACC function and unlock
bypass modes are not available when the Secured Silicon Sector is enabled.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is
initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the
Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program
pulses and verifies the programmed cell margin. Table 22 shows the address and
data requirements for the word program command sequence, respectively.
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When the Embedded Program algorithm is complete, the device then returns to
the read mode and addresses are no longer latched. The system can determine
the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits. Any commands
written to the device during the Embedded Program Algorithm are ignored. Note
that the Secured Silicon Sector, autoselect, and CFI functions are unavailable
when a program operation is in progress. Note that a hardware reset immediately terminates the program operation. The program command sequence should
be reinitiated once the device has returned to the read mode, to ensure data
integrity.
Programming is allowed in any sequence of address locations and across sector
boundaries. Programming to the same word address multiple times without intervening erases (incremental bit programming) requires a modified
programming method. For such application requirements, please contact your
local Spansion representative. Word programming is supported for backward
compatibility with existing Flash driver software and for occasional writing of individual words. Use of write buffer programming (see below) is strongly
recommended for general programming use when more than a few words are to
be programmed. The effective word programming time using write buffer programming is approximately four times shorter than the single word programming
time.
Any bit in a word cannot be programmed from “0” back to a “1.” Attempting to do so may cause the device to set DQ5=1, or cause DQ7 and DQ6 status
bits to indicate the operation was successful. However, a succeeding read will
show that the data is still “0.” Only erase operations can convert a “0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to the device
faster than using the standard program command sequence. The unlock bypass
command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle containing the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle unlock bypass mode command
sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle
contains the program address and data. Additional data is programmed in the
same manner. This mode dispenses with the initial two unlock cycles required in
the standard program command sequence, resulting in faster total programming
time.Table 22 shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. The first cycle
must contain the data 90h. The second cycle must contain the data 00h. The device then returns to the read mode.
Write Buffer Programming
Write Buffer Programming allows the system write to a maximum of 16 in one
programming operation. This results in faster effective programming time than
the standard programming algorithms. The Write Buffer Programming command
sequence is initiated by first writing two unlock cycles. This is followed by a third
write cycle containing the Write Buffer Load command written at the Sector Address in which programming will occur. The fourth cycle writes the sector address
and the number of word locations, minus one, to be programmed. For example,
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if the system will program 6 unique address locations, then 05h should be written
to the device. This tells the device how many write buffer addresses will be loaded
with data and therefore when to expect the Program Buffer to Flash command.
The number of locations to program cannot exceed the size of the write buffer or
the operation will abort.
The fifth cycle writes the first address location and data to be programmed. The
write-buffer-page is selected by address bits AMAX–A4. All subsequent address/
data pairs must fall within the selected-write-buffer-page. The system then
writes the remaining address/data pairs into the write buffer. Write buffer locations may be loaded in any order.
The write-buffer-page address must be the same for all address/data pairs loaded
into the write buffer. (This means Write Buffer Programming cannot be performed
across multiple write-buffer pages.) This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load
programming data outside of the selected write-buffer page, the operation will
abort.
Note that if a Write Buffer address location is loaded multiple times, the address/
data pair counter will be decremented for every data load operation. The host
system must therefore account for loading a write-buffer location more than
once. The counter decrements for each data load operation, not for each unique
write-buffer-address location. Note also that if an address location is loaded more
than once into the buffer, the final data loaded for that address will be
programmed.
Once the specified number of write buffer locations have been loaded, the system
must then write the Program Buffer to Flash command at the sector address. Any
other address and data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while
monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5,
and DQ1 should be monitored to determine the device status during Write Buffer
Programming.
The write-buffer programming operation can be suspended using the standard
program suspend/resume commands. Upon successful completion of the Write
Buffer Programming operation, the device is ready to execute the next command.
The Write Buffer Programming Sequence can be aborted in the following ways:
Load a value that is greater than the page buffer size during the Number of
Locations to Program step.
Write to an address in a sector different than the one specified during the
Write-Buffer-Load command.
Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data loading stage of
the operation.
Write data other than the Confirm Command after the specified number of
data load cycles.
The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address
location loaded), DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the device for the next operation.
Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when a program operation is in progress.This flash device is capable of
handling multiple write buffer programming operations on the same write buffer
address range without intervening erases. For applications requiring incremental
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bit programming, a modified programming method is required; please contact
your local Spansion representative. Any bit in a write buffer address range
cannot be programmed from “0” back to a “1.” Attempting to do so may
cause the device to set DQ5=1, of cause the DQ7 and DQ6 status bits to indicate
the operation was successful. However, a succeeding read will show that the data
is still “0.” Only erase operations can convert a “0” to a “1.”
Accelerated Program
The device offers accelerated program operations through the WP#/ACC or ACC
pin depending on the particular product. When the system asserts VHH on the
WP#/ACC or ACC pin. The device uses the higher voltage on the WP#/ACC or ACC
pin to accelerate the operation. Note that the WP#/ACC pin must not be at VHH
for operations other than accelerated programming, or device damage may result. WP# has an internal pullup; when unconnected, WP# is at VIH.
Figure 3 illustrates the algorithm for the program operation. Refer to the Erase
and Program Operations–“AC Characteristics” section on page 67 section for parameters, and Figure 14 for timing diagrams.
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Write “Write to Buffer”
command and
Sector Address
Part of “Write to Buffer”
Command Sequence
Write number of addresses
to program minus 1(WC)
and Sector Address
Write first address/data
Yes
WC = 0 ?
No
Abort Write to
Buffer Operation?
Write to a different
sector address
Yes
Write to buffer ABORTED.
Must write “Write-to-buffer
Abort Reset” command
sequence to return
to read mode.
No
Write next address/data pair
(Note 1)
WC = WC - 1
Write program buffer to
flash sector address
Read DQ7 - DQ0 at
Last Loaded Address
DQ7 = Data?
No
Yes
No
No
DQ1 = 1?
DQ5 = 1?
Yes
Yes
Read DQ7 - DQ0 with
address = Last Loaded
Address
(Note 2)
DQ7 = Data?
Yes
No
(Note 3)
FAIL or ABORT
PASS
Notes:
1. When Sector Address is specified, any address in the selected sector is acceptable. However, when loading Write-Buffer
address locations with data, all addresses must fall within the selected Write-Buffer Page.
2. DQ7 may change simultaneously with DQ5. Therefore, DQ7 should be verified.
3. If this flowchart location was reached because DQ5= “1”, then the device FAILED. If this flowchart location was reached
because DQ1= “1”, then the Write to Buffer operation was ABORTED. In either case, the proper reset command must be
written before the device can begin another operation. If DQ1=1, write the Write-Buffer-Programming-Abort-Reset
command. if DQ5=1, write the Reset command.
4. See Table 22 for command sequences required for write buffer programming.
Figure 3. Write Buffer Programming Operation
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START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
Increment Address
No
Last Address?
Yes
Programming
Completed
Note:See Table 22 for program command sequence.
Figure 4. Program Operation
Program Suspend/Program Resume Command Sequence
The Program Suspend command allows the system to interrupt a programming
operation or a Write to Buffer programming operation so that data can be read
from any non-suspended sector. When the Program Suspend command is written
during a programming process, the device halts the program operation within 15
µs maximum (5µs typical) and updates the status bits. Addresses are not required when writing the Program Suspend command.
After the programming operation has been suspended, the system can read array
data from any non-suspended sector. The Program Suspend command may also
be issued during a programming operation while an erase is suspended. In this
case, data may be read from any addresses not in Erase Suspend or Program
Suspend. If a read is needed from the Secured Silicon Sector area (One-time Program area), then user must use the proper command sequences to enter and exit
this region. Note that the Secured Silicon Sector, autoselect, and CFI functions
are unavailable when a program operation is in progress.
The system may also write the autoselect command sequence when the device
is in the Program Suspend mode. The system can read as many autoselect codes
as required. When the device exits the autoselect mode, the device reverts to the
Program Suspend mode, and is ready for another valid operation. See Autoselect
Command Sequence for more information.
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After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status for more information.
The system must write the Program Resume command (address bits are don’t
care) to exit the Program Suspend mode and continue the programming operation. Further writes of the Resume command are ignored. Another Program
Suspend command can be written after the device has resumed programming.
Program Operation
or Write-to-Buffer
Sequence in Progress
Write address/data
XXXh/B0h
Write Program Suspend
Command Sequence
Command is also valid for
Erase-suspended-program
operations
Wait 15 µs
Read data as
required
No
Autoselect and SecSi Sector
read operations are also allowed
Data cannot be read from erase- or
program-suspended sectors
Done
reading?
Yes
Write address/data
XXXh/30h
Write Program Resume
Command Sequence
Device reverts to
operation prior to
Program Suspend
Figure 5.
Program Suspend/Program Resume
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 22 shows the address and data requirements
for the chip erase command sequence.
When the Embedded Erase algorithm is complete, the device returns to the read
mode and addresses are no longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, or DQ2. Refer to the Write Operation
Status section for information on these status bits.
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Any commands written during the chip erase operation are ignored. However,
note that a hardware reset immediately terminates the erase operation. If that
occurs, the chip erase command sequence should be reinitiated once the device
has returned to reading array data, to ensure data integrity.
Figure 6 illustrates the algorithm for the erase operation. Refer to the Erase and
Program Operations table in the AC Characteristics section for parameters, and
Figure 18 section for timing diagrams.
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Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is
initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the
sector to be erased, and the sector erase command. Table 22 shows the address
and data requirements for the sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory
for an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 µs occurs.
During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than 50 µs, otherwise erasure
may begin. Any sector erase address and command following the exceeded timeout may or may not be accepted. It is recommended that processor interrupts be
disabled during this time to ensure all commands are accepted. The interrupts
can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out
period resets the device to the read mode. Note that the Secured Silicon
Sector, autoselect, and CFI functions are unavailable when an erase operation is in progress. The system must rewrite the command sequence and
any additional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out
(See the section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the device returns to reading
array data and addresses are no longer latched. The system can determine the
status of the erase operation by reading DQ7, DQ6, or DQ2 in the erasing sector.
Refer to the Write Operation Status section for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is
valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase
command sequence should be reinitiated once the device has returned to reading
array data, to ensure data integrity.
Figure 6 illustrates the algorithm for the erase operation. Refer to the Erase and
Program Operations table in the AC Characteristics section for parameters, and
Figure 18 section for timing diagrams.
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START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
No
Embedded
Erase
algorithm
in progress
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 22 for program command sequence.
2. See the section on DQ3 for information on the sector erase timer.
Figure 6. Erase Operation
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase
operation and then read data from, or program data to, any sector not selected
for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The
Erase Suspend command is ignored if written during the chip erase operation or
Embedded Program algorithm.
When the Erase Suspend command is written during the sector erase operation,
the device requires a typical of 5 µs (maximum of 20 µs) to suspend the erase
operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and
suspends the erase operation.
After the erase operation has been suspended, the device enters the erase-suspend-read mode. The system can read data from or program data to any sector
not selected for erasure. (The device “erase suspends” all sectors selected for
erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2
together, to determine if a sector is actively erasing or is erase-suspended. Refer
to the Write Operation Status section for information on these status bits.
After an erase-suspended program operation is complete, the device returns to
the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard word
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program operation. Refer to the Write Operation Status section for more
information.
In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the “Autoselect Mode” section on page 31 and
“Autoselect Command Sequence” section on page 45 sections for details.
To resume the sector erase operation, the system must write the Erase Resume
command. Further writes of the Resume command are ignored. Another Erase
Suspend command can be written after the chip has resumed erasing.
Note:During an erase operation, this flash device performs multiple internal operations which are invisible to the system. When an
erase operation is suspended, any of the internal operations that were not fully completed must be restarted. As such, if this flash
device is continually issued suspend/resume commands in rapid succession, erase progress will be impeded as a function of the
number of suspends. The result will be a longer cumulative erase time than without suspends. Note that the additional suspends do
not affect device reliability or future performance. In most systems rapid erase/suspend activity occurs only briefly. In such cases,
erase performance will not be significantly impacted.
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Command Definitions
Table 22.
Bus Cycles (Notes 2–5)
Cycles
Command
Sequence
(Note 1)
Command Definitions (x16 Mode)
Addr
Read (Note 6)
1
RA
Reset (Note 7)
First
Second
Data
RD
Third
Fourth
Addr
Data
Addr
Data
Addr
Fifth
Data
Addr
Sixth
Data
Addr
Data
XXX
F0
4
555
AA
2AA
55
555
90
X00
0001
Device ID (Note 9)
4
555
AA
2AA
55
555
90
X01
227E
Secured Silicon Sector Factory
Protect (Note 10)
4
555
AA
2AA
55
555
90
X03
(Note 10)
Sector Group Protect Verify (Note
12)
4
555
AA
2AA
55
555
90
(SA)X02
00/01
Enter Secured Silicon Sector Region
3
555
AA
2AA
55
555
88
Exit Secured Silicon Sector Region
4
555
AA
2AA
55
555
90
XXX
00
Program
4
555
AA
2AA
55
555
A0
PA
PD
Write to Buffer (Note 11)
3
555
AA
2AA
55
SA
25
SA
WC
PA
PD
WBL
PD
Program Buffer to Flash
1
SA
29
Write to Buffer Abort Reset (Note 13)
3
555
AA
2AA
55
555
F0
Unlock Bypass
3
555
AA
2AA
55
555
20
Unlock Bypass Program (Note 14)
2
XXX
A0
PA
PD
Unlock Bypass Reset (Note 15)
2
XXX
90
XXX
00
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Sector Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
Program/Erase Suspend (Note 16)
1
XXX
B0
Program/Erase Resume (Note 17)
1
XXX
30
CFI Query (Note 18)
1
55
98
Autoselect (Note 8)
1
Manufacturer ID
X0E
X0F
Legend:
X = Don’t care
RA = Read Address of memory location to be read.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on falling edge of WE# or
CE# pulse, whichever happens later.
PD = Program Data for location PA. Data latches on rising edge of
WE# or CE# pulse, whichever happens first.
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A21–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within same write
buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
56
See Table 1 for description of bus operations.
All values are in hexadecimal.
Shaded cells indicate read cycles. All others are write cycles.
During unlock and command cycles, when lower address bits are
555 or 2AA as shown in table, address bits above A11 and data
bits above DQ7 are don’t care.
No unlock or command cycles required when device is in read
mode.
Reset command is required to return to read mode (or to erasesuspend-read mode if previously in Erase Suspend) when device
is in autoselect mode, or if DQ5 goes high while device is
providing status information.
Fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care. Except for RD, PD
and WC. See Autoselect Command Sequence section for more
information.
Device ID must be read in three cycles.
If WP# protects highest address sector, data is 98h for factory
locked and 18h for not factory locked. If WP# protects lowest
address sector, data is 88h for factory locked and 08h for not
factor locked.
10. Data is 00h for an unprotected sector group and 01h for a
protected sector group.
11. Total number of cycles in command sequence is determined by
number of words written to write buffer. Maximum number of
cycles in command sequence is 21, including “Program Buffer to
Flash” command.
12. Command sequence resets device for next command after
aborted write-to-buffer operation.
13. Unlock Bypass command is required prior to Unlock Bypass
Program command.
14. Unlock Bypass Reset command is required to return to read
mode when device is in unlock bypass mode.
15. System may read and program in non-erasing sectors, or enter
autoselect mode, when in Erase Suspend mode. Erase Suspend
command is valid only during a sector erase operation.
16. Erase Resume command is valid only during Erase Suspend
mode.
17. Command is valid when device is ready to read array data or
when device is in autoselect mode.
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Write Operation Status
The device provides several bits to determine the status of a program or erase
operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 23 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for
determining whether a program or erase operation is complete or in progress.
The device also provides a hardware-based output signal, RY/BY#, to determine
whether an Embedded Program or Erase operation is in progress or has been
completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded
Program or Erase algorithm is in progress or completed, or whether the device is
in Erase Suspend. Data# Polling is valid after the rising edge of the final WE#
pulse in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to DQ7. The system must
provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then the device returns to the read mode.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.
When the Embedded Erase algorithm is complete, or if the device enters the
Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must
provide an address within any of the sectors selected for erasure to read valid
status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing
are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the
device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected
sectors that are protected. However, if the system reads DQ7 at an address within
a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7
may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to
valid data on DQ7. Depending on when the system samples the DQ7 output, it
may read the status or valid data. Even if the device has completed the program
or erase operation and DQ7 has valid data, the data outputs on DQ0–DQ6 may
be still invalid. Valid data on DQ0–DQ7 will appear on successive read cycles.
Table 23 shows the outputs for Data# Polling on DQ7. Figure 7 shows the Data#
Polling algorithm. Figure 19 in the AC Characteristics section shows the Data#
Polling timing diagram.
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START
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
Yes
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
Yes
No
FAIL
PASS
Notes:
1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector
being erased. During chip erase, a valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Figure 7. Data# Polling Algorithm
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an
Embedded Algorithm is in progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command sequence. Since RY/BY#
is an open-drain output, several RY/BY# pins can be tied together in parallel with
a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or programming. (This
includes programming in the Erase Suspend mode.) If the output is high (Ready),
the device is in the read mode, the standby mode, or in the erase-suspend-read
mode. Table 23 shows the outputs for RY/BY#.
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DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm
is in progress or complete, or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is valid after the rising edge
of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE#
to control the read cycles. When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing
are protected, DQ6 toggles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to
reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling
once the Embedded Program algorithm is complete.
Table 23 shows the outputs for Toggle Bit I on DQ6. Figure 8 shows the toggle bit
algorithm. Figure 20 in the “AC Characteristics” section shows the toggle bit timing diagrams. Figure 21 shows the differences between DQ2 and DQ6 in graphical
form. See also the subsection on DQ2: Toggle Bit II.
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START
Read Byte
(DQ7–DQ0)
Address =VA
Read Byte
(DQ7–DQ0)
Address =VA
Toggle Bit
= Toggle?
No
Yes
No
DQ5 = 1?
Yes
Read Byte Twice
(DQ7–DQ0)
Address = VA
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes:
1. The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes
to “1.” See the subsections on DQ6 and DQ2 for more information.
Figure 8. Toggle Bit Algorithm
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DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular
sector is actively erasing (that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have
been selected for erasure. (The system may use either OE# or CE# to control the
read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or
is erase-suspended. DQ6, by comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected
for erasure. Thus, both status bits are required for sector and mode information.
Refer to Table 23 to compare outputs for DQ2 and DQ6.
Figure 8 shows the toggle bit algorithm in flowchart form, and the section “DQ2:
Toggle Bit II” explains the algorithm. See also the RY/BY#: Ready/Busy# subsection. Figure 20 shows the toggle bit timing diagram. Figure 21 shows the
differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 8 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the system would note and
store the value of the toggle bit after the first read. After the second read, the
system would compare the new value of the toggle bit with the first. If the toggle
bit is not toggling, the device has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle
bit is still toggling, the system also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the
device did not completed the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit
is toggling and DQ5 has not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 8).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or write-to-buffer time has exceeded a specified internal pulse count limit. Under these conditions DQ5
produces a “1,” indicating that the program or erase cycle was not successfully
completed.
The device may output a “1” on DQ5 if the system tries to program a “1” to a
location that was previously programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.”
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In all these cases, the system must write the reset command to return the device
to the reading the array (or to erase-suspend-read if the device was previously
in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional sectors are selected for erasure,
the entire time-out also applies after each additional sector erase command.
When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the
time between additional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See also the
Sector Erase Command Sequence section.
After the sector erase command is written, the system should read the status of
DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase
algorithm has begun; all further commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. To ensure the command has been accepted, the
system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the
last command might not have been accepted.
Table 23 shows the status of DQ3 relative to the other status bits.
DQ1: Write-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these
conditions DQ1 produces a “1”. The system must issue the Write-to-Buffer-AbortReset command sequence to return the device to reading array data. See Write
Buffer section for more details.
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Table 23. Write Operation Status
DQ7
(Note 2)
DQ6
DQ5
(Note 1)
DQ3
DQ2
(Note 2)
DQ1
RY/
BY#
Embedded Program Algorithm
DQ7#
Toggle
0
N/A
No toggle
0
0
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
N/A
0
Status
Standard
Mode
Program
Suspend
Mode
Erase
Suspend
Mode
Write-toBuffer
ProgramSuspend
Read
EraseSuspend
Read
Program-Suspended
Sector
Invalid (not allowed)
1
Data
1
Non-Program
Suspended Sector
Erase-Suspended
Sector
1
No toggle
0
Non-Erase
Suspended Sector
N/A
Toggle
N/A
Data
1
1
Erase-Suspend-Program
(Embedded Program)
DQ7#
Toggle
0
N/A
N/A
N/A
0
Busy (Note 3)
DQ7#
Toggle
0
N/A
N/A
0
0
Abort (Note 4)
DQ7#
Toggle
0
N/A
N/A
1
0
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the
maximum timing limits. Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for
further details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
4. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation.
March 31, 2005 S71GL032A_00_A0
S71GL032A Based MCPs
63
A d v a n c e
I n f o r m a t i o n
Absolute Maximum Ratings
Storage Temperature, Plastic Packages . . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature with Power Applied . . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground:
VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
ACC and RESET# (Note 2) . . . . . . . . . . . . . . . . . . . . –0.5 V to +12.5 V
All other pins (Note 1) . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC+0.5 V
Output Short Circuit Current (Note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs
or I/Os may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 9.
Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage transitions,
input or I/O pins may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure
10.
2. Minimum DC input voltage on pins A9, OE#, ACC, and RESET# is –0.5 V. During
voltage transitions, A9, OE#, ACC, and RESET# may overshoot VSS to –2.0 V for
periods of up to 20 ns. See Figure 9. Maximum DC input voltage on pin A9, OE#,
ACC, and RESET# is +12.5 V which may overshoot to +14.0V for periods up to
20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short
circuit should not be greater than one second.
4. Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this data sheet is not implied. Exposure of the device to
absolute maximum rating conditions for extended periods may affect device
reliability.
20 ns
20 ns
20 ns
VCC
+2.0 V
VCC
+0.5 V
+0.8 V
–0.5 V
–2.0 V
2.0 V
20 ns
20 ns
Figure 9. Maximum Negative
Overshoot Waveform
20 ns
Figure 10. Maximum Positive
Overshoot Waveform
Operating Ranges
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Supply Voltages
VCC for full voltage range . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 V to +3.6 V
VCC for regulated voltage range . . . . . . . . . . . . . . . . . . . . . +3.0 V to +3.6 V
VIO
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC
Note:Operating ranges define those limits between which the functionality of the device is guaranteed.
64
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
A d v a n c e
I n f o r m a t i o n
DC Characteristics
CMOS Compatible
Parameter
Symbol
Parameter Description (Notes)
Test Conditions
ILI
Input Load Current (Note 1)
VIN = VSS to VCC,
VCC = VCC max
ILIT
A9, ACC Input Load Current
VCC = VCC max; A9 =
12.5 V
ILR
Reset Leakage Current
VCC = VCC max; RESET# = 12.5 V
ILO
Output Leakage Current
VOUT = VSS to VCC,
VCC = VCC max
VCC Initial Read Current (Notes 2, 3)
CE# = VIL, OE# =
VIH,
ICC1
Min
Typ
Max
Unit
±1.0
µA
-40°C to 0°C
250
0°C to 85°C
35
µA
35
µA
±1.0
µA
1 MHz
5
20
5 MHz
18
25
10 MHz
35
50
10 MHz
5
20
40 MHz
10
40
50
60
mA
mA
ICC2
VCC Intra-Page Read Current (Notes 2, 3)
CE# = VIL, OE# = VIH
ICC3
VCC Active Write Current (Note 3)
CE# = VIL, OE# = VIH
ICC4
VCC Standby Current (Note 3)
CE#, RESET# = VCC ± 0.3 V,
WP# = VIH
1
5
µA
ICC5
VCC Reset Current (Note 3)
RESET# = VSS ± 0.3 V, WP# = VIH
1
5
µA
ICC6
Automatic Sleep Mode (Notes 3, 5)
VIH = VCC ± 0.3 V;
-0.1< VIL ≤ 0.3 V, WP# = VIH
1
5
µA
VIL
Input Low Voltage 1 (Note 6)
–0.5
0.8
V
VIH
Input High Voltage 1 (Note 6)
0.7 VCC
VCC + 0.5
V
VHH
Voltage for ACC Program
Acceleration
VCC = 2.7 –3.6 V
11.5
12.0
12.5
V
VID
Voltage for Autoselect and Temporary
Sector Unprotect
VCC = 2.7 –3.6 V
11.5
12.0
12.5
V
VOL
Output Low Voltage (Note 6)
IOL = 4.0 mA, VCC = VCC min
0.45
V
VOH1
Output High Voltage
VOH2
VLKO
mA
IOH = –2.0 mA, VCC = VCC min
0.85 VCC
V
IOH = –100 µA, VCC = VCC min
VCC–0.4
V
Low VCC Lock-Out Voltage (Note 7)
2.3
2.5
V
Notes:
1. On the WP#/ACC pin only, the maximum input load current when WP# = VIL is ± 5.0 µA.
2. The ICC current listed is typically less than 3.5 mA/MHz, with OE# at VIH.
3. Maximum ICC specifications are tested with VCC = VCCmax.
4. ICC active while Embedded Erase or Embedded Program is in progress.
5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns.
6. VCC voltage requirements.
7. Not 100% tested.
March 31, 2005 S71GL032A_00_A0
S71GL032A Based MCPs
65
A d v a n c e
I n f o r m a t i o n
Test Conditions
3.3 V
2.7 kΩ
Device
Under
Test
CL
6.2 kΩ
Table 24.
Test Specifications
Test Condition
All Speeds
Unit
Output Load
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
5
ns
0.0 or VCC
V
Input timing measurement
reference levels (See Note)
0.5 VCC
V
Output timing measurement
reference levels
0.5 VCC
V
Input Pulse Levels
Note: Diodes are IN3064 or equivalent.
Figure 11.
Test Setup
Key to Switching Waveforms
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
VCC
Input
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
0.5 VCC
Measurement Level
0.5 VCC
Output
0.0 V
Figure 12. Input Waveforms and Measurement Levels
66
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
A d v a n c e
I n f o r m a t i o n
AC Characteristics
Read-Only Operations-S29GL064A only
Parameter
Speed Options
JEDEC
Std.
tAVAV
tRC
tAVQV
tACC
Address to Output Delay
tELQV
tCE
Chip Enable to Output Delay
tPACC
Description
Test Setup
90
10
11
Unit
Min
90
100
110
ns
CE#, OE# = VIL
Max
90
100
110
ns
OE# = VIL
Max
90
100
110
ns
Page Access Time
Max
25
30
30
ns
25
30
30
ns
Read Cycle Time (Note 1)
tGLQV
tOE
Output Enable to Output Delay
Max
tEHQZ
tDF
Chip Enable to Output High Z (Note 1)
Max
16
ns
tGHQZ
tDF
Output Enable to Output High Z (Note 1)
Max
16
ns
tOH
Output Hold Time From Addresses, CE# or OE#, Whichever Occurs
First
Min
0
ns
Output Enable Hold Time
(Note 1)
Read
Min
0
ns
tOEH
Toggle and
Data# Polling
Min
10
ns
tAXQX
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 24 for test specifications.
Read-Only Operations-S29GL032A only
Parameter
Speed Options
JEDEC
Std.
tAVAV
tRC
Read Cycle Time (Note 1)
tAVQV
tACC
Address to Output Delay
tELQV
tCE
Chip Enable to Output Delay
tPACC
Description
Test Setup
90
10
11
Unit
Min
90
100
110
ns
CE#, OE# = VIL
Max
90
100
110
ns
OE# = VIL
Max
90
100
110
ns
Page Access Time
Max
25
30
30
ns
25
30
30
ns
tGLQV
tOE
Output Enable to Output Delay
Max
tEHQZ
tDF
Chip Enable to Output High Z (Note 1)
Max
16
ns
tGHQZ
tDF
Output Enable to Output High Z (Note 1)
Max
16
ns
tAXQX
tOH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
Min
0
ns
Read
Min
0
ns
tOEH
Output Enable Hold Time (Note 1)
Toggle and
Data# Polling
Min
10
ns
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 24 for test specifications.
March 31, 2005 S71GL032A_00_A0
S71GL032A Based MCPs
67
A d v a n c e
I n f o r m a t i o n
tRC
Addresses Stable
Addresses
tACC
CE#
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Valid Data
Data
RESET#
RY/BY#
0V
Figure 13. Read Operation Timings
Same Page
A23-A2
A1-A0*
Aa
tACC
Data Bus
Ab
tPACC
tPACC
Qa
Ad
Ac
Qb
tPACC
Qc
Qd
CE#
OE#
Note: * Figure shows device in word mode. Addresses are A1–A-1 for byte mode.
Figure 14. Page Read Timings
68
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
A d v a n c e
I n f o r m a t i o n
Hardware Reset (RESET#)
Parameter
JEDEC
Std.
Description
All Speed Options
Unit
tReady
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
Max
20
µs
tReady
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
Max
500
ns
tRP
RESET# Pulse Width
Min
500
ns
tRH
Reset High Time Before Read (See Note)
Min
50
ns
tRPD
RESET# Input Low to Standby Mode (See Note)
Min
20
µs
tRB
RY/BY# Output High to CE#, OE# pin Low
Min
0
ns
Note:Not 100% tested.
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
3. For 1–16 words/1–32 bytes programmed.
Figure 15. Reset Timings
March 31, 2005 S71GL032A_00_A0
S71GL032A Based MCPs
69
A d v a n c e
I n f o r m a t i o n
Erase and Program Operations-S29GL064A Only
Parameter
Speed Options
JEDEC
Std.
tAVAV
tWC
Write Cycle Time (Note 1)
Min
tAVWL
tAS
tWLAX
Description
90
10
11
Unit
90
100
110
ns
Address Setup Time
Min
0
ns
tASO
Address Setup Time to OE# low during toggle bit polling
Min
15
ns
tAH
Address Hold Time
Min
45
ns
tAHT
Address Hold Time From CE# or OE# high during toggle bit polling
Min
0
ns
tDVWH
tDS
Data Setup Time
Min
35
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
tCEPH
CE# High during toggle bit polling
Min
20
ns
tOEPH
OE# High during toggle bit polling
Min
20
ns
tGHWL
tGHWL
Read Recovery Time Before Write (OE# High to WE# Low)
Min
0
ns
tELWL
tCS
CE# Setup Time
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
35
ns
tWHDL
tWPH
Write Pulse Width High
Min
30
ns
Write Buffer Program Operation (Notes 2, 3)
Typ
240
tWHWH1
tWHWH1
Single Word Program Operation (Note 2)
Typ
60
Accelerated Single Word Program Operation (Note 2)
Typ
54
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ
0.5
sec
tVHH
VHH Rise and Fall Time (Note 1)
Min
250
ns
tVCS
VCC Setup Time (Note 1)
Min
50
µs
tBUSY
WE# High to RY/BY# Low
Min
tPOLL
Program Valid before Status Polling
Max
90
100
4
µs
110
ns
µs
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once
programming has resumed (that is, the program resume command has been written). If the suspend command was issued
after tPOLL, status data is available immediately after programming has resumed. See Figure 16.
70
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
A d v a n c e
I n f o r m a t i o n
Erase and Program Operations-S29GL032A Only
Parameter
Speed Options
JEDEC
Std.
tAVAV
tWC
Write Cycle Time (Note 1)
Min
tAVWL
tAS
Address Setup Time
Min
0
ns
tASO
Address Setup Time to OE# low during toggle bit polling
Min
15
ns
tAH
Address Hold Time
Min
45
ns
tAHT
Address Hold Time From CE# or OE# high during toggle bit polling
Min
0
ns
tDVWH
tDS
Data Setup Time
Min
35
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
tCEPH
CE# High during toggle bit polling
Min
20
ns
tOEPH
OE# High during toggle bit polling
Min
20
ns
tGHWL
tGHWL
Read Recovery Time Before Write (OE# High to WE# Low)
Min
0
ns
tELWL
tCS
CE# Setup Time
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
35
ns
tWHDL
tWPH
Write Pulse Width High
Min
30
ns
Write Buffer Program Operation (Notes 2, 3)
Typ
240
Single Word Program Operation (Note 2)
Typ
60
Accelerated Single Word Program Operation (Note 2)
Typ
54
tWHWH2
Sector Erase Operation (Note 2)
Typ
0.5
sec
tVHH
VHH Rise and Fall Time (Note 1)
Min
250
ns
tVCS
VCC Setup Time (Note 1)
Min
50
µs
tBUSY
WE# High to RY/BY# Low
Min
tPOLL
Program Valid before Status Polling
Max
tWLAX
tWHWH1
tWHWH2
tWHWH1
Description
90
10
11
Unit
90
100
110
ns
90
100
4
µs
110
ns
µs
Notes:
1. Not 100% tested.
2. See “Erase And Programming Performance” for more information
3. For 1–16 words/1–32 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once
programming resumes (that is, the program resume command has been written). If the suspend command was issued after
tPOLL, status data is available immediately after programming resumes. See Figure 16.
March 31, 2005 S71GL032A_00_A0
S71GL032A Based MCPs
71
A d v a n c e
I n f o r m a t i o n
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
Read Status Data (last two cycles)
555h
PA
PA
PA
tAH
CE#
tCH
OE#
tPOLL
tWP
WE#
tWPH
tCS
tDS
tWHWH1
tDH
PD
A0h
Data
Status
tBUSY
DOUT
tRB
RY/BY#
VCC
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 16.
Program Operation Timings
VHH
HH
ACC
VIL
IL or VIH
IH
VIL
IL or VIH
IH
tVHH
VHH
tVHH
VHH
Figure 17.
72
Accelerated Program Timing Diagram
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
A d v a n c e
I n f o r m a t i o n
Erase Command Sequence (last two cycles)
tAS
tWC
2AAh
Addresses
Read Status Data
VA
SA
VA
555h for chip erase
tAH
CE#
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
30h
Status
DOUT
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.)
2. Illustration shows device in word mode.
Figure 18. Chip/Sector Erase Operation Timings
tRC
Addresses
VA
tPOLL
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ7
Complement
Complement
DQ0–DQ6
Status Data
Status Data
True
Valid Data
High Z
True
Valid Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array
data read cycle.
Figure 19. Data# Polling Timings (During Embedded Algorithms)
March 31, 2005 S71GL032A_00_A0
S71GL032A Based MCPs
73
A d v a n c e
I n f o r m a t i o n
tAHT
tAS
Addresses
tAHT
tASO
CE#
tCEPH
tOEH
WE#
tOEPH
OE#
tDH
DQ6/DQ2
tOE
Valid Data
Valid
Status
Valid
Status
Valid
Status
(first read)
(second read)
(stops toggling)
Valid Data
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last
status read cycle, and array data read cycle.
Figure 20.
Enter
Embedded
Erasing
WE#
Erase
Suspend
Erase
Toggle Bit Timings (During Embedded Algorithms)
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#
to toggle DQ2 and DQ6.
Figure 21. DQ2 vs. DQ6
74
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
A d v a n c e
I n f o r m a t i o n
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
tVIDR
tRSP
VID Rise and Fall Time (See Note)
RESET# Setup Time for Temporary Sector
Unprotect
All Speed Options
Unit
Min
500
ns
Min
4
µs
Notes:
1. Not 100% tested.
VID
VID
RESET#
VIL or VIH
VIL or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRRB
tRSP
RY/BY#
Figure 22.
March 31, 2005 S71GL032A_00_A0
Temporary Sector Group Unprotect Timing Diagram
S71GL032A Based MCPs
75
A d v a n c e
I n f o r m a t i o n
VID
VIH
RESET#
SA, A6,
A3, A2,
A1, A0
Valid*
Valid*
Sector Group Protect or Unprotect
Data
60h
60h
Valid*
Verify
40h
Status
Sector Group Protect: 150 µs,
Sector Group Unprotect: 15 ms
1 µs
CE#
WE#
OE#
Note: For sector group protect, A6:A0 = 0xx0010. For sector group unprotect, A6:A0 = 1xx0010.
Figure 23.
76
Sector Group Protect and Unprotect Timing Diagram
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
A d v a n c e
I n f o r m a t i o n
AC Characteristics
Alternate CE# Controlled Erase and Program Operations-S29GL064A
Parameter
Speed Options
Std.
tAVAV
tWC
Write Cycle Time (Note 1)
Min
tAVWL
tAS
Address Setup Time
Min
0
ns
tELAX
tAH
Address Hold Time
Min
45
ns
tDVEH
tDS
Data Setup Time
Min
35
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tGHEL
tGHEL
Read Recovery Time Before Write (OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
tELEH
tCP
CE# Pulse Width
Min
35
ns
tEHEL
tCPH
CE# Pulse Width High
Min
25
ns
Write Buffer Program Operation (Notes 2, 3)
Typ
240
Single Word Program Operation (Note 2)
Typ
60
Accelerated Single Word Program Operation (Note 2)
Typ
54
tWHWH2
Sector Erase Operation (Note 2)
Typ
0.5
sec
tRH
RESET# High Time Before Write
Min
50
ns
Program Valid before Status Polling (Note 5)
Max
4
µs
tWHWH1
tWHWH2
tWHWH1
tPOLL
Description
90
10
11
90
100
110
Unit
JEDEC
ns
µs
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once
programming has resumed (that is, the program resume command has been written). If the suspend command was issued
after tPOLL, status data is available immediately after programming has resumed. See Figure 24.
March 31, 2005 S71GL032A_00_A0
S71GL032A Based MCPs
77
A d v a n c e
I n f o r m a t i o n
Alternate CE# Controlled Erase and Program Operations-S29GL032A
Parameter
Speed Options
JEDEC
Std.
tAVAV
tWC
Write Cycle Time (Note 1)
Min
tAVWL
tAS
Address Setup Time
Min
0
ns
tELAX
tAH
Address Hold Time
Min
45
ns
tDVEH
tDS
Data Setup Time
Min
35
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tGHEL
tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
tELEH
tCP
CE# Pulse Width
Min
35
ns
tEHEL
tCPH
CE# Pulse Width High
Min
25
ns
Write Buffer Program Operation (Notes 2, 3)
Typ
240
Single Word Program Operation (Note 2)
Typ
60
Accelerated Single Word Program Operation (Note 2)
Typ
54
tWHWH2
Sector Erase Operation (Note 2)
Typ
0.5
sec
tRH
RESET# High Time Before Write
Min
50
ns
Program Valid before Status Polling (Note 4)
Max
4
µs
tWHWH1
tWHWH2
tWHWH1
tPOLL
Description
90
10
11
Unit
90
100
110
ns
µs
Notes:
1. Not 100% tested.
2. See “Erase And Programming Performance” for more information
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once
programming resumes (that is, the program resume command has been written). If the suspend command was issued after
tPOLL, status data is available immediately after programming resumes. See Figure 24.
78
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
A d v a n c e
PBA for program
2AA for erase
I n f o r m a t i o n
SA for program buffer to flash
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tPOLL
tGHEL
OE#
tWHWH1 or 2
tCP
CE#
tWS
tCPH
tBUSY
tDS
tDH
DQ7#
Data
tRH
PBD for program
55 for erase
DOUT
29 for program buffer to flash
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Illustration shows device in word mode.
Figure 24.
March 31, 2005 S71GL032A_00_A0
Alternate CE# Controlled Write (Erase/Program) Operation Timings
S71GL032A Based MCPs
79
A d v a n c e
I n f o r m a t i o n
Erase And Programming Performance
Typ (Note 1)
Max
(Note 2)
0.5
3.5
S29GL032A
32
64
S29GL064A
64
128
Parameter
Sector Erase Time
Chip Erase Time
Unit
Comments
sec
Excludes 00h
programming
prior to erasure
(Note 6)
Total Write Buffer Program Time (Notes 3, 5)
240
µs
Total Accelerated Effective Write Buffer Program Time
(Notes 4, 5)
200
µs
Chip Program Time
S29GL032A
31.5
S29GL064A
63
Excludes system
level overhead
(Note 7)
sec
Notes:
1. Typical program and erase times assume the following conditions: 25°C, VCC = 3.0V, 10,000 cycles; checkerboard
data pattern.
2. Under worst case conditions of 90°C; Worst case VCC, 100,000 cycles.
3. Effective programming time (typ) is 15 µs (per word), 7.5 µs (per byte).
4. Effective accelerated programming time (typ) is 12.5 µs (per word), 6.3 µs (per byte).
5. Effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer
operation.
6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
7. System-level overhead is the time required to execute the command sequence(s) for the program command. See
Table 22 for further information on command definitions.
80
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
A d v a n c e
I n f o r m a t i o n
Type 4 pSRAM
4 Mbit (256K x 16)
Features
Wide voltage range: 2.7V to 3.3V
Typical active current: 3 mA @ f = 1 MHz
Low standby power
Automatic power-down when deselected
Functional Description
The Type 4 pSRAM is a high-performance CMOS pseudo static RAM (pSRAM) organized as 256K words by 16 bits that supports an asynchronous memory
interface. This device features advanced circuit design to provide ultra-low active
current. The device can be put into standby mode reducing power consumption
dramatically when deselected (CE1# Low, CE2 High or both BHE# and BLE# are
High). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE1# High, CE2 Low, OE# is deasserted High), or
during a write operation (Chip Enabled and Write Enable WE# Low). Reading
from the device is accomplished by asserting the Chip Enables (CE1# Low and
CE2 High) and Output Enable (OE#) Low while forcing the Write Enable (WE#)
High. If Byte Low Enable (BLE#) is Low, then data from the memory location
specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable
(BHE#) is Low, then data from memory will appear on I/O8 to I/O15. See Table
27 for a complete description of read and write modes.
Product Portfolio
Power Dissipation
Operating, ICC (mA)
VCC Range (V)
Min
Typ
Max
Speed
(ns)
2.7V
3.0V
3.3V
70 ns
f = 1 MHz
f = fmax
Standby (ISB2) (µA)
Typ. (note 1)
Max
Typ. (note 1)
Max
Typ. (note 1)
Max
3
5
TBD
25 mA
15
40
Notes:
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC
(typ) and TA = 25°C.
March 31, 2005 S71GL032A_00_A0
S71GL032A Based MCPs
81
A d v a n c e
I n f o r m a t i o n
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested)
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Ambient Temperature with Power Applied . . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage to Ground Potential . . . . . . . . . . . . . . . . . . . . . -0.4V to 4.6V
DC Voltage Applied to Outputs in High-Z
State (note 1, 2, 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 3.7V
DC Input Voltage (note 1, 2, 3) . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 3.7V
Output Current into Outputs (Low). . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Static Discharge Voltage . . . . . . . . . >2001V (per MIL-STD-883, Method 3015)
Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >200 mA
Notes:
1. VIH(MAX) = VCC + 0.5V for pulse durations less than 20 ns.
2. VIL(MIN) = –0.5V for pulse durations less than 20 ns.
3. Overshoot and undershoot specifications are characterized and are not 100% tested.
Operating Range
Ambient Temperature (TA)
VCC
-25°C to +85°C
2.7V to 3.3V
Table 25. DC Electrical Characteristics (Over the Operating Range)
Parameter
Description
Test Conditions
VCC
Supply Voltage
VOH
Output High Voltage
IOH = –1.0 mA
VOL
Output Low Voltage
IOL = 0.1 mA
VIH
Input High Voltage
Min.
Typ.
(note 1)
2.7
Max
3.3
VCC - 0.4
0.4
0.8 * VCC
VCC + 0.4
VIL
Input Low Voltage
F=0
-0.4
0.4
IIX
Input Leakage Current
GND ≤ VIN ≤ VCC
-1
+1
IOZ
Output Leakage Current
GND ≤ VOUT ≤ VCC, Output Disabled
-1
+1
ICC
VCC Operating Supply Current
ISB1
Automatic CE# Power-Down
Current—CMOS Inputs
CE# ≥ VCC – 0.2V, CE2 ≤ 0.2V
VIN ≥ VCC – 0.2V, VIN ≤ 0.2V,
f = fmax (Address and Data Only),
f=0 (OE#, WE#, BHE# and BLE#)
Automatic CE# Power-Down
Current—CMOS Inputs
CE# ≥ VCC – 0.2V, CE2 ≤ 0.2V
VIN ≥ VCC – 0.2V or VIN ≤ 0.2V,
f = 0, VCC = 3.3V
ISB2
f = fMAX = 1/tRC
f = 1 MHz
Unit
VCC = 3.3V
IOUT = 0 mA
CMOS Levels
TBD
15
3
V
µA
mA
250
µA
40
Notes:
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC =
VCC(typ.), TA = 25°C.
82
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
A d v a n c e
I n f o r m a t i o n
Capacitance
Parameter
CIN
COUT
Description
Test Condition
Max
Input Capacitance
TA = 25°C, f = 1 MHz,
VCC = VCC(typ.)
8
Output Capacitance
Unit
pF
8
Note: Tested initially and after any design or process changes that may affect these parameters.
Thermal Resistance
Parameter
θ JA
θ JC
Description
Test Conditions
VFBGA
Thermal Resistance (Junction to Ambient) Test conditions follow standard test methods
and procedures for measuring thermal
Thermal Resistance (Junction to Case)
impedance, per EIA / JESD51.
Unit
55
17
°C/W
Note: Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
R1
VCC
ALL INPUT PULSES
VCC
OUTPUT
10%
R2
30 pF
90%
GND
Rise Time: 1 V/ns
90%
10%
Fall Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉ VENIN EQUIVALENT
OUTPUT
RTH
VTH
Figure 25. AC Test Loads and Waveforms
March 31, 2005 S71GL032A_00_A0
Parameters
3.0V VCC
R1
22000
R2
22000
RTH
11000
VTH
1.50
S71GL032A Based MCPs
Unit
Ω
V
83
A d v a n c e
I n f o r m a t i o n
Table 26. Switching Characteristics
Parameter
Description
Min
Max
Unit
Read Cycle
tRC
Read Cycle Time
70
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE#1 Low and CE2 High to Data Valid
70
tDOE
OE# Low to Data Valid
35
tLZOE
OE# Low to Low Z (note 2, 3)
tHZOE
OE# High to High Z (note 2, 3)
tLZCE
CE#1 Low and CE2 High to Low Z (note 2, 3)
tHZCE
CE#1 High and CE2 Low to High Z (note 2, 3)
25
tDBE
BHE# / BLE# Low to Data Valid
70
tLZBE
BHE# / BLE# Low to Low Z (note 2, 3)
tHZBE
BHE# / BLE# High to High Z (note 2, 3)
25
tSK (note 4)
Address Skew
10
70
10
5
25
ns
5
5
Write Cycle (note 5)
tWC
Write Cycle Time
70
tSCE
CE#1 Low an CE2 High to Write End
55
tAW
Address Set-Up to Write End
55
tHA
Address Hold from Write End
0
tSA
Address Set-Up to Write Start
0
tPWE
WE# Pulse Width
55
tBW
BLE# / BHE# LOW to Write End
55
tSD
Data Set-up to Write End
25
tHD
Data Hold from Write End
0
tHZWE
WE# Low to High Z (note 2, 3)
tLZWE
WE# High to Low Z (note 2, 3)
ns
25
5
Notes:
1. Test conditions assume signal transition time of 1V/ns or higher, timing reference levels of VCC(typ.) /2, input pulse levels of
0 to VCC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance.
2. tHZOE, tHZCE, tHZBE and tHZWE transitions are measured when the outputs enter a high-impedance state.
3. High-Z and Low-Z parameters are characterized and are not 100% tested.
4. To achieve 55-ns performance, the read access should be CE# controlled. In this case tACE is the critical parameter and tSK is
satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable
within 10 ns after the start of the read cycle.
5. The internal write time of the memory is defined by the overlap of WE#, CE#1 = VIL, CE2 = VIH, BHE and/or BLE =VIL. All
signals must be Active to initiate a write and any of these signals can terminate a write by going Inactive. The data input setup and hold timing should be referenced to the edge of the signal that terminates write.
84
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
A d v a n c e
I n f o r m a t i o n
Switching Waveforms
tRC
ADDRESS
tSK
DATA OUT
tOHA
tAA
DATA VALID
PREVIOUS DATA VALID
Figure 26. Read Cycle 1 (Address Transition Controlled)
Notes:
1. To achieve 55-ns performance, the read access should be CE# controlled. In this case tACE is the critical parameter and tSK is
satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable
within 10 ns after the start of the read cycle.
2. Device is continuously selected. OE#, CE# = VIL.
3. WE# is High for Read Cycle.
ADDRESS
CE#1
tRC
tSK
CE2
tHZCE
tACE
BHE#/BLE#
tLZBE
tDBE
tHZBE
OE#
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDENCE
DATA VALID
tLZCE
HIGH
IMPEDENCE
Figure 27. Read Cycle 2 (OE# Controlled)
Notes:
1. To achieve 55-ns performance, the read access should be CE# controlled. In this case tACE is the critical parameter and tSK is
satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable
within 10 ns after the start of the read cycle.
2. WE# is High for Read Cycle.
March 31, 2005 S71GL032A_00_A0
S71GL032A Based MCPs
85
A d v a n c e
I n f o r m a t i o n
Figure 28. Write Cycle 1 (WE# Controlled)
Notes:
1. High-Z and Low-Z parameters are characterized and are not 100% tested.
2. The internal write time of the memory is defined by the overlap of WE#, CE#1 = VIL, CE2 = VIH, BHE and/or BLE =VIL. All
signals must be Active to initiate a write and any of these signals can terminate a write by going Inactive. The data input setup and hold timing should be referenced to the edge of the signal that terminates write.
3. Data I/O is high impedance if OE# ≥ VIH.
4. If Chip Enable goes Inactive simultaneously with WE# = High, the output remains in a high-impedance state.
5. During the Don’t Care period in the Data I/O waveform, the I/Os are in output state and input signals should not be applied.
86
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
A d v a n c e
I n f o r m a t i o n
tWC
ADDRESS
tSCE
CE#1
CE2
tSA
tAW
tHA
tPWE
WE#
tBW
BHE#/BLE#
OE#
tSD
DATA I/O
tHD
VALID DATA
DON’T CARE
tHZOE
Figure 29.
Write Cycle 2 (CE#1 or CE2 Controlled)
Notes:
1. High-Z and Low-Z parameters are characterized and are not 100% tested.
2. The internal write time of the memory is defined by the overlap of WE#, CE#1 = VIL, CE2 = VIH, BHE and/or BLE =VIL. All
signals must be Active to initiate a write and any of these signals can terminate a write by going Inactive. The data input setup and hold timing should be referenced to the edge of the signal that terminates write.
3. Data I/O is high impedance if OE# ≥ VIH.
4. If Chip Enable goes Inactive simultaneously with WE# = High, the output remains in a high-impedance state.
5. During the Don’t Care period in the Data I/O waveform, the I/Os are in output state and input signals should not be applied.
March 31, 2005 S71GL032A_00_A0
S71GL032A Based MCPs
87
A d v a n c e
I n f o r m a t i o n
tWC
ADDRESS
tSCE
CE#1
CE2
tBW
BHE#/BLE#
tAW
tSA
tHA
tPWE
WE#
tSD
DATA I/O DON’T CARE
tHD
VALID DATA
tLZWE
tHZWE
Figure 30.
Write Cycle 3 (WE# Controlled, OE# Low)
Notes:
1. If Chip Enable goes Inactive simultaneously with WE# = High, the output remains in a high-impedance state.
2. During the Don’t Care period in the Data I/O waveform, the I/Os are in output state and input signals should not be applied.
CE#1
CE2
BHE#/BLE#
WE#
Figure 31. Write Cycle 4 (BHE#/BLE# Controlled, OE# Low)
Notes:
1. If Chip Enable goes Inactive simultaneously with WE# = High, the output remains in a high-impedance state.
2. During the Don’t Care period in the Data I/O waveform, the I/Os are in output state and input signals should not be applied.
88
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
A d v a n c e
I n f o r m a t i o n
Truth Table
Table 27.
CE#1
CE2
WE#
OE#
BHE#
BLE#
H
X
X
X
X
X
High-Z
X
L
X
X
X
X
High-Z
Truth Table
Inputs / Outputs
Mode
Deselect/Power-Down
X
X
X
X
H
H
High-Z
L
H
H
L
L
L
Data Out (I/O0–I/O15)
Read (Upper Byte and Lower Byte)
L
H
H
L
H
L
Data Out (I/O0 –I/O7);
I/O8–I/O15 in High Z
Read (Upper Byte only)
L
H
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read (Lower Byte only)
L
H
H
H
L
L
High-Z
Output Disabled
L
H
H
H
H
L
High-Z
Output Disabled
L
H
H
H
L
H
High-Z
Output Disabled
L
H
L
X
L
L
Data In (I/O0–I/O15)
Write (Upper Byte and Lower Byte)
L
H
L
X
H
L
Data In (I/O0–I/O7);
I/O8–I/O15 in High Z
Write (Lower Byte Only)
L
H
L
X
L
H
Data In (I/O8–I/O15);
I/O0 –I/O7 in High Z
Write (Upper Byte Only)
March 31, 2005 S71GL032A_00_A0
S71GL032A Based MCPs
Power
Standby (ISB)
Active (ICC)
89
A d v a n c e
I n f o r m a t i o n
Type 1 SRAM
4/8 Megabit CMOS SRAM
Common Features
Process Technology: Full CMOS
Power Supply Voltage: 2.7~3.3V
Three state outputs
Version
Density
Organization
(ISB1, Max.)
Standby
(ICC2, Max.)
Operating
Mode
F
4Mb
x8 or x16 (note 1)
10 µA
22 mA
Dual CS, UB# / LB# (tCS)
G
4Mb
x8 or x16 (note 1)
10 µA
22 mA
Dual CS, UB# / LB# (tCS)
C
8Mb
x8 or x16 (note 1)
15 µA
22 mA
Dual CS, UB# / LB# (tCS)
D
8Mb
X16
TBD
TBD
Dual CS, UB# / LB# (tCS)
Notes:
1. UB#, LB# swapping is available only at x16. x8 or x16 select by BYTE# pin.
Pin Description
Pin Name
90
Description
I/O
CS1#, CS2
Chip Selects
I
OE#
Output Enable
I
WE#
Write Enable
I
BYTE#
Word (VCC)/Byte (VSS) Select
I
A0~A17 (4M)
A0~A18 (8M)
Address Inputs
I
SA
Address Input for Byte Mode
I
I/O0~I/O15
Data Inputs/Outputs
VCC
Power Supply
-
VSS
Ground
-
DNU
Do Not Use
-
NC
No Connection
-
S71GL032A Based MCPs
I/O
S71GL032A_00_A0 March 31, 2005
A d v a n c e
I n f o r m a t i o n
Functional Description
4M Version F, 4M version G, 8M version C
CS1#
CS2
OE# WE#
BYTE#
SA
LB#
UB#
IO0~7
IO8~15
Mode
Power
H
X
X
X
X
X
X
X
High-Z
High-Z
Deselected
Standby
X
L
X
X
X
X
X
X
High-Z
High-Z
Deselected
Standby
X
X
X
X
X
X
H
H
High-Z
High-Z
Deselected
Standby
L
H
H
H
VCC
X
L
X
High-Z
High-Z
Output Disabled
Active
L
H
H
H
VCC
X
X
L
High-Z
High-Z
Output Disabled
Active
L
H
L
H
VCC
X
L
H
Dout
High-Z
Lower Byte Read
Active
L
H
L
H
VCC
X
H
L
High-Z
Dout
Upper Byte Read
Active
L
H
L
H
VCC
X
L
L
Dout
Dout
Word Read
Active
L
H
X
L
VCC
X
L
H
Din
High-Z
Lower Byte Write
Active
L
H
X
L
VCC
X
H
L
High-Z
Din
Upper Byte Write
Active
L
H
X
L
VCC
X
L
L
Din
Din
Word Write
Active
Note: X means don’t care (must be low or high state).
Byte Mode
CS1#
CS2
OE# WE#
BYTE#
SA
LB#
UB#
IO0~7
IO8~15
Mode
Power
H
X
X
X
X
X
X
X
High-Z
High-Z
Deselected
Standby
X
L
X
X
X
X
X
X
High-Z
High-Z
Deselected
Standby
L
H
H
H
X
X
H
H
High-Z
High-Z
Deselected
Standby
L
H
L
L
VCC
X
L
X
High-Z
High-Z
Output Disabled
Active
L
H
X
L
VCC
X
X
L
High-Z
High-Z
Output Disabled
Active
March 31, 2005 S71GL032A_00_A0
S71GL032A Based MCPs
91
A d v a n c e
I n f o r m a t i o n
Functional Description
8M Version D
CS1#
CS2
OE# WE#
LB#
UB#
IO0~8
IO9~16
Mode
Power
H
X
X
X
X
X
High-Z
High-Z
Deselected
Standby
X
L
X
X
X
X
High-Z
High-Z
Deselected
Standby
X
X
X
X
H
H
High-Z
High-Z
Deselected
Standby
L
H
H
H
L
X
High-Z
High-Z
Output Disabled
Active
L
H
H
H
X
L
High-Z
High-Z
Output Disabled
Active
L
H
L
H
L
H
Dout
High-Z
Lower Byte Read
Active
L
H
L
H
H
L
High-Z
Dout
Upper Byte Read
Active
L
H
L
H
L
L
Dout
Dout
Word Read
Active
L
H
X
L
L
H
Din
High-Z
Lower Byte Write
Active
L
H
X
L
H
L
High-Z
Din
Upper Byte Write
Active
L
H
X
L
L
L
Din
Din
Word Write
Active
Note: X means don’t care (must be low or high state).
Absolute Maximum Ratings (4M Version F)
Item
Symbol
Ratings
Unit
Voltage on any pin relative to VSS
VIN,VOUT
-0.2 to VCC+0.3V
V
Voltage on VCC supply relative to VSS
VCC
-0.2 to 4.0V
V
Power Dissipation
PD
1.0
W
Operating Temperature
TA
-40 to 85
°C
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Absolute Maximum Ratings (4M Version G, 8M Version C, 8M Version D)
Item
Symbol
Ratings
Unit
Voltage on any pin relative to VSS
VIN,VOUT
-0.2 to VCC+0.3V (Max. 3.6V)
V
Voltage on VCC supply relative to VSS
VCC
-0.2 to 3.6V
V
Power Dissipation
PD
1.0
W
Operating Temperature
TA
-40 to 85
°C
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
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DC Characteristics
Recommended DC Operating Conditions (Note 1)
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
VCC
2.7
3.0
3.3
V
Ground
VSS
0
0
0
V
Input high voltage
VIH
2.2
-
VCC+0.2 (Note 2)
V
Input low voltage
VIL
-0.2 (Note 3)
-
0.6
V
Notes:
1. TA = -40 to 85°C, unless otherwise specified.
2. Overshoot: Vcc+1.0V in case of pulse width ≤20ns.
3. Undershoot: -1.0V in case of pulse width ≤20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
Capacitance (f=1MHz, TA=25°C)
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
CIN
VIN=0V
-
8
pF
Input/Output capacitance
CIO
VIO=0V
-
10
pF
Note: Capacitance is sampled, not 100% tested
DC Operating Characteristics
Common
Item
Symbol
Test Conditions
Min
Typ
(Note)
Max
Unit
Input leakage current
ILI
VIN=VSS to VCC
-1
-
1
µA
Output leakage current
ILO
CS1#=VIH or CS2=VIL or OE#=VIH or
WE#=VIL or LB#=UB#=VIH, VIO=Vss to VCC
-1
-
1
µA
Output low voltage
VOL
IOL = 2.1mA
-
-
0.4
V
Output high voltage
VOH
IOH = -1.0mA
2.4
-
-
V
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DC Operating Characteristics
4M Version F
Item
Symbol
ICC1
Average operating current
ICC2
Standby Current (CMOS)
Test Conditions
Cycle time=1µs, 100% duty, IIO=0mA, CS1# ≤ 0.2V,
CS2 ≥ VCC-0.2V,
BYTE#=VSS or VCC, VIN ≤ 0.2V or VIN ≥ VCC-0.2V, LB#
≤ 0.2V or/and UB# ≤ 0.2V
Cycle time=Min, IIO=0mA, 100% duty, CS1# = VIL,
CS2=VIH,
BYTE# = VSS or VCC, VIN=VIL or VIH, LB# ≤ 0.2V or/
and UB# ≤ 0.2V
CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V (CS1# controlled)
ISB1 or CS2 ≤ 0.2V (CS2 controlled), BYTE# = V or V ,
SS
CC
(Note)
Other input =0~VCC
Min
Typ
(Note)
Max
Unit
-
-
3
mA
-
-
22
mA
-
1.0
(Note)
10
µA
Note: Typical values are not 100% tested.
DC Operating Characteristics
4M Version G
Item
Symbol
ICC1
Average operating current
ICC2
Standby Current (CMOS)
Test Conditions
Cycle time=1µs, 100% duty, IIO=0mA, CS1# ≤ 0.2V,
CS2 ≥ VCC-0.2V,
BYTE#=VSS or VCC, VIN ≤ 0.2V or VIN ≥ VCC-0.2V, LB#
≤ 0.2V or/and UB# ≤ 0.2V
Cycle time=Min, IIO=0mA, 100% duty, CS1# = VIL,
CS2=VIH,
BYTE# = VSS or VCC, VIN=VIL or VIH, LB# ≤ 0.2V or/
and UB# ≤ 0.2V
CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V (CS1# controlled)
ISB1 or CS2 ≤ 0.2V (CS2 controlled), BYTE# = V or V ,
SS
CC
(Note)
Other input = 0~VCC
Min
Typ
(Note)
Max
Unit
-
-
4
mA
-
-
22
mA
-
3.0
(Note)
10
µA
Note: Typical values are not 100% tested.
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DC Operating Characteristics
8M Version C
Item
Symbol
ICC1
Average operating current
ICC2
Standby Current (CMOS)
Test Conditions
Cycle time=1µs, 100% duty, IIO=0mA, CS1# ≤ 0.2V,
CS2 ≥ VCC-0.2V,
BYTE#=VSS or VCC, VIN ≤ 0.2V or VIN ≥ VCC-0.2V, LB#
≤ 0.2V or/and UB# ≤ 0.2V
Cycle time=Min, IIO=0mA, 100% duty, CS1# = VIL,
CS2=VIH,
BYTE# = VSS or VCC, VIN=VIL or VIH, LB# ≤ 0.2V or/
and UB# ≤ 0.2V
CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V (CS1# controlled)
ISB1 or CS2 ≤ 0.2V (CS2 controlled), BYTE# = V or V ,
SS
CC
(Note)
Other input = 0~VCC
Min
Typ
(Note)
Max
Unit
-
-
3
mA
-
-
22
mA
-
-
15
µA
Min
Typ
(Note)
Max
Unit
-
-
TBD
mA
-
-
TBD
mA
-
-
TBD
µA
Note: Typical values are not 100% tested.
DC Operating Characteristics
8M Version D
Item
Symbol
ICC1
Average operating current
ICC2
Standby Current (CMOS)
Test Conditions
Cycle time=1µs, 100% duty, IIO=0mA, CS1# ≤ 0.2V,
CS2 ≥ VCC-0.2V,
BYTE#=VSS or VCC, VIN ≤ 0.2V or VIN ≥ VCC-0.2V, LB#
≤ 0.2V or/and UB# ≤ 0.2V
Cycle time=Min, IIO=0mA, 100% duty, CS1# = VIL,
CS2=VIH,
BYTE# = VSS or VCC, VIN=VIL or VIH, LB# ≤ 0.2V or/
and UB# ≤ 0.2V
CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V (CS1# controlled)
ISB1 or CS2 ≤ 0.2V (CS2 controlled), BYTE# = V or V ,
SS
CC
(Note)
Other input = 0~VCC
Note: Typical values are not 100% tested.
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AC Operating Conditions
Test Conditions
Test Load and Test Input/Output Reference
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See Figure 32): CL= 30pF+1TTL
VTM (note 3)
R2 (note 2)
CL (note 1)
Figure 32.
R1 (note 2)
AC Output Load
Notes:
1. Including scope and jig capacitance.
2. R1=3070Ω, R2=3150Ω.
3. VTM =2.8V.
AC Characteristics
Read/Write Characteristics (VCC=2.7-3.3V)
Speed Bins
70ns
Read
Parameter List
96
Symbol
Min
Max
Units
Read cycle time
tRC
70
-
ns
Address access time
tAA
-
70
ns
Chip select to output
tCO1, tCO2
-
70
ns
Output enable to valid output
tOE
-
35
ns
LB#, UB# Access Time
tBA
-
70
ns
tLZ1, tLZ2
10
-
ns
LB#, UB# enable to low-Z output
tBLZ
10
-
ns
Output enable to low-Z output
tOLZ
5
-
ns
Chip disable to high-Z output
tHZ1, tHZ2
0
25
ns
UB#, LB# disable to high-Z output
tBHZ
0
25
ns
Output disable to high-Z output
tOHZ
0
25
ns
Output hold from address change
tOH
10
-
ns
Chip select to low-Z output
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
A d v a n c e
I n f o r m a t i o n
Speed Bins
70ns
Write
Parameter List
Symbol
Min
Max
Units
Write cycle time
tWC
70
-
ns
Chip select to end of write
tCW
60
-
ns
Address set-up time
tAS
0
-
ns
Address valid to end of write
tAW
60
-
ns
LB#, UB# valid to end of write
tBW
60
-
ns
Write pulse width
tWP
50
-
ns
Write recovery time
tWR
0
-
ns
Write to output high-Z
tWHZ
0
20
ns
Data to write time overlap
tDW
30
-
ns
Data hold from write time
tDH
0
-
ns
End write to output low-Z
tOW
5
-
ns
Data Retention Characteristics (4M Version F)
Item
Symbol
Test Condition
Min
Typ
Max
Unit
VCC for data retention
VDR
CS1# ≥ VCC-0.2V (Note 1), VIN ≥ 0V. BYTE# = VSS or VCC
1.5
-
3.3
V
Data retention current
IDR
VCC=3.0V, CS1# ≥ VCC-0.2V (Note 1), VIN ≥ 0V
-
1.0
(Note 2)
10
µA
Data retention set-up time
tSDR
0
-
-
Recovery time
tRDR
tRC
-
-
See data retention waveform
ns
Notes:
1. CS1 controlled:CS1#≥ VCC-0.2V. CS2 controlled: CS2 ≤ 0.2V.
2. Typical values are not 100% tested.
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Data Retention Characteristics (4M Version G)
Item
Symbol
Test Condition
Min
Typ
Max
Unit
VCC for data retention
VDR
CS1# ≥ VCC-0.2V (Note 1), VIN ≥ 0V. BYTE# = VSS or VCC
1.5
-
3.3
V
Data retention current
IDR
VCC=1.5V, CS1# ≥ VCC-0.2V (Note 1), VIN ≥ 0V
-
-
3
µA
Data retention set-up time
tSDR
0
-
-
Recovery time
tRDR
tRC
-
-
Min
Typ
Max
Unit
1.5
-
3.3
V
-
-
15
µA
0
-
-
tRC
-
-
Min
Typ
Max
Unit
1.5
-
3.3
V
-
-
TBD
µA
0
-
-
tRC
-
-
See data retention waveform
ns
Notes:
1. CS1 controlled:CS1#≥ VCC-0.2V. CS2 controlled: CS2 ≤ 0.2V.
Data Retention Characteristics (8M Version C)
Item
Symbol
Test Condition
VCC for data retention
VDR
CS1# ≥ VCC-0.2V (Note 1). BYTE# = VSS or VCC
Data retention current
IDR
VCC=3.0V, CS1# ≥ VCC-0.2V (Note 1)
Data retention set-up time
tSDR
Recovery time
tRDR
See data retention waveform
ns
Notes:
1. CS1 controlled:CS1#≥ VCC-0.2V. CS2 controlled: CS2 ≤ 0.2V.
Data Retention Characteristics (8M Version D)
Item
Symbol
Test Condition
VCC for data retention
VDR
CS1# ≥ VCC-0.2V (Note 1), BYTE# = VSS or VCC
Data retention current
IDR
VCC=3.0V, CS1# ≥ VCC-0.2V (Note 1)
Data retention set-up time
tSDR
Recovery time
tRDR
See data retention waveform
ns
Notes:
1. CS1 controlled:CS1#≥ VCC-0.2V. CS2 controlled: CS2 ≤ 0.2V.
Timing Diagrams
tRC
Address
tOH
Data Out
Figure 33.
98
tAA
Previous Data Valid
Data Valid
Timing Waveform of Read Cycle(1) (Address Controlled, CS#1=OE#=VIL, CS2=WE#=VIH, UB#
and/or LB#=VIL)
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
A d v a n c e
I n f o r m a t i o n
tRC
Address
tOH
tAA
tCO1
CS1#
CS2
tCO2
tHZ
tBA
UB#, LB#
tBHZ
tOE
OE#
tOLZ
tBLZ
Data out
tOHZ
tLZ
High-Z
Data Valid
Notes:
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to
output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from
device to device interconnection.
Figure 34.
Timing Waveform of Read Cycle(2) (WE#=VIH, if BYTE# is Low, Ignore UB#/LB# Timing)
tWC
Address
tCW(2)
tWR(4)
CS1#
tAW
CS2
tCW(2)
tBW
UB#, LB#
tWP(1)
WE#
tAS(3)
Data in
tDW
High-Z
Figure 35.
High-Z
Data Valid
tWHZ
Data out
tDH
tOW
Data Undefined
Timing Waveform of Write Cycle(1) (WE# controlled, if BYTE# is Low, Ignore UB#/LB# Timing)
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tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS1#
tAW
CS2
tBW
UB#, LB#
tWP(1)
WE#
tDW
Data Valid
Data in
High-Z
High-Z
Data out
Figure 36.
tDH
Timing Waveform of Write Cycle(2) (CS# controlled, if BYTE# is Low, Ignore UB#/LB# Timing)
tWC
Address
tCW(2)
tWR(4)
CS1#
tAW
CS2
tCW(2)
tBW
UB#, LB#
tAS(3)
tWP(1)
WE#
tDW
Data in
tDH
Data Valid
High-Z
Data out
High-Z
Notes:
1. A write occurs during the overlap (tWP) of low CS1# and low WE#. A write begins when CS1# goes low and WE#
goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double
byte operation. A write ends at the earliest transition when CS1# goes high and WE# goes high. The tWP is
measured from the beginning of write to the end of write.
2. tCW is measured from the CS1# going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS1# or WE#
going high.
Figure 37.
100
Timing Waveform of Write Cycle(3) (UB#, LB# controlled)
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
A d v a n c e
I n f o r m a t i o n
CS1# Controlled
VCC
Data Retention Mode
tSDR
tRDR
2.7V
2.2V
VDR
CS1# VCC - 0.2V
CS1#
GND
CS2 Controlled
VCC
Data Retention Mode
2.7V
CS2
tSDR
tRDR
VDR
0.4V
CS2 0.2V
GND
Figure 38. Data Retention Waveform
March 31, 2005 S71GL032A_00_A0
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A d v a n c e
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Revision Summary
Revision A (March 31, 2005)
Initial release.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other
abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development
by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.
Copyright ©2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and product
names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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