STMICROELECTRONICS 74LVX238TTR

74LVX238
LOW VOLTAGE CMOS 3 TO 8 LINE DECODER
WITH 5V TOLERANT INPUTS
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HIGH SPEED :
tPD = 5.5ns (TYP.) at VCC = 3.3V
5V TOLERANT INPUTS
INPUT VOLTAGE LEVEL :
VIL=0.8V, VIH=2V at VCC=3V
LOW POWER DISSIPATION:
ICC = 2 µA (MAX.) at TA=25°C
LOW NOISE:
VOLP = 0.3V (TYP.) at VCC = 3.3V
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN)
BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
IMPROVED LATCH-UP IMMUNITY
POWER DOWN PROTECTION ON INPUTS
DESCRIPTION
The 74LVX238 is a low voltage CMOS 3 TO 8
LINE DECODER fabricated with sub-micron
silicon gate and double-layer metal wiring C2MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
If the device is enabled, 3 binary select (A, B, and
C) determine which one of the outputs will go high.
If enable input G1 is held low or either G2A or G2B
SOP
TSSOP
ORDER CODES
PACKAGE
TUBE
T&R
SOP
TSSOP
74LVX238M
74LVX238MTR
74LVX238TTR
is held high, the decoding function is inhibited and
all the 8 outputs go low.
Tree enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V
system. It combines high speed performance with
the true CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001
1/9
74LVX238
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL
1, 2, 3
4, 5
6
15, 14, 13,
12, 11, 10, 9,
7
8
16
A, B, C
G2A, G2B
G1
Y0 to Y7
GND
VCC
NAME AND FUNCTION
Address Inputs
Enable Inputs
Enable Input
Outputs
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
INPUTS
OUTPUTS
ENABLE
SELECT
G2B
G2A
G1
C
B
A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
X
X
H
L
L
L
L
L
L
L
L
X
H
X
L
L
L
L
L
L
L
L
L
X
X
H
H
H
H
H
H
H
H
X
X
X
L
L
L
L
H
H
H
H
X
X
X
L
L
H
H
L
L
H
H
X
X
X
L
H
L
H
L
H
L
H
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
X : Don’t Care
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
2/9
74LVX238
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Value
Unit
Supply Voltage
-0.5 to +7.0
V
VI
DC Input Voltage
-0.5 to +7.0
V
VO
DC Output Voltage
-0.5 to VCC + 0.5
V
IIK
DC Input Diode Current
- 20
mA
IOK
DC Output Diode Current
± 20
mA
IO
DC Output Current
± 25
mA
± 50
mA
ICC or IGND DC VCC or Ground Current
Tstg
Storage Temperature
TL
Lead Temperature (10 sec)
-65 to +150
°C
300
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Value
Unit
Supply Voltage (note 1)
2 to 3.6
V
VI
Input Voltage
0 to 5.5
V
VO
Output Voltage
Top
Operating Temperature
dt/dv
Input Rise and Fall Time (note 2) (VCC = 3.3V)
0 to VCC
V
-55 to 125
°C
0 to 100
ns/V
1) Truth Table guaranteed: 1.2V to 3.6V
2) VIN from 0.8V to 2.0V
DC SPECIFICATIONS
Test Condition
Symbol
VIH
VIL
VOH
VOL
II
ICC
Parameter
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
Low Level Output
Voltage
Input Leakage
Current
Quiescent Supply
Current
Value
TA = 25°C
VCC
(V)
Min.
2.0
3.0
3.6
2.0
3.0
3.6
Typ.
Max.
1.5
2.0
2.4
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
1.5
2.0
2.4
0.5
0.8
0.8
Max.
1.5
2.0
2.4
0.5
0.8
0.8
V
0.5
0.8
0.8
2.0
IO=-50 µA
1.9
2.0
1.9
1.9
3.0
IO=-50 µA
2.9
3.0
2.9
2.9
2.58
Unit
V
V
3.0
IO=-4 mA
2.0
IO=50 µA
0.0
3.0
IO=50 µA
0.0
0.1
0.1
0.1
3.0
IO=4 mA
0.36
0.44
0.55
3.6
VI = 5V or GND
± 0.1
±1
±1
µA
3.6
VI = VCC or GND
2
20
20
µA
2.48
0.1
2.4
0.1
0.1
V
3/9
74LVX238
DYNAMIC SWITCHING CHARACTERISTICS
Test Condition
Symbol
VOLP
VOLV
VIHD
VILD
Parameter
Dynamic Low
Voltage Quiet
Output (note 1, 2)
Dynamic High
Voltage Input (note
1, 3)
Dynamic Low
Voltage Input (note
1, 3)
Value
TA = 25°C
VCC
(V)
Min.
3.3
-0.5
3.3
Typ.
Max.
0.3
0.5
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
Unit
Max.
-0.3
2
CL = 50 pF
V
3.3
0.8
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns)
Test Condition
Symbol
Parameter
tPLH tPHL Propagation Delay
Time
A, B, C to Y
tPLH tPHL Propagation Delay
Time
G1 to Y
tPLH tPHL Propagation Delay
Time
G2A or G2B to Y
tOSLH
tOSHL
Output To Output
Skew Time (note1,
2)
Value
TA = 25°C
-40 to 85°C
-55 to 125°C
Max.
Min.
Max.
Min.
Max.
13.8
17.3
1.0
1.0
16.5
20.0
1.0
1.0
18.5
22.0
8.8
1.0
10.5
1.0
11.5
14.0
1.0
15.0
19.5
23.0
1.0
1.0
205
25.0
12.5
1.0
13.5
1.0
16.0
1.0
17.0
16.0
19.5
1.0
1.0
18.5
22.0
1.0
1.0
19.5
23.0
6.9
10.4
1.0
11.5
1.0
13.5
50
9.4
13.9
1.0
15.0
1.0
17.0
50
0.5
0.5
1.0
1.0
VCC
(V)
CL
(pF)
Typ.
2.7
2.7
15
50
7.1
9.6
3.3(*)
15
5.5
3.3(*)
2.7
2.7
50
8.0
12.3
1.0
15
50
8.7
11.2
16.3
19.8
1.0
1.0
3.3(*)
15
6.8
10.6
1.0
3.3(*)
2.7
2.7
50
9.3
14.1
15
50
8.8
11.3
3.3(*)
15
3.3(*)
2.7
3.3
(*)
50
Min.
1.5
1.5
1.5
1.5
Unit
ns
ns
ns
ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
4/9
74LVX238
CAPACITIVE CHARACTERISTICS
Test Condition
Symbol
Parameter
TA = 25°C
VCC
(V)
CIN
Input Capacitance
3.3
CPD
Power Dissipation
Capacitance
(note 1)
3.3
Value
Min.
fIN = 10MHz
Typ.
Max.
4
10
34
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
10
Unit
Max.
10
pF
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
TEST CIRCUIT
CL =15/50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
5/9
74LVX238
WAVEFORM 1: PROPAGATION DELAYS FOR INVERTING OUTPUTS (f=1MHz; 50% duty cycle)
WAVEFORM 2: PROPAGATION DELAYS FOR NON-INVERTING OUTPUTS (f=1MHz; 50% duty cycle)
6/9
74LVX238
SO-16 MECHANICAL DATA
DIM.
mm.
MIN.
TYP
A
a1
inch
MAX.
MIN.
TYP.
1.75
0.1
0.068
0.2
a2
MAX.
0.003
0.007
1.65
0.064
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.019
c1
45° (typ.)
D
9.8
10
0.385
0.393
E
5.8
6.2
0.228
0.244
e
1.27
0.050
e3
8.89
0.350
F
3.8
4.0
0.149
0.157
G
4.6
5.3
0.181
0.208
L
0.5
1.27
0.019
0.050
M
S
0.62
0.024
8° (max.)
PO13H
7/9
74LVX238
TSSOP16 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
A
MAX.
MIN.
TYP.
MAX.
1.2
A1
0.05
A2
0.8
b
0.047
0.15
0.002
0.004
0.006
1.05
0.031
0.039
0.041
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.0089
D
4.9
5
5.1
0.193
0.197
0.201
E
6.2
6.4
6.6
0.244
0.252
0.260
E1
4.3
4.4
4.48
0.169
0.173
0.176
1
e
0.65 BSC
K
0°
L
0.45
A
0.60
0.0256 BSC
8°
0°
0.75
0.018
8°
0.024
0.030
A2
A1
b
e
K
c
L
E
D
E1
PIN 1 IDENTIFICATION
1
0080338D
8/9
74LVX238
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consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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