STMICROELECTRONICS 74VHCT373A

74VHCT373A

OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT NON INVERTING
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HIGH SPEED: tPD = 6.4 ns (TYP.) at VCC = 5V
LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 oC
COMPATIBLE WITH TTL OUTPUTS:
VIH = 2V (MIN), VIL = 0.8V (MAX)
POWER DOWN PROTECTION ON INPUTS &
OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: VOLP = 0.9V (Max.)
DESCRIPTION
The 74VHCT373A is an advanced high-speed
CMOS OCTAL D-TYPE LATCH with 3 STATE
OUTPUT NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology.
This 8 bit D-Type latch is controlled by a latch
enable input (LE) and an output enable input
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74VHCT373AM
74VHCT373AT
(OE).
While the LE input is held at a high level, the Q
outputs will follow the data inputs precisely. When
the LE is taken low, the Q outputs will be latched
precisely at the logic level of D input data. While
the (OE) input is low, the 8 outputs will be in a
normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
November 1999
1/10
74VHCT373A
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL
1
OE
NAME AND FUNCT ION
2, 5, 6,
9, 12, 15,
16, 19
Q0 to Q7
3 State Outputs
3, 4, 7,
8, 13, 14,
17, 18
D0 to D7
Data Inputs
11
LE
Latch Enable
Input
10
GND
Ground (0V)
20
VCC
Positive Supply Voltage
3 State Output Enable
Input (Active LOW)
TRUTH TABLE
INPUTS
OUT PUTS
OE
LE
D
H
X
X
Z
L
L
X
NO CHANGE *
L
H
L
L
L
H
H
H
X:DON’T CARE
Z: HIGH IMPEDANCE
*: Q OUTPUTSARE LATCHED AT THE TIME WHEN THE LEINPUT ISTAKEN LOW LOGIC LEVEL.
LOGIC DIAGRAM
2/10
Q
74VHCT373A
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Supply Voltage
Value
Unit
-0.5 to +7.0
V
VI
DC Input Voltage
-0.5 to +7.0
V
VO
DC Output Voltage (see note 1)
-0.5 to +7.0
V
VO
DC Output Voltage (see note 2)
-0.5 to VCC + 0.5
V
IIK
DC Input Diode Current
- 20
mA
IOK
DC Output Diode Current
± 20
mA
IO
DC Output Current
± 25
mA
± 50
mA
ICC or IGND DC VCC or Ground Current
Tstg
TL
Storage Temperature
Lead Temperature (10 sec)
-65 to +150
o
300
o
C
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
1) Output in OFF State
2) High or Low State
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Supply Voltage
Valu e
Unit
4.5 to 5.5
V
VI
Input Voltage
0 to 5.5
V
VO
Output Voltage (see note 1)
0 to 5.5
V
VO
Output Voltage (see note 2)
Top
Operating Temperature
dt/dv
Input Rise and Fall Time (see note 3) (V CC = 5.0 ± 0.5V)
0 to VCC
-40 to +85
0 to 20
V
o
C
ns/V
1) Output in OFF State
2) High or Low State
3)VIN from0.8V to 2 V
3/10
74VHCT373A
DC SPECIFICATIONS
Symb ol
Parameter
T est Cond ition s
Min.
2
VIH
High Level Input
Voltage
4.5 to 5.5
VIL
Low Level Input
Voltage
4.5 to 5.5
VOH
High Level Output
Voltage
VOL
IOZ
II
Value
T A = 25 o C
V CC
(V)
Typ .
Un it
-40 to 85 o C
Max.
Min .
Max.
2
0.8
V
0.8
V
4.5
I O =-50 µA
4.4
4.5
IO=-8 mA
3.94
Low Level Output
Voltage
4.5
I O=50 µA
0.1
0.1
4.5
IO=8 mA
0.36
0.44
High Impedance
Output Leakage
Current
4.5 to 5.5
VI = VIH or VIL
VO = 0V to 5.5V
±0.25
±2.5
µA
0 to 5.5
VI = 5.5V or GND
±0.1
±1.0
µA
Input Leakage Current
4.5
4.4
V
3.8
0.0
V
ICC
Quiescent Supply
Current
5.5
VI = VCC or GND
4
40
µA
∆ICC
Additional Worst Case
Supply Current
5.5
One Input at 3.4V,
other input at VCC or
GND
1.35
1.5
mA
IOPD
Output Leakage
Current
0
VOUT = 5.5V
0.5
5.0
µA
AC ELECTRICAL CHARACTERISTICS (Input t r = tf =3 ns)
Symb ol
Parameter
V CC
(V)
Test Co ndition
CL
(pF )
(*)
Value
T A = 25 o C
Min. Typ . Max.
Un it
-40 to 85 o C
Min . Max.
tPLH
tPHL
Propagation Delay
Time LE to Q
5.0
5.0(*)
15
50
5.4
6.0
12.3
13.3
1.0
1.0
13.5
14.5
ns
tPLH
tPHL
Propagation Delay
Time D to Q
5.0(*)
5.0(*)
15
50
6.4
7.1
8.5
9.5
1.0
1.0
9.5
10.5
ns
tPZL
tPZH
Output EnableTime
5.0(*)
15
6.2
10.9
1.0
12.5
tPLZ
tPHZ
tw
Output Disable Time
5.0(*)
5.0(*)
50
50
6.9
6.7
11.9
11.2
1.0
1.0
13.5
12.0
Pulse Width (LE)
HIGH
5.0(*)
6.5
8..5
ns
ts
Setup Time D to LE
HIGH or LOW
5.0(*)
1.5
1.5
ns
th
Hold Time D toLE
HIGH or LOW
5.0(*)
3.5
3.5
ns
Output to Output Skew
Time (note 1)
5.0(*)
tOSLH
tOSHL
R L = 1KΩ
R L = 1KΩ
50
(*) Voltage range is 5V ± 0.5V
Note 1: Parameter guaranteed by design. tsoLH = |tpLHm- tpLHn|, tsoHL = |tpHLm - tpHLn|
4/10
1.0
1.0
ns
ns
ns
74VHCT373A
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
T est Cond ition s
Value
T A = 25 o C
Min.
Un it
-40 to 85 o C
Typ .
Max.
Input Capacitance
4
10
COUT
Output Capacitance
9
pF
CPD
Power Dissipation
Capacitance (note 1)
14
pF
C IN
Min .
Max.
10
pF
1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operating current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/8 (per Latch)
DYNAMIC SWITCHING CHARACTERISTICS
Symb ol
Parameter
T est Cond ition s
Dynamic Low Voltage
Quiet Output (note 1, 2)
5.0
VIHD
Dynamic High Voltage
Input (note 1, 3)
5.0
VILD
Dynamic Low Voltage
Input (note 1, 3)
5.0
VOLP
VOLV
Value
o
Min.
-0.9
C L = 50 pF
Un it
o
T A = 25 C
V CC
(V)
-40 to 85 C
Typ .
Max.
0.6
0.9
Min .
Max.
-0.6
2.0
V
0.8
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.0V, (n -1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to3.0V. Inputs under test switching: 3.0V to threshold (VILD), 0V to threshold (VIHD), f=1MHz.
TEST CIRCUIT
T EST
tPLH , tPHL
SW IT CH
Open
tPZL , tPLZ
VCC
tPZH , tPHZ
GND
CL = 15/50 pF or equivalent (includes jig and probe capacitance)
RL = R1 = 1KΩ orequivalent
RT = ZOUT of pulse generator (typically 50Ω)
5/10
74VHCT373A
WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH,
Dn TO LE SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
6/10
74VHCT373A
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 3: PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
7/10
74VHCT373A
SO-20 MECHANICAL DATA
mm
DIM.
MIN.
TYP.
A
a1
inch
MAX.
MIN.
TYP.
2.65
0.10
0.104
0.20
a2
MAX.
0.004
0.007
2.45
0.096
b
0.35
0.49
0.013
0.019
b1
0.23
0.32
0.009
0.012
C
0.50
0.020
c1
45 (typ.)
D
12.60
13.00
0.496
0.512
E
10.00
10.65
0.393
0.419
e
1.27
0.050
e3
11.43
0.450
F
7.40
7.60
0.291
0.299
L
0.50
1.27
0.19
0.050
M
S
0.75
0.029
8 (max.)
P013L
8/10
74VHCT373A
TSSOP20 MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
A
MIN.
TYP.
MAX.
1.1
0.433
A1
0.05
0.10
0.15
0.002
0.004
0.006
A2
0.85
0.9
0.95
0.335
0.354
0.374
b
0.19
0.30
0.0075
0.0118
c
0.09
0.2
0.0035
0.0079
D
6.4
6.5
6.6
0.252
0.256
0.260
E
6.25
6.4
6.5
0.246
0.252
0.256
E1
4.3
4.4
4.48
0.169
0.173
0.176
e
0.65 BSC
0.0256 BSC
K
0o
4o
8o
0o
4o
8o
L
0.50
0.60
0.70
0.020
0.024
0.028
A
A2
A1
b
K
e
L
E
c
D
E1
PIN 1 IDENTIFICATION
1
9/10
74VHCT373A
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems withoutexpress written approval of STMicroelectronics.
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 1999 STMicroelectronics – Printed in Italy – All Rights Reserved
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