74LVX373 LOW VOLTAGE OCTAL D-TYPE LATCH (3-STATE NON INV.) WITH 5V TOLERANT INPUTS ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 5.8 ns (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS POWER-DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC = 3V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.3 V (TYP.) at VCC = 3.3V SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 3.6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The LVX373 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. This 8 bit D-Type latch is controlled by a latch enable input (LE) and an output enable input (OE). M (Micro Package) T (TSSOP Package) ORDER CODES : 74LVX373M 74LVX373T While the LE input is held at a high level, the Q outputs will follow the data input precisely. When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. It has better speed performance at 3.3V than 5V LS-TTL family combined with the true CMOS low power consuption. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS May 1999 1/10 74LVX373 INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1 OE NAME AND FUNCT ION 2, 5, 6, 9, 12, 15, 17, 18 Q0 to Q7 3 State Outputs 3, 4, 7, 8, 13, 14, 17, 18 D0 to D7 Data Inputs 11 LE Latch Enable Input 10 GND Ground (0V) 20 VCC Positive Supply Voltage 3 State Output Enable Input (Active LOW) TRUTH TABLE INPUT S LE D H X X Z L L X NO CHANGE * Q L H L L L H H H X: Don’t care Z: High impedance * Q outputs are latched at the time when the LE input is taken low. LOGICS DIAGRAM 2/10 OUTPUTS OE 74LVX373 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage VI DC Input Voltage VO DC Output Voltage Value Unit -0.5 to +7.0 V -0.5 to 7.0 V -0.5 to VCC + 0.5 V IIK DC Input Diode Current - 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 25 mA ± 50 mA ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) -65 to +150 o 300 o C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage (note 1) Valu e Unit 2 to 3.6 V V VI Input Voltage 0 to 5.5 VO Output Voltage 0 to VCC Top dt/dv Operating Temperature: Input Rise and Fall Time (VCC = 3V) (note 2) -40 to +85 0 to 100 V o C ns/V 1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2V 3/10 74LVX373 DC SPECIFICATIONS Symb ol VIH VIL Parameter High Level Input Voltage Low Level Input Voltage Test Co nditions Valu e T A = 25 oC Min. 2.0 1.5 1.5 3.0 2.0 2.0 3.6 2.4 T yp. Max. Max. V 2.4 0.5 0.5 3.0 0.8 0.8 0.8 0.8 High Level Output Voltage 2.0 Low Level Output Voltage 2.0 3.0 3.0 VOL Min. 2.0 3.6 VOH Un it -40 to 85 o C V CC (V) 3.0 VI = V IH or V IL I O =-50 µA 1.9 2.0 1.9 IO=-50 µA 2.9 3.0 2.9 IO=-4 mA 2.58 VI(*) = VIH or VIL IO=50 µA 0.0 0.1 0.1 IO=50 µA 0.0 0.1 0.1 (* ) V V 2.48 0.36 0.44 Input Leakage Current 3.6 VI = 5V or GND ±0.1 ±1 µA IOZ 3 State Output Leakage Current 3.6 VI = VIH or VIL VO = VCC or GND ±0.25 ±2.5 µA ICC Quiescent Supply Current 3.6 VI = VCC or GND 2 20 µA 3.0 II IO=4 mA V (*) All outputs loaded. DYNAMIC SWITCHING CHARACTERISTICS Symb ol Parameter Test Co nditions Dynamic Low Voltage Quiet Output (note 1, 2) 3.3 VIHD Dynamic High Voltage Input (note 1, 3) 3.3 VILD Dynamic Low Voltage Input (note 1, 3) 3.3 VOLP VOLV Valu e T A = 25 oC V CC (V) Min. T yp. Max. 0.3 0.8 -0.8 -0.3 2 C L = 50 pF Un it -40 to 85 o C Min. Max. V 0.8 1) Worst case package 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n -1) outputs switching and one output at GND 3) max number of data inputs (n) switching. (n-1) switching 0V to3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD). f=1MHz 4/10 74LVX373 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf =3 ns) Symb ol Parameter T est Con ditio n CL (p F) V CC (V) tPLH tPHL Propagation Delay Time LE to Q tPLH tPHL Propagation Delay Time D to Q tPZL tPZH Output Enable Time 2.7 2.7 15 50 3.3(*) 3.3(*) 2.7 2.7 3.3(*) 3.3(*) 2.7 15 50 15 50 15 50 15 2.7 3.3(*) 50 15 50 50 50 50 50 50 tw LE pulse Width, HIGH ts Setup Time D to LE HIGH or LOW 3.3(*) 2.7 3.3(*) 2.7 3.3(*) 2.7 3.3(*) Hold Time D to LE HIGH or LOW 2.7 3.3(*) Output to Output Skew Time (note 1, 2) 3.3 tPLZ tPHZ th tOSLH tOSHL Output Disable Time 2.7 (*) R L = 1 kΩ R L = 1 kΩ 50 50 50 Valu e T A = 25 oC -40 to Min. T yp. Max. Min. 7.5 14.5 1.0 10.0 18.0 1.0 Un it 85 o C Max. 17.5 21.0 ns 6.8 9.3 7.7 10.2 6.0 8.5 7.7 10.3 13.8 15.0 18.5 9.7 13.2 15.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 12.0 15.5 18.5 22.0 11.5 15.0 18.5 ns 10.2 6.0 18.5 9.7 1.0 1.0 22.0 11.5 ns 8.5 9.8 8.2 6.5 5.0 6.0 4.0 13.2 18.0 12.8 1.0 1.0 1.0 15.0 21.0 14.5 7.5 5.0 6.0 4.0 1.0 1.0 1.0 1.0 50 0.5 1.0 1.5 50 0.5 1.0 1.5 ns ns ns ns ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the same direction, either HIGH or LOW 2) Parameter guaranteed by design (*) Voltage range is 3.3V ± 0.3V CAPACITIVE CHARACTERISTICS Symb ol Parameter Test Co nditions C IN Valu e o Un it o -40 to 85 C T A = 25 C Min. T yp. Max. Min. Max. V CC (V) Input Capacitance 3.3 5 pF COUT Output Capacitance 3.3 10 pF CPD Power Dissipation Capacitance (note 1) 3.3 10 pF fIN = 10 MHz 1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operting current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/8(per circuit) 5/10 74LVX373 TEST CIRCUIT T EST tPLH , tPHL SW IT CH Open tPZL , tPLZ VCC tPZH , tPHZ GND CL = 15/50 pF or equivalent (includes jig and probe capacitance) RL = R1 = 1KΩ orequivalent RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 6/10 74LVX373 WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) WAVEFORM 3: PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) 7/10 74LVX373 SO-20 MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 2.65 0.10 0.104 0.20 a2 MAX. 0.004 0.007 2.45 0.096 b 0.35 0.49 0.013 0.019 b1 0.23 0.32 0.009 0.012 C 0.50 0.020 c1 45 (typ.) D 12.60 13.00 0.496 0.512 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.40 7.60 0.291 0.299 L 0.50 1.27 0.19 0.050 M S 0.75 0.029 8 (max.) P013L 8/10 74LVX373 TSSOP20 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. A MIN. TYP. MAX. 1.1 0.433 A1 0.05 0.10 0.15 0.002 0.004 0.006 A2 0.85 0.9 0.95 0.335 0.354 0.374 b 0.19 0.30 0.0075 0.0118 c 0.09 0.2 0.0035 0.0079 D 6.4 6.5 6.6 0.252 0.256 0.260 E 6.25 6.4 6.5 0.246 0.252 0.256 E1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 BSC 0.0256 BSC K 0o 4o 8o 0o 4o 8o L 0.50 0.60 0.70 0.020 0.024 0.028 A A2 A1 b K e L E c D E1 PIN 1 IDENTIFICATION 1 9/10 74LVX373 Information furnished is believed to be accurate and reliable. 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