74VHCT574A OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 180 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN), VIL = 0.8V (MAX) POWER DOWN PROTECTION ON INPUTS & OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 574 IMPROVED LATCH-UP IMMUNITY LOW NOISE VOLP = 0.9V (Max.) DESCRIPTION The 74VHCT574A is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. This 8 bit D-Type flip-flop is controlled by a clock input (CK) and an output enable input (OE). On the positive transition of the clock, the Q M (Micro Package) T (TSSOP Package) ORDER CODES : 74VHCT574AM 74VHCT574AT outputs will be set to logic states that were setup at the D inputs. While the OE input is low, the 8 outputs will be in a normal logic state (high or low logic level) and, while high level, the outputs will be in a high impedance state. The output control does not affect the internal operation of flip flop; that is, the old data can be retained or the new data can be entered even while the outputs are off. Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS August 1999 1/10 74VHCT574A INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1 OE NAME AND FUNCT ION 2, 3, 4, 5, 6, 7, 8, 9 D0 to D7 Data Inputs 12, 13, 14, 15, 16, 17, 18, 19 Q0 to Q7 3 State Outputs 11 CLOCK Clock Input (LOW to HIGH, edge triggered) 10 GND Ground (0V) 20 VCC Positive Supply Voltage 3 State Output Enable Input (Active LOW) TRUTH TABLE INPUTS CK D H X X Z X NO CHANGE L Q L L L L H H X:Don’t Care Z: High Impedance LOGIC DIAGRAM 2/10 OUT PUTS OE 74VHCT574A ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage Value Unit -0.5 to +7.0 V VI DC Input Voltage -0.5 to +7.0 V VO DC Output Voltage (see note 1) -0.5 to +7.0 V VO DC Output Voltage (see note 2) -0.5 to VCC + 0.5 V IIK DC Input Diode Current - 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 25 mA ± 50 mA ICC or IGND DC VCC or Ground Current Tstg TL Storage Temperature Lead Temperature (10 sec) -65 to +150 o 300 o C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. 1) Output in OFF State 2) High or Low State RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage Valu e Unit 4.5 to 5.5 V VI Input Voltage 0 to 5.5 V VO Output Voltage (see note 1) 0 to 5.5 V VO Output Voltage (see note 2) Top Operating Temperature dt/dv Input Rise and Fall Time (see note 3) (V CC = 5.0 ± 0.5V) 0 to VCC -40 to +85 0 to 20 V o C ns/V 1) Output in OFF State 2) High or Low State 3)VIN from0.8V to 2 V 3/10 74VHCT574A DC SPECIFICATIONS Symb ol Parameter T est Cond ition s Min. 2 VIH High Level Input Voltage 4.5 to 5.5 VIL Low Level Input Voltage 4.5 to 5.5 VOH High Level Output Voltage VOL IOZ II Value T A = 25 o C V CC (V) Typ . Un it -40 to 85 o C Max. Min . Max. 2 0.8 V 0.8 V 4.5 I O =-50 µA 4.4 4.5 IO=-8 mA 3.94 Low Level Output Voltage 4.5 I O=50 µA 0.1 0.1 4.5 IO=8 mA 0.36 0.44 High Impedance Output Leakage Current 4.5 to 5.5 VI = VIH or VIL VO = 0V to 5.5V ±0.25 ±2.5 µA 0 to 5.5 VI = 5.5V or GND ±0.1 ±1.0 µA Input Leakage Current 4.5 4.4 V 3.8 0.0 V ICC Quiescent Supply Current 5.5 VI = VCC or GND 4 40 µA ∆ICC Additional Worst Case Supply Current 5.5 One Input at 3.4V, other input at VCC or GND 1.35 1.5 mA IOPD Output Leakage Current 0 VOUT = 5.5V 0.5 5.0 µA AC ELECTRICAL CHARACTERISTICS (Input t r = tf =3 ns) Symb ol Parameter V CC (V) Test Co ndition CL (pF ) (*) tPLH tPHL Propagation Delay Time CK to Q 5.0 5.0(*) 15 tPZL tPZH Output EnableTime tPLZ tPHZ fMAX Output Disable Time 5.0(*) 5.0(*) 5.0(*) 15 50 50 Maximum Clock Frequency 5.0(*) 5.0(*) 15 Output to Output Skew Time (note 1) 5.0(*) 50 tOSLH tOSHL 50 RL=1KΩ RL=1KΩ 50 (*) Voltage range is 5V ± 0.5V Note 1: Parameter guaranteed by design. tsoLH = |tpLHm- tpLHn|, tsoHL = |tpHLm - tpHLn| 4/10 Value T A = 25 o C Min. Typ . Max. 90 85 Un it -40 to 85 o C Min . Max. 4.1 5.6 9.4 10.4 1.0 1.0 10.5 11.5 6.5 7.3 7.0 10.2 11.2 11.2 1.0 1.0 1.0 11.5 12.5 12.0 140 130 80 1.5 ns ns ns MHz 1.5 ns 74VHCT574A CAPACITIVE CHARACTERISTICS Symb ol Parameter T est Cond ition s Value T A = 25 o C Min. Un it -40 to 85 o C Typ . Max. Input Capacitance 4 10 COUT Output Capacitance 9 pF CPD Power Dissipation Capacitance (note 1) 25 pF C IN Min . Max. 10 pF 1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operating current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/8 (per Flip-Flop) DYNAMIC SWITCHING CHARACTERISTICS Symb ol Parameter T est Cond ition s Dynamic Low Voltage Quiet Output (note 1, 2) 5.0 VIHD Dynamic High Voltage Input (note 1, 3) 5.0 VILD Dynamic Low Voltage Input (note 1, 3) 5.0 VOLP VOLV Value o Min. -1.6 C L = 50 pF Un it o T A = 25 C V CC (V) -40 to 85 C Typ . Max. 1.2 1.6 Min . Max. -1.2 3.5 V 1.5 1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n -1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to5.0V. Inputs under test switching: 5.0V to threshold (VILD), 0V to threshold (VIHD), f=1MHz. 5/10 74VHCT574A TEST CIRCUIT T EST t PLH, tPHL SWIT CH Open t PZL, tPLZ VCC t PZH, t PHZ GND CL = 15/50 pF or equivalent (includes jig and probe capacitance) RL = R1 = 1KΩ or equivalent RT = ZOUT ofpulse generator (typically 50Ω) WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 6/10 74VHCT574A WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) WAVEFORM 3: PULSE WIDTH 7/10 74VHCT574A SO-20 MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 2.65 0.10 0.104 0.20 a2 MAX. 0.004 0.007 2.45 0.096 b 0.35 0.49 0.013 0.019 b1 0.23 0.32 0.009 0.012 C 0.50 0.020 c1 45 (typ.) D 12.60 13.00 0.496 0.512 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.40 7.60 0.291 0.299 L 0.50 1.27 0.19 0.050 M S 0.75 0.029 8 (max.) P013L 8/10 74VHCT574A TSSOP20 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. A MIN. TYP. MAX. 1.1 0.433 A1 0.05 0.10 0.15 0.002 0.004 0.006 A2 0.85 0.9 0.95 0.335 0.354 0.374 b 0.19 0.30 0.0075 0.0118 c 0.09 0.2 0.0035 0.0079 D 6.4 6.5 6.6 0.252 0.256 0.260 E 6.25 6.4 6.5 0.246 0.252 0.256 E1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 BSC 0.0256 BSC K 0o 4o 8o 0o 4o 8o L 0.50 0.60 0.70 0.020 0.024 0.028 A A2 A1 b K e L E c D E1 PIN 1 IDENTIFICATION 1 9/10 74VHCT574A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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