74VHCT16374A 16-BIT D-TYPE FLIP FLOP WITH 3-STATE OUTPUTS NON INVERTING ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 185 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS: VIH =2V (MIN.) VIL = 0.8 (MAX.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 16374 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.9V (MAX.) TSSOP ORDER CODES PACKAGE TSSOP TUBE T&R 74VHCT16374ATTR PIN CONNECTION DESCRIPTION The 74VHCT16374A is an advanced high-speed CMOS 16 D-TYPE FLIP FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 16 bit D-TYPE flip-flop is controlled by two clock inputs (CK) and two output enable inputs (nOE). The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock, the Q outputs will be set to the logic state that were setup at the D inputs. While the (OE) input is low, the outputs will be in a normal logic state (high or low logic level); while OE is high, the outputs will be in a high impedance state. The output control does not affect the internal operation of flip-flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. February 2002 1/9 74VHCT16374A INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1 1OE 2, 3, 5, 6, 8, 9, 11, 12 13, 14, 16, 17, 19, 20, 22, 23 24 1Q0 to 1Q7 2Q0 to 2Q7 2OE IEC LOGIC SYMBOLS NAME AND FUNCTION 3 State Output Enable Input (Active LOW) 3-State Outputs 3-State Outputs 3 State Output Enable Input (Active LOW) 25 2CK Clock Input (LOW-to-HIGH Edge Trigger) 36, 35, 33, 32, 2D0 to 2D7 Data Inputs 30, 29, 27, 26 47, 46, 44, 43, 1D0 to 1D7 Data Inputs 41, 40, 38, 37 48 1CK Clock Input (LOW-to-HIGH Edge Trigger) 4, 10, 15, 21, GND Ground (0V) 28, 34, 39, 45 7, 18, 31, 42 V CC Positive Supply Voltage TRUTH TABLE INPUTS OE CK D Q H X X Z L X NO CHANGE L L L L H H X : Don’t Care Z : High Impedance 2/9 OUTPUTS 74VHCT16374A LOGIC DIAGRAM This logic diagram has not to be used to estimate propagation delays ABSOLUTE MAXIMUM RATINGS Symbol V CC Parameter Supply Voltage VI DC Input Voltage VO DC Output Voltage Value Unit -0.5 to +7.0 V -0.5 to +7.0 V -0.5 to VCC + 0.5 - 20 V mA IIK DC Input Diode Current IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 25 mA ICC or IGND DC VCC or Ground Current Storage Temperature Tstg TL Lead Temperature (10 sec) ± 75 mA -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied RECOMMENDED OPERATING CONDITIONS Symbol V CC Parameter Supply Voltage VI Input Voltage VO Output Voltage Top Operating Temperature dt/dv Input Rise and Fall Time (note 1) (Vcc= 5.0±0.5V) Value Unit 4.5 to 5.5 V 0 to 5.5 V 0 to VCC V -55 to 125 °C 0 to 20 ns/V 1) VIN from 0.8V to 2.0V 3/9 74VHCT16374A DC SPECIFICATIONS Test Condition Symbol VIH V IL VOH VOL I OZ II ICC Parameter 4.5 to 5.5 4.5 to 5.5 Low Level Output Voltage High Impedance Output Leakage Current Input Leakage Current Quiescent Supply Current TA = 25°C VCC (V) High Level Input Voltage Low Level Input Voltage High Level Output Voltage Value Min. Typ. Max. 2 -40 to 85°C -55 to 125°C Min. Min. 2 0.8 4.5 IO=-50 µA 4.4 4.5 IO=-8 mA 3.94 4.5 IO=50 µA 4.5 Max. 4.5 0.0 Max. 2 0.8 V 0.8 4.4 4.4 3.8 3.7 Unit V V 0.1 0.1 0.1 IO=8 mA 0.36 0.44 0.55 5.5 VI = VIH or VIL VO = VCC or GND ±0.25 ± 2.5 ± 2.5 µA 0 to 5.5 VI = 5.5V or GND ± 0.1 ±1 ±1 µA 5.5 VI = VCC or GND 4 40 40 µA V AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns) Test Condition Symbol Parameter VCC (V) CL (pF) Value TA = 25°C Min. Typ. -55 to 125°C Max. Min. Max. Min. Max. tPLH tPHL Propagation Delay Time CK to Q 5.0 (*) 15 5.6 9.4 1.0 10.5 1.0 10.5 (*) 50 6.4 10.4 1.0 11.5 1.0 11.5 tPZL tPZH Output Enable Time 5.0 (*) 15 6.2 10.2 1.0 11.5 1.0 11.5 (*) 50 7.3 11.2 1.0 12.5 1.0 12.5 tPLZ tPHZ Output Disable Time 5.0 (*) 50 7.0 11.2 1.0 12.0 1.0 12.0 tw ts th fMAX tOSLH tOSHL Clock Pulse Width HIGH or LOW Setup Time D to CK HIGH or LOW Hold Time D to CK HIGH or LOW Maximum Clock Frequency Output to Output Skew time (note 1) 5.0 5.0 RL = 1KΩ RL = 1KΩ Unit ns ns ns 5.0 (*) 6.5 6.5 6.5 ns 5.0 (*) 2.5 2.5 2.5 ns 5.0 (*) 2.5 2.5 2.5 ns 5.0 (*) 15 90 140 110 80 5.0 (*) 50 85 130 75 75 5.0 (*) 50 (*) Voltage range is 5.0V ± 0.5V (Note 1 : Parameter guaranteed by design. tsoLH = |tpLHm - tpLHn|, tsoHL = |t pHLm - tpHLn| 4/9 -40 to 85°C 1.0 1.0 MHz 1.0 ns 74VHCT16374A CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter CIN Input Capacitance C OUT Output Capacitance Power Dissipation Capacitance (note 1) C PD TA = 25°C VCC (V) 5.0 Value Min. fIN = 10MHz Typ. Max. 4 10 -40 to 85°C -55 to 125°C Min. Min. Max. 10 Unit Max. 10 pF 6 pF 21 pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/16 (per Latch) DYNAMIC SWITCHING CHARACTERISTICS Test Condition Symbol VOLP V OLV V IHD VILD Parameter Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) TA = 25°C VCC (V) Min. 5.0 5.0 5.0 Value -0.9 C L = 50 pF Typ. Max. 0.6 0.9 -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. V -0.6 3.5 V 1.5 V 1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (VILD), 0V to threshold (VIHD), f=1MHz. 5/9 74VHCT16374A TEST CIRCUIT TEST SWITCH tPLH, tPHL Open tPZL, tPLZ VCC tPZH, tPHZ GND C L = 15/50 pF or equivalent (includes jig and probe capacitance) R L = R1 = 1KΩ or equivalent R T = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1 : PROPAGATION DELAYS, SETUP AND HOLD TIMES, MAXIMUM CLOCK FREQUENCY (f=1MHz; 50% duty cycle) 6/9 74VHCT16374A WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) WAVEFORM 3 : CLOCK PULSE WIDTH (f=1MHz; 50% duty cycle) 7/9 74VHCT16374A TSSOP48 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. 1.1 A1 0.05 0.043 0.15 A2 MAX. 0.002 0.006 0.9 0.035 b 0.17 0.27 0.0067 0.011 c 0.09 0.20 0.0035 0.0079 D 12.4 12.6 0.408 0.496 E 7.95 8.25 0.313 0.325 E1 6.0 6.2 0.236 0.244 e 0.5 BSC 0.0197 BSC K 0° 8° 0° 8° L 0.50 0.75 0.020 0.030 A A2 A1 b K e L E c D E1 PIN 1 IDENTIFICATION 1 7065588A 8/9 74VHCT16374A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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