ESDA6V1-4F1 ® A.S.D.™ APPLICATIONS Where transient overvoltage protection in ESD sensitive equipment is required, such as : Computers Printers Communication systems GSM handsets and accessories Other telephone sets Set top boxes ■ ■ QUAD TRANSIL™ ARRAY FOR ESD PROTECTION 3 2 1 A Z1 GND Z3 B Z2 GND Z4 ■ ■ ■ ■ DESCRIPTION The ESDA6V1-4F1 is a 4-bit wide monolithic suppressor designed to protect against ESD components which are connected to data and transmission lines. It clamps the voltage just above the logic level supply for positive transients, and to a diode forward voltage drop below ground for negative transients. Flip Chip (Bump side) FUNCTIONAL DIAGRAM A3 A2 A1 B3 B2 B1 FEATURES ■ ■ ■ ■ 4 Unirectional transil functions Breakdown voltage: VBR = 6.1Vmin Low leakage current < 10 µA Very low PCB space consuming BENEFITS ■ ■ ■ > ± 15kV ESD Protection High integration Suitable for high density boards ESD RESPONSE TO IEC61000-4-2 (air discharge 16kV, positive surge) COMPLIES WITH THE FOLLOWING STANDARDS: - IEC61000-4-2: Level 4 15 kV (air discharge) 8 kV (contact discharge) - MIL STD 883E-Method 3015-6: class3 (Human body model) July 2002 - Ed: 2A 1/6 ESDA6V1-4F1 ABSOLUTE MAXIMUM RATINGS (Tamb = 25°C) Symbol Test conditions Value Unit VPP ESD discharge - MIL STD 883E - Method 3015-6 IEC61000-4-2 air discharge IEC61000-4-2 contact discharge ±25 ±15 ±8 kV PPP Peak pulse power (8/20µs) 150 W Junction temperature 150 °C -55 to +150 °C 260 °C -40 to +85 °C Tj Tstg Storage temperature range TL Lead solder temperature (10 seconds duration) Top Operating temperature range ELECTRICAL CHARACTERISTICS (Tamb = 25°C) Symbol Parameter I VRM Stand-off voltage VBR Breakdown voltage VCL Clamping voltage IRM Leakage current IPP Peak pulse current αT Voltage temperature coefficient C Capacitance per line Rd Dynamic impedance VF Forward voltage drop VCLVBR VRM Slope = 1/Rd IPP VBR Type ESDA6V1- 4F1 min. @ IR max. IRM @ VRM Rd T C max. typ. max max note 1 note 2 0V bias V V mA µA V mΩ 10-4/°C pF 6.1 7.2 1 10 5 350 6 250 Note 1: Square pulse IPP = 15A, tp = 2.5µs Note 2: ∆VBR = αT * (Tamb - 25) * VBR(25°C) 2/6 V IRM IR ESDA6V1-4F1 Fig. 1: Peak power dissipation versus initial junction temperature Fig. 2: Peak pulse power versus exponential pulse duration (Tj initial = 25°C) Ppp[Tj initial]/Ppp[Tj initial=25°C] 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 Ppp(W) 1000 100 Tj initial(°C) 0 25 50 75 100 tp(µs) 125 150 175 Fig. 3: Clamping voltage versus peak pulse current (Tj initial = 25°C). Rectangular waveform tP = 2.5µs. 10 1 10 100 Fig. 4: Capacitance versus reverse applied voltage (typical values). C(pF) Ipp(A) 250 50.0 F=1MHz Vosc=30mV tp = 2.5µs 225 10.0 200 175 150 1.0 125 100 Vcl(V) 0.1 0 5 10 15 20 25 30 75 0.0 VR(V) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Fig. 5: Relative variation of leakage current versus junction temperature (typical values). IR[Tj] / IR[Tj=25°C] 1.8 1.6 1.4 1.2 Tj(°C) 1.0 25 50 75 100 125 150 3/6 ESDA6V1-4F1 CALCULATION OF THE CLAMPING VOLTAGE USE OF THE DYNAMIC RESISTANCE The ESDA6V1-4F1 has been designed to clamp fast spikes like ESD. Generally the PCB designers need to calculate easily the clamping voltage VCL. This is why we give the dynamic resistance in addition to the classical parameters. The voltage across the protection cell can be calculated with the following formula: V CL = V BR + Rd ⋅ I PP Where IPP is the peak current through the ESDA cell. DYNAMIC RESISTANCE MEASUREMENT The short duration of the ESD has led us to prefer a more adapted test wave, as below defined, to the classical 8/20 µs and 10/1000 µs surges I IPP t 2µs 2.5 µs 2.5 µs duration measurement wave As the value of the dynamic resistance remains stable for a surge duration lower than 20µs, the 2.5µs rectangular surge is well adapted. In addition both rise and fall times are optimised to avoid any parasitic phenomenon during the measurement of Rd. ESD PROTECTION WITH ESDA6V1-4F1 With the focus of lowering the operation levels, the problem of malfunction caused by the environment is critical. Electrostatic discharge (ESD) is a major cause of failure in electronic system. Transient Voltage Suppressors are an ideal choice for ESD protection and have proven capable in suppressing ESD events. They are capable of clamping the incoming transient to a low enough level such that damage to the protected semiconductor is prevented. Surface mount TVS arrays offer the best choice for minimal lead inductance. They serve as parallel protection elements, connected between the signal line to ground. As the transient rises above the operating voltage of the device, the TVS array becomes a low impedance path diverting the transient current to ground. 4/6 IC to be pr ot Connector ec ted ESDA6V1-4F1 ESDA6V1-4F1 The ESDA6V1-4F1 array is the ideal product for use as board level protection of ESD sensitive semiconductor components. The Flip Chip package makes the ESDA6V1-4F1 device some of the smallest ESD protection devices available. It also allows design flexibility in the design of “crowded” boards where the space saving is at a premium. This enables to shorten the routing and can contribute to improved ESD performance. LAYOUT RECOMMENDATIONS 500µm 500µm 500µm Copper Pad Cu - Ni (2-6µm) - Au (0.2µm max) ∅ = 250µm (300µm max) Ø =320µm max (stencil aperture) Solder paste Stencil Design thickness of 150µm Ø =340µm min (for 300µm ∅ pad Non Solder mask opening Circuit board layout is a critical design step in the suppression of ESD induced transients. The following guidelines are recommended : The ESDA6V1-4F1 should be placed as close as possible to the input terminals or connectors. Minimise the path length between the ESD suppressor and the protected device Minimise all conductive loops, including power and ground loops The ESD transient return path to ground should be kept as short as possible. Use ground planes whenever possible. ■ ■ ■ ■ ■ 5/6 ESDA6V1-4F1 PACKAGE MECHANICAL DATA Flip Chip (all dimensions in µm) 500 650 500 1070 MARKING ® Die size: (1570 ± 50) x (1070 ± 50) Die height (including bumps): 650 ± 40 Bump diameter: 315 ± 50 Pitch: 500 ± 50 EB 1570 MARKING Type Marking Delivery mode Order Code Base qty ESDA6V1-4F1 EB Tape & reel ESDA6V1-4F1 5000 Note: For PCB design, assembly recommendations and packing information please refer to Application note AN1235. (“Flip-Chip: Package Description and recommendations for use”) Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2002 STMicroelectronics - Printed in Italy - All rights reserved. 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