ESDA25LY Automotive dual Transil™ array for ESD protection Features ■ 2 Unidirectional Transil functions ■ Low leakage current: 1 µA @ 24 V ■ 300 W peak pulse power (8/20 µs) 3 2 1 Benefits ■ High ESD protection level: up to 25 kV ■ High integration ■ Suitable for high density boards SOT23-3L Figure 1. 1 Complies with the following standards ■ ■ Functional diagram IEC 61000-4-2 level 4 – 15 kV (air discharge) – 8 kV (contact discharge) 3 MIL STD 883G - Method 3015-7 Class 3B – (human body model) 2 Applications Where transient overvoltage protection in ESD sensitive equipment is required, such as : ■ Computers ■ Printers ■ Communication systems and cellular phones It is particulary recommended for the RS232 I/O port protection where the line interface withstands only with 2 kV ESD surges. Description The ESDA25LY is a dual monolithic voltage suppressor designed to protect components which are connected to data and transmission lines against ESD. It clamps the voltage just above the logic level supply for positive transients, and to a diode drop below ground for negative transients. It can also work as bidirectionnal suppressor by connecting only pin1 and 2. TM: Transil is a trademark of STMicroelectronics. A.S.D.™= Application Specific Discretes February 2010 Doc ID 16914 Rev 1 1/10 www.st.com 10 Characteristics ESDA25LY 1 Characteristics Table 1. Absolute maximum ratings (Tamb = 25°C) Symbol Parameter MIL STD 883E-Method 3015-7 IEC 61000-4-2 air discharge IEC 61000-4-2 contact discharge Value Unit 25 16 9 kV VPP ESD discharge PPP Peak pulse power (8/20 µs) 300 W Junction temperature 150 °C -55 to +150 °C 260 °C -40 to +125 °C Tj Tstg Storage temperature range TL Maximum lead temperature for soldering during 10 s at 5 mm for case Top Operating temperature range Figure 2. Electrical characteristics (definitions) I Symbol VBR VCL IRM VRM IF IPP IR VF Rd αT Table 2. Parameter Breakdown voltage Clamping voltage Leakage current @ VRM Stand-off voltage Forward current Peak pulse current Breakdown current Forward voltage drop Dynamic impedance Voltage temperature = = = = = = = = = = ESDA25LY V IRM IR Slope = 1/Rd IRM @ VRM max. VF@ IF IPP max. Rd αT C typ. note(1) max. note(2) typ. 0V bias min. max. V V mA µA V V mA mΩ 10-4/C pF 25 30 1 1 24 1.2 10 1000 10 50 1. Square pulse, Ipp = 15 A, tp = 2.5 µs. 2. Δ VBR = αT* (Tamb - 25 °C) * VBR (25 °C) 2/10 VF VCL VBR VRM Electrical characteristics (values, Tamb = 25 °C) VBR @ IR Order code IF Doc ID 16914 Rev 1 ESDA25LY Figure 3. 1.1 Characteristics Peak power dissipation versus initial junction temperature Figure 4. PPP[Tj initial] / PPP[Tj initial = 25 °C] 3000 Peak pulse power versus exponential pulse duration (Tj initial = 25 °C) PPP(W) Tj initial = 25°C 1.0 0.9 1000 0.8 0.7 0.6 0.5 100 0.4 0.3 0.2 0.1 Tj initial (°C) 0.0 0 25 Figure 5. 50.0 50 75 100 125 150 Clamping voltage versus peak pulse current (Tj initial = 25 °C, rectangular waveform, tp = 2.5µs) tp(µs) 10 1 10 Figure 6. 100 Capacitance versus reverse applied voltage (typical values) C(pF) IPP(A) 200 F = 1 MHz VOSC = 30 mVRMS Tj = 25 °C 100 10.0 tp = 2.5 µs 50 1.0 20 0.1 0 VCL(V) 5 10 Figure 7. 200 15 20 25 30 35 40 45 50 55 60 65 70 75 80 Relative variation of leakage current versus junction temperature (typical values) VR(V) 10 1 2 Figure 8. IR[Tj] / IR[Tj = 25 °C] 5.00 5 10 20 50 Peak forward voltage drop versus forward current (typical values) IFM(A) Tj = 25 °C 100 1.00 10 0.10 1 25 Tj(°C) 50 75 100 125 0.01 0.0 VFM(V) 0.5 Doc ID 16914 Rev 1 1.0 1.5 2.0 2.5 3.0 3.5 4.0 3/10 Calculation of the clamping voltage ESDA25LY 2 Calculation of the clamping voltage 2.1 Use of the dynamic resistance The ESDA family has been designed to clamp fast spikes like ESD. Generally the PCB designers need to calculate easily the clamping voltage VCL. This is why we give the dynamic resistance in addition to the classical parameters. The voltage across the protection cell can be calculated with the following formula: VCL = VBR + Rd IPP Where Ipp is the peak current through the ESDA cell. 3 Dynamic resistance measurement The short duration of the ESD has led us to prefer a more adapted test wave, as below defined, to the classical 8/20 µs and 10/1000 µs surges. As the value of the dynamic resistance remains stable for a surge duration lower than 20 µs, the 2.5 µs rectangular surge is well adapted. In addition both rise and fall times are optimized to avoid any parasitic phenomenon during the measurement of Rd. Figure 9. 2.5 µs duration measurement wave I IPP t 2µs tp = 2.5µs 4/10 Doc ID 16914 Rev 1 ESDA25LY 4 ESD Protection by ESDA25LY ESD Protection by ESDA25LY Electrostatic discharge (ESD) is a major cause of failure in electronic systems. Transient Voltage Suppressors (TVS) are an ideal choice for ESD protection. They are capable of clamping the incoming transient to a low enough level such that damage to the protected semiconductor is prevented. Surface mount TVS arrays offer the best choice for minimal lead inductance. They serve as parallel protection elements, connected between the signal line to ground. As the transient rises above the operating voltage of the device, the TVS array becomes a low impedance path diverting the transient current to ground. The ESDA25LY array is the ideal board level protection of ESD sensitive semiconductor components. The tiny SOT23 package allows design flexibility in the design of high density boards where the space saving is at a premium. This enables to shorten the routing and contributes to hardening againt ESD. Figure 10. ESD protection diagram I/O I/O I/O I/O ESD sensitive device GND 2 * ESDA25LY Doc ID 16914 Rev 1 5/10 Circuit board layout 5 ESDA25LY Circuit board layout Circuit board layout is a critical design step in the suppression of ESD induced transients. The following guidelines are recommended : 6/10 ● The ESDA25LY should be placed as close as possible to the input terminals or connectors. ● The path length between the ESD suppressor and the protected line should be minimized ● All conductive loops, including power and ground loops should be minimized ● The ESD transient return path to ground should be kept as short as possible. ● Ground planes should be used whenever possible. Doc ID 16914 Rev 1 ESDA25LY 6 Ordering information scheme Ordering information scheme Figure 11. Ordering information scheme ESDA 25 LY ESD Array Breakdown Voltage 25 V = 25 Volts min. Packages L = SOT23-3L Y = Automotive grade Doc ID 16914 Rev 1 7/10 Package information 7 ESDA25LY Package information ● Epoxy meets UL94, V0 ● Lead-free packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 3. SOT23-3L dimensions Dimensions Ref. A Inches Min. Max. Min. Max. A 0.89 1.4 0.035 0.055 A1 0 0.1 0 0.004 B 0.3 0.51 0.012 0.02 c 0.085 0.18 0.003 0.007 D 2.75 3.04 0.108 0.12 e 0.85 1.05 0.033 0.041 e1 1.7 2.1 0.067 0.083 E 1.2 1.6 0.047 0.063 H 2.1 2.75 0.083 0.108 E e B Millimeters D e1 S A1 L c H L S 0.6 typ. 0.35 0.65 Figure 12. Footprint (dimensions in mm) 0.95 0.61 1.26 0.73 8/10 3.25 Doc ID 16914 Rev 1 0.024 typ. 0.014 0.026 ESDA25LY 8 Ordering information Ordering information Table 4. 9 Ordering information Order code Marking Package Weight Base qty Delivery mode ESDA25LY EL2Y SO23-3L 0.01 g 3000 Tape and reel Revision history Table 5. Document revision history Date Revision 01-Feb-2010 1 Changes First issue. Doc ID 16914 Rev 1 9/10 ESDA25LY Please Read Carefully: Information in this document is provided solely in connection with ST products. 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